GRM21BR60J226ME39 [ONSEMI]
3 MHz, 2 A Synchronous Buck Converter;
| 型号： | GRM21BR60J226ME39 |
| 厂家： | 
ONSEMI |
| 描述： | 3 MHz, 2 A Synchronous Buck Converter |
| 文件： | 总16页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP6323, NCV6323
3 MHz, 2 A Synchronous
Buck Converter
High Efficiency, Low Ripple, Adjustable
Output Voltage
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The NCP/NCV6323 is a synchronous buck converter which is
optimized to supply different sub systems of portable applications
powered by one cell Li−ion or three cell Alkaline/NiCd/NiMH
batteries. The devices are able to deliver up to 2 A on an external
adjustable voltage. Operation with 3 MHz switching frequency allows
employing small size inductor and capacitors. Input supply voltage
feedforward control is employed to deal with wide input voltage
range. Synchronous rectification offer improved system efficiency.
The NCP/NCV6323 is in a space saving, low profile 2.0 x 2.0 x
0.75 mm WDFN−8 package.
MARKING
DIAGRAMS
1
1
23 MG
WDFN8
(NCV6323)
CASE 511BT
G
1
1
Features
NN MG
• 2.5 V to 5.5 V Input Voltage Range
• External Adjustable Voltage
• Up to 2 A Output Current
• 3 MHz Switching Frequency
• Synchronous Rectification
• Enable Input
• Power Good Output Option
• Soft Start
• Over Current Protection
WDFN8
(NCP6323)
CASE 511BE
G
23/NN = Specific Device Code
M
G
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT
• Active Discharge When Disabled
• Thermal Shutdown Protection
• WDFN−8, 2 x 2 mm, 0.5 mm Pitch Package
• Maximum 0.8 mm Height for Super Thin Applications
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PGND
1
2
3
4
8
7
6
5
PVIN
AVIN
SW
AGND
FB
9
PG
EN
• This is a Pb−Free Device
Typical Applications
(Top View)
• Cellular Phones, Smart Phones, and PDAs
• Portable Media Players
• Digital Still Cameras
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
• Wireless and DSL Modems
• USB Powered Devices
• Point of Load
• Game and Entertainment System
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2015 − Rev. 4
NCV6323/D
NCP6323, NCV6323
NCP/NCV6323
1uH
Vo = 0.6V to Vin
Vin = 2.5 V to 5.5 V
Rpg
PGND PVIN
Cin
Cout
10uF
SW
AVIN
10uF
1M
Power Good
Cfb
PG
AGND
FB
R1
R2
Enable
EN
(a) Power Good Output Option (NCP/NCV6323)
Figure 1. Typical Application Circuit
PIN DESCRIPTION
Pin
Name
Type
Description
1
PGND
Power
Ground
Power Ground for power, analog blocks. Must be connected to the system ground.
2
3
4
5
6
7
SW
AGND
FB
Power
Output
Switch Power pin connects power transistors to one end of the inductor.
Analog
Ground
Analog Ground analog and digital blocks. Must be connected to the system ground.
Analog
Input
Feedback Voltage from the buck converter output. This is the input to the error amplifier. This pin
is connected to the resistor divider network between the output and AGND.
EN
Digital
Input
Enable of the IC. High level at this pin enables the device. Low level at this pin disables the de-
vice.
PG
Digital
Output
It is open drain output. Low level at this pin indicates the device is not in power good, while high
impedance at this pin indicates the device is in power good.
AVIN
Analog
Input
Analog Supply. This pin is the analog and the digital supply of the device. An optional 1 mF or lar-
ger ceramic capacitor bypasses this input to the ground. This capacitor should be placed as close
as possible to this input.
8
9
PVIN
PAD
Power
Input
Power Supply Input. This pin is the power supply of the device. A 10 mF or larger ceramic capacit-
or must bypass this input to the ground. This capacitor should be placed as close a possible to
this input.
Exposed
Pad
Exposed Pad. Must be soldered to system ground to achieve power dissipation performances.
This pin is internally unconnected
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCP6323DMTAATBG
NN
WDFN8
(Pb−Free)
3000 / Tape & Reel
NCV6323BMTAATBG
23
WDFN8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NCP6323, NCV6323
L
Vo
Vin
PVIN
8
SW
2
1uH
Cin
Cout
10uF
10uF
PWM
AVIN
7
UVLO
Control
PGND
1
Cfb
R1
FB
4
Enable
EN
5
Error
Amp
Logic Control
&
R2
Rpg
1M
Current Limit
&
Power Good
PG
6
AGND
3
Thermal
Shutdown
PG
Reference
Voltage
Figure 2. Functional Block Diagram
MAXIMUM RATINGS
Value
Min
Max
7.0
Rating
Symbol
, V
Unit
Input Supply Voltage to GND
Switch Node to GND
EN, PG to GND
V
−0.3
−0.3
−0.3
−0.3
V
PVIN AVIN
V
SW
7.0
V
V
V
EN
, V
PG
7.0
FB to GND
V
FB
7.0
V
Human Body Model (HBM) ESD Rating are (Note 1)
Machine Model (MM) ESD Rating (Note 1)
Latchup Current (Note 2)
ESD HBM
ESD MM
2000
200
100
125
V
V
I
LU
−100
−40
mA
°C
°C
Operating Junction Temperature Range (Note 3)
Operating Ambient Temperature Range
T
J
NCP6323
NCV6323
T
A
−40
−40
85
125
Storage Temperature Range
T
−55
150
°C
°C/W
°C/W
°C/W
W
STG
Thermal Resistance Junction−to−Top Case (Note 4)
Thermal Resistance Junction−to−Board (Note 4)
Thermal Resistance Junction−to−Ambient (Note 4)
Power Dissipation (Note 5)
R
R
R
12
30
62
1.6
1
q
JC
q
JB
q
JA
D
P
Moisture Sensitivity Level (Note 6)
MSL
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) 200 V per JEDEC standard: JESD22−A115.
2. Latchup Current per JEDEC standard: JESD78 Class II.
3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. The thermal resistance values are dependent of the PCB heat dissipation. The board used to drive this data was an 80x50 mm NCP6324EVB
board. It is a multilayer board with 1 ounce internal power and ground planes and 2−1 ounce copper traces on top and bottom of the board.
If the copper traces of top and bottom are 1 ounce too, R
5. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected.
6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
= 11°C/W, R
= 30°C/W, and R
= 72°C/W.
q
q
q
JC
JB
JA
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3
NCP6323, NCV6323
ELECTRICAL CHARACTERISTICS (V = 3.6 V, V
= 1.8 V, L = 1 mH, C = 10 mF, typical values are referenced to T = 25°C, Min
IN
OUT
J
and Max values are referenced to T up to 125°C, unless other noted.)
J
Symbol
Characteristics
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE
V
IN
Input Voltage V Range
(Note 7)
2.5
−
5.5
V
IN
SUPPLY CURRENT
I
V
IN
V
IN
Quiescent Supply Current
Shutdown Current
EN high, no load, Forced PWM Mode
EN low (Note 9 for NCP6323)
−
−
5.7
−
−
1
mA
Q
I
mA
SD
OUTPUT VOLTAGE
V
Output Voltage Range
FB Voltage
(Note 8)
0.6
594
−
−
V
V
OUT
IN
V
PWM Mode
600
−0.5
606
−
mV
%/A
FB
FB Voltage in Load Regulation
V
IN
= 3.6 V, I
from 200 mA to I
,
OUT
OUTMAX
PWM mode (Note 8)
= 200 mA, V from MAX (V +
NOM
FB Voltage in Line Regulation
Maximum Duty Cycle
I
−
−
0
−
−
%/V
%
OUT
IN
0.5 V, 2.3 V) to 5.5 V, PWM mode (Note 8)
D
(Note 8)
100
MAX
OUTPUT CURRENT
I
Output Current Capability
(Note 8)
2.0
2.3
−
−
A
A
A
OUTMAX
I
Output Peak Current Limit P−Channel
Output Peak Current Limit N−Channel
2.8
0.9
3.3
LIMP
I
LIMN
VOLTAGE MONITOR
V
V
V
UVLO Falling Threshold
UVLO Hysteresis
−
−
2.4
200
92
V
mV
%
INUV−
INHYS
IN
IN
V
60
87
140
90
V
Power Good Low Threshold
V
OUT
falls down to cross the threshold
(percentage of FB voltage)
PGL
V
Power Good Hysteresis
V
rises up to cross the threshold
0
5
7
%
PGHYS
OUT
(percentage of Power Good Low Threshold
(V ) voltage)
PGL
Td
Power Good High Delay in Start Up
Power Good Low Delay in Shut Down
From EN rising edge to PG going high.
−
−
1.15
8
−
−
ms
PGH1
Td
From EN falling edge to PG going low.
(Note 8)
ms
PGL1
Td
Power Good High Delay in Regulation From V going higher than 95% nominal
−
−
5
8
−
−
ms
ms
PGH
FB
level to PG going high.
Not for the first time in start up. (Note 8)
Td
Power Good Low Delay in Regulation
From V going lower than 90% nominal
PGL
FB
level to PG going low. (Note 8)
Voltage at PG pin with 5 mA sink current
3.6 V at PG pin when power good valid
VPG_L
PG_LK
Power Good Pin Low Voltage
−
−
−
−
0.3
V
Power Good Pin Leakage Current
100
nA
INTEGRATED MOSFETs
R
High−Side MOSFET ON Resistance
V
V
= 3.6 V (Note 9 for NCP6323)
−
−
160
130
200
−
mW
mW
ON_H
IN
= 5 V (Note 9 for NCP6323)
IN
R
Low−Side MOSFET ON Resistance
V
IN
= 3.6 V (Note 9 for NCP6323)
= 5 V (Note 9 for NCP6323)
110
100
140
−
ON_L
V
IN
SWITCHING FREQUENCY
Normal Operation Frequency
F
SW
2.7
3.0
3.3
MHz
7. Operation above 5.5 V input voltage for extended periods may affect device reliability. At the first power−up, input voltage must be > 2.6 V.
8. Guaranteed by design, not tested in production.
9. Maximum value applies for T = 85°C.
J
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4
NCP6323, NCV6323
ELECTRICAL CHARACTERISTICS (V = 3.6 V, V
= 1.8 V, L = 1 mH, C = 10 mF, typical values are referenced to T = 25°C, Min
IN
OUT
J
and Max values are referenced to T up to 125°C, unless other noted.)
J
Symbol
Characteristics
Test Conditions
Min
Typ
Max
Unit
SOFT START
T
SS
Time from EN to 90% of
output voltage target
ms
Soft−Start Time
NCV6323
NCP6323D
NCP6323D
0
0
0.4
1
1
Soft−Start Time
Soft−Start Time
0.54
0.24
Time from 10% to 90% of
output voltage target
0.16
0.3
CONTROL LOGIC
V
EN Input High Voltage
EN Input Low Voltage
EN Input Hysteresis
EN Input Bias Current
1.1
−
−
−
−
0.4
−
V
V
EN_H
V
EN_L
V
−
270
0.1
mV
mA
EN_HYS
EN_BIAS
I
1
OUTPUT ACTIVE DISCHARGE
R_DIS Internal Output Discharge Resistance
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
from SW to PGND
75
500
700
W
T
−
−
170
25
−
−
°C
°C
SD
T
SD_HYS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NCP6323, NCV6323
TYPICAL OPERATING CHARACTERESTICS
2
1.5
1
2
V
IN
V
IN
V
IN
= 5.5 V
= 3.6 V
= 2.5 V
1.5
1
0.5
0
0.5
0
2.5
3
3.5
4
4.5
5
5.5
−40
−15
10
35
60
85
V
IN
(V)
Temperature (°C)
Figure 3. Shutdown Current vs. Input Voltage
Figure 4. Shutdown Current vs. Temperature
(EN = Low, VIN = 3.6 V)
(EN = Low, TA = 255C)
8
7.5
7
8
7.5
7
V
IN
V
IN
V
IN
= 5.5 V
= 3.6 V
= 2.5 V
6.5
6
6.5
6
5.5
5
5.5
5
4.5
4
4.5
4
2.5
3
3.5
4
4.5
5
5.5
−40
−15
10
35
60
85
V
IN
(V)
V
IN
(V)
Figure 5. PWM Quiescent Current vs. Input
Voltage (EN = High, Open Loop, VOUT = 1.8 V,
TA = 255C)
Figure 6. PWM Quiescent Current vs.
Temperature (EN = High, Open Loop,
V
OUT = 1.8 V, VIN = 3.6 V)
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
V
IN
V
IN
V
IN
= 5.5 V
= 3.6 V
= 2.5 V
V
IN
V
IN
V
IN
= 5.5 V
= 3.6 V
= 2.5 V
0
400
800
1200
(mA)
1600
2000
0
400
800
1200
(mA)
1600
2000
I
I
OUT
OUT
Figure 7. Efficiency vs. Output Current and
Figure 8. Efficiency vs. Output Current and
Input Voltage (VOUT = 1.05 V, TA = 255C)
Input Voltage (VOUT = 1.8 V, TA = 255C)
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6
NCP6323, NCV6323
TYPICAL OPERATING CHARACTERESTICS
100
95
100
95
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
V
IN
V
IN
= 4.5 V
= 5.5 V
V
IN
V
IN
= 3.6 V
= 5.5 V
55
50
0
400
800
1200
(mA)
1600
2000
0
400
800
1200
(mA)
1600
2000
I
I
OUT
OUT
Figure 9. Efficiency vs. Output Current and
Figure 10. Efficiency vs. Output Current and
Input Voltage (VOUT = 3.3 V, TA = 255C)
Input Voltage (VOUT = 4 V , TA = 255C)
Figure 11. Output Ripple Voltage in PWM Mode
(VIN = 3.6 V, VOUT = 1.8 V, IOUT = 1 A, L=1 mH,
Figure 12. Load Transient Response (VIN = 3.6 V,
= 1.8 V, IOUT = 500 mA to 1500 mA, L = 1 mH,
V
OUT
C
OUT = 10 mF)
C
OUT = 10 mF)
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7
NCP6323, NCV6323
TYPICAL OPERATING CHARACTERESTICS
Figure 13. Power Up Sequence and Inrush Current in
Figure 14. Power Up Sequence and Power Good
Input (VIN = 3.6 V, VOUT = 1.8 V, IOUT = 0 A,
(VIN = 3.6 V, VOUT = 1.8 V, IOUT = 0 A, L = 1 mH,
L = 1 mH, COUT = 10 mF)
COUT = 10 mF)
Figure 15. Power Down Sequence and Active Output
Discharge (VIN = 3.6 V, VOUT = 1.8 V, IOUT = 0 A,
L = 1 mH, COUT = 10 mF)
Figure 16. Soft−start Time for NCP6323D
(VIN = 4.2 V, VOUT = 1.1 V, IOUT = 0 A,
L = 1 mH,COUT = 10 mF)
Figure 17. Soft−start Time for NCV6323
(VIN = 4.2 V, VOUT = 1.8 V, IOUT = 0 A,
L = 1 mH,COUT = 10 mF)
Figure 18. Soft−start Time for NCP6323D
(VIN = 4.2 V, VOUT = 1.8 V, IOUT = 0 A,
L = 1 mH,COUT = 10 mF)
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8
NCP6323, NCV6323
DETAILED DESCRIPTION
General
N−MOSFET operates as synchronous rectifier and its
The NCP/NCV6323 is a synchronous buck converter
turn−on signal is complimentary to that of the P−MOSFET.
which is optimized to supply different sub−systems of
portable applications powered by one cell Li−ion or three
cell Alkaline/NiCd/NiMH batteries. The devices are able to
deliver up to 2 A on an external adjustable voltage.
Operation with 3 MHz switching frequency allows
employing small size inductor and capacitors. Input supply
voltage feedforward control is employed to deal with wide
input voltage range. Synchronous rectification offer
improved system efficiency.
Undervoltage Lockout
The input voltage VIN must reach or exceed 2.5 V
(typical) before the NCP/NCV6323 enables the converter
output to begin the start up sequence. The UVLO threshold
hysteresis is typically 100 mV.
Enable
The NCP/NCV6323 has an enable logic input pin EN. A
high level (above 1.1 V) on this pin enables the device to
active mode. A low level (below 0.4 V) on this pin disables
the device and makes the device in shutdown mode. There
is an internal filter with 5 ms time constant. The EN pin is
pulled down by an internal 10 nA sink current source. In
most of applications, the EN signal can be programmed
independently to VIN power sequence.
PWM Mode Operation
In medium and heavy load range, the inductor current is
continuous and the device operates in PWM mode with fixed
switching frequency, which has a typical value of 3 MHz. In
this mode, the output voltage is regulated by on−time pulse
width modulation of an internal P−MOSFET. An internal
Figure 19. Power Good and Active Discharge Timing Diagram
Power Good Output
Soft−Start
The device monitors the output voltage and provides a
power good output signal at the PG pin. This pin is an
open−drain output pin. To indicate the output of the
converter is established, a power good signal is available.
The power good signal is low when EN is high but the output
voltage has not been established. Once the output voltage of
the converter drops out below 90% of its regulation during
operation, the power good signal is pulled low and indicates
a power failure. A 5% hysteresis is required on power good
comparator before signal going high again.
A soft start limits inrush current when the converter is
enabled. After a minimum 300 ms delay time following the
enable signal, the output voltage starts to ramp up in 100 ms
(NCV6323) / 240 ms (NCP6323) (for external adjustable
voltage devices) or with a typical 10 V/ms slew rate (for
fixed voltage devices).
Active Output Discharge
An output discharge operation is active in when EN is low.
A discharge resistor (500 W typical) is enabled in this
condition to discharge the output capacitor through SW pin.
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NCP6323, NCV6323
Cycle−by−Cycle Current Limitation
Negative Current Protection
The NCP/NCV6323 protects the device from over current
with a fixed−value cycle−by−cycle current limitation. The
typical peak current limit ILMT is 2.8 A. If inductor current
exceeds the current limit threshold, the P−MOSFET will be
turned off cycle−by−cycle. The maximum output current
can be calculated by
The NCP/NCV6323 includes a 1 A negative current
protection. It helps to protect the internal NMOS in case of
applications which require high output capacitor value.
Thermal Shutdown
The NCP/NCV6323 has a thermal shutdown protection to
protect the device from overheating when the die
temperature exceeds 170°C. After the thermal protection is
triggered, the fault state can be ended by re−applying VIN
and/or EN when the temperature drops down below 125°C.
ǒ
Ǔ
VOUT @ VIN * VOUT
(eq. 1)
IMAX + ILMT
*
2 @ VIN @ fSW @ L
where VIN is input supply voltage, VOUT is output voltage,
L is inductance of the filter inductor, and f
normal switching frequency.
is 3 MHz
SW
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10
NCP6323, NCV6323
APPLICATION INFORMATION
Output Filter Design Considerations
The output filter introduces a double pole in the system at
a frequency of
to 50% of the maximum output current IOUT_MAX for a
trade−off between transient response and output ripple. The
inductance corresponding to the given current ripple is
1
ǒ
Ǔ
VIN * VOUT @ VOUT
fLC
+
(eq. 2)
(eq. 3)
Ǹ
L +
2 @ p @ L @ C
VIN @ fSW @ IL_PP
The internal compensation network design of the
NCP/NCV6323 is optimized for the typical output filter
comprised of a 1.0 mH inductor and a 10 mF ceramic output
capacitor, which has a double pole frequency at about
50 kHz. Other possible output filter combinations may have
a double pole around 50 kHz to have optimum operation
with the typical feedback network. Normal selection range
of the inductor is from 0.47 mH to 4.7 mH, and normal
selection range of the output capacitor is from 4.7 mF to
22 mF.
The selected inductor must have high enough saturation
current rating to be higher than the maximum peak current
that is
IL_PP
(eq. 4)
IL_MAX + IOUT_MAX
)
2
The inductor also needs to have high enough current
rating based on temperature rise concern. Low DCR is good
for efficiency improvement and temperature rise reduction.
Table 1 shows some recommended inductors for high power
applications and Table 2 shows some recommended
inductors for low power applications.
Inductor Selection
The inductance of the inductor is determined by given
peak−to−peak ripple current IL_PP of approximately 20%
Table 1. LIST OF RECOMMENDED INDUCTORS FOR HIGH POWER APPLICATIONS
Case Size
(mm)
Rated Current (mA)
(Inductance Drop)
Manufacturer
MURATA
Part Number
L (mH)
2.2
Structure
Wire Wound
Wire Wound
Wire Wound
LQH44PN2R2MP0
LQH44PN1R0NP0
LQH32PNR47NNP0
4.0 x 4.0 x 1.8
4.0 x 4.0 x 1.8
3.0 x 2.5 x 1.7
2500 (−30%)
MURATA
1.0
2950 (−30%)
MURATA
0.47
3400 (−30%)
Table 2. LIST OF RECOMMENDED INDUCTORS FOR LOW POWER APPLICATIONS
Case Size
(mm)
Rated Current (mA)
(Inductance Drop)
1320 (−30%)
2000 (−30%)
1150 (−30%)
Manufacturer
MURATA
MURATA
TDK
Part Number
L (mH)
2.2
Structure
Wire Wound
Wire Wound
Wire Wound
Wire Wound
LQH44PN2R2MJ0
LQH44PN1R0NJ0
VLS201612ET−2R2
VLS201612ET−1R0
4.0 x 4.0 x 1.1
4.0 x 4.0 x 1.1
2.0 x 1.6 x 1.2
2.0 x 1.6 x 1.2
1.0
2.2
TDK
1.0
1650 (−30%)
Output Capacitor Selection
operation mode, the three ripple components can be
obtained by
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
a given peak−to−peak ripple current IL_PP in the inductor
of the output filter, the output voltage ripple across the
output capacitor is the sum of three ripple components as
below.
IL_PP
(eq. 6)
VOUT_PP(C)
+
8 @ C @ fSW
VOUT_PP(ESR) + IL_PP @ ESR
(eq. 7)
(eq. 8)
ESL
VOUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
VOUT_PP(ESL)
+
@ VIN
ESL ) L
(eq. 5)
and the peak−to−peak ripple current is
where VOUT_PP(C) is a ripple component by an equivalent
total capacitance of the output capacitors, VOUT_PP(ESR)
is a ripple component by an equivalent ESR of the output
capacitors, and VOUT_PP(ESL) is a ripple component by
an equivalent ESL of the output capacitors. In PWM
ǒ
Ǔ
VIN * VOUT @ VOUT
(eq. 9)
IL_PP
+
VIN @ fSW @ L
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11
NCP6323, NCV6323
2
In applications with all ceramic output capacitors, the
ǒ
Ǔ
IOUT_MAX @ D * D
(eq. 11)
(eq. 12)
main ripple component of the output ripple is
VOUT_PP(C). So that the minimum output capacitance can
be calculated regarding to a given output ripple requirement
VOUT_PP in PWM operation mode.
CIN_MIN +
VIN_PP @ fSW
where
VOUT
IL_PP
D +
VIN
(eq. 10)
CMIN
+
8 @ VOUT_PP @ fSW
In addition, the input capacitor needs to be able to absorb
the input current, which has a RMS value of
Input Capacitor Selection
Ǹ
IIN_RMS + IOUT_MAX @ D * D2
(eq. 13)
One of the input capacitor selection guides is the input
voltage ripple requirement. To minimize the input voltage
ripple and get better decoupling in the input power supply
rail, ceramic capacitor is recommended due to low ESR and
ESL. The minimum input capacitance regarding to the input
ripple voltage VIN_PP is
The input capacitor also needs to be sufficient to protect
the device from over voltage spike, and normally at least a
4.7 mF capacitor is required. The input capacitor should be
located as close as possible to the IC on PCB.
Table 3. LIST OF RECOMMENDED INPUT CAPACITORS AND OUTPUT CAPACITORS
Rated
Voltage
(V)
Case
Size
Height
Max (mm)
Manufacturer
MURATA
TDK
Part Number
C (mF)
22
Structure
MLCC
MLCC
MLCC
MLCC
MLCC
MLCC
MLCC
MLCC
MLCC
MLCC
MLCC
GRM21BR60J226ME39, X5R
C2012X5R0J226M, X5R
0805
0805
0805
0805
0603
0603
0603
0805
0805
0805
0805
1.4
1.25
1.35
1.25
0.9
6.3
6.3
10
22
MURATA
TDK
GRM21BR61A106KE19, X5R
C2012X5R1A106M, X5R
10
10
10
MURATA
TDK
GRM188R60J106ME47, X5R
C1608X5R0J106M, X5R
10
6.3
6.3
6.3
6.3
6.3
6.3
6.3
0.8
10
MURATA
Murata
TDK
GRM188R60J475KE19, X5R
GRM21BR70J106KE76, X7R
C2012X7R0J106K125AB, X7R
GRM21BR71A106KE51, X7R
C2012X7R1A106K125AC, X7R
0.87
1.4
4.7
10
1.45
1.4
10
Murata
TDK
10
1.45
10
Design of Feedback Network
the resistance from FB to AGND, which is used to program
the output voltage according to equation (14) once the value
of R1 has been selected. A capacitor Cfb needs to be
The output voltage is programmed by an external resistor
divider connected from V to FB and then to AGND, as
OUT
shown in the typical application schematic Figure 1(a). The
programmed output voltage is
employed between the V
and FB in order to provide
OUT
feedforward function to achieve optimum transient
response. Normal value range of Cfb is from 0 to 100 pF, and
a typical value is 15 pF for applications with the typical
output filter and R1 = 220 kW.
R1
@ ǒ1 ) Ǔ
(eq. 14)
VOUT + VFB
R2
Table 4 provides reference values of R1 and Cfb in case
of different output filter combinations. The final design may
need to be fine tuned regarding to application specifications.
where V is equal to the internal reference voltage 0.6 V,
FB
R1 is the resistance from V
to FB, which has a normal
OUT
value range from 50 kW to 1 MW and a typical value of
220 kW for applications with the typical output filter. R2 is
www.onsemi.com
12
NCP6323, NCV6323
Table 4. REFERENCE VALUES OF FEEDBACK NETWORKS (R1 AND CFB) FOR OUTPUT FILTER COMBINATIONS (L
and C)
R1 (kW)
L (mH)
Cfb (pF)
0.47
0.68
1
2.2
3.3
4.7
220
3
220
5
220
8
220
15
330
15
330
22
4.7
10
22
220
8
220
10
220
15
220
27
330
27
330
39
C (mF)
220
15
220
22
220
27
220
39
330
47
330
56
www.onsemi.com
13
NCP6323, NCV6323
LAYOUT CONSIDERATIONS
Electrical Layout Considerations
• Arrange a “quiet” path for output voltage sense and
feedback network, and make it surrounded by a ground
plane.
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
Thermal Layout Considerations
• Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high−frequency loop area. It is also
good for efficiency improvement.
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• The exposed pad must be well soldered on the board.
• The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and/or
underneath the exposed pad to connect the inner ground
layers to reduce thermal impedance.
• SW node should be a large copper pour, but compact
because it is also a noise source.
• Use large area copper especially in top layer to help
thermal conduction and radiation.
• It would be good to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Directly connect AGND pin to the exposed pad
and then connect to AGND ground plane through vias.
Try best to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation.
• Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
GND
VIN
P
P
P
P
P
P
PGND
SW
PVIN
1
2
3
4
8
7
6
5
A
AVIN
A
A
AGND
FB
MODE/PG
EN
F
P
L
P
P
Cfb
R1
O
O
P
P
P
P
P
P
F
R2
A
VOUT
GND
Figure 20. Recommended PCB Layout for Application Boards
www.onsemi.com
14
NCP6323, NCV6323
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511BE−01
ISSUE A
L
L
A
B
E
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE
CONSTRUCTIONS
2X
0.10 C
MILLIMETERS
DIM MIN
MAX
0.80
0.05
2X
0.10
C
A3
A
A1
A3
b
0.70
0.00
0.20 REF
TOP VIEW
EXPOSED Cu
MOLD CMPD
0.20
0.30
DETAIL B
A
D
2.00 BSC
0.10
C
D2
E
1.50
2.00 BSC
1.70
A3
C
A1
E2
e
K
0.80
0.50 BSC
0.25 REF
1.00
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.08
C
A1
SIDE VIEW
NOTE 4
L
L1
0.20
−−−
0.40
0.15
SEATING
PLANE
D2
DETAIL A
8X L
RECOMMENDED
SOLDERING FOOTPRINT*
1
4
8X
0.50
1.70
PACKAGE
OUTLINE
E2
b
5
8
K
8X
e
0.10
C
C
A
B
2.30
1.00
0.05
NOTE 3
BOTTOM VIEW
1
8X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
15
NCP6323, NCV6323
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511BT
ISSUE O
B
E
A
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
L1
DETAIL A
2X
0.10 C
MILLIMETERS
DIM MIN
MAX
0.80
0.05
2X
0.10
C
A
A1
A3
b
0.70
0.00
0.20 REF
TOP VIEW
MOLD CMPD
EXPOSED Cu
0.20
0.30
1.70
DETAIL B
A
D
2.00 BSC
0.10
C
D2
E
1.50
2.00 BSC
A3
C
E2
e
K
0.80
0.50 BSC
0.25 REF
1.00
A3
A1
0.08
C
DETAIL B
A1
SIDE VIEW
NOTE 4
L
L1
0.20
−−−
0.40
0.15
SEATING
PLANE
RECOMMENDED
D2
DETAIL A
SOLDERING FOOTPRINT*
8X L
1
4
8X
0.50
1.70
PACKAGE
OUTLINE
E2
b
5
8
K
1.00
2.30
8X
e
0.10
C
C
A
B
0.05
NOTE 3
BOTTOM VIEW
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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NCV6323/D
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