HCPL3700VM [ONSEMI]
交流/直流到逻辑接口光耦合器;
| 型号： | HCPL3700VM |
| 厂家： | 
ONSEMI |
| 描述： | 交流/直流到逻辑接口光耦合器 光电 |
| 文件： | 总13页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
AC/DC to Logic
Interface Optocoupler
8
8
1
HCPL3700M
1
PDIP8 GW
CASE 709AC
PDIP8 9.655x6.6, 2.54P
CASE 646CQ
Description
The HCPL3700M voltage/current threshold detection optocoupler
consists of an AlGaAs LED connected to a threshold sensing input
buffer IC which are optically coupled to a high gain darlington output.
The input buffer chip is capable of controlling threshold levels over
a wide range of input voltages with a single resistor. The output is
TTL and CMOS compatible.
ELECTRICAL CONNECTION
AC
1
2
3
4
8
7
6
5
V
CC
Features
• AC or DC Input
NC
DC+
DC−
AC
• Programmable Sense Voltage
• Logic Level Compatibility
• Threshold Guaranteed Over Temperature (0°C to 70°C)
• Safety and Regulatory Approvals
V
O
GND
♦ UL1577, 5,000 VAC
for 1 Minute
RMS
♦ DIN EN/IEC60747−5−5
• These are Pb−Free Devices
TRUTH TABLE
(Positive Logic)
Applications
• Low Voltage Detection
Input
Output
• 5 V to 240 V AC/DC Voltage Sensing
• Relay Contact Monitor
• Current Sensing
• Microprocessor Interface
• Industrial Controls
H
L
L
H
A 0.1 mF bypass capacitor must be connected
between pins 8 and 5.
MARKING DIAGRAM
RX
AC/DC
POWER
3700
VXXYYB
HCPL3700M
LOGIC
3700
= Device Number
V
= DIN EN/IEC60747−5−5 Option
(only appears on component ordered
with this option)
GND 1
GND 2
XX
YY
B
= Two−Digit Year Code
= Two−Digit Work Week
= Assembly Package Code
Figure 1. Schematic
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
March, 2022 − Rev. 2
HCPL3700M/D
HCPL3700M
SAFETY AND INSULATION RATINGS (As per DIN EN/IEC 60747−5−5, this optocoupler is suitable for “safe electrical insulation”
only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.)
Parameter
Characteristics
Installation Classifications per DIN VDE 0110/1.89 Table 1, For Rated
Mains Voltage
<150 V
<300 V
<450 V
<600 V
I–IV
I–IV
RMS
RMS
RMS
RMS
I–III
I–III
<1000 V
(Option TV)
I–III
RMS
Climatic Classification
40/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index
175
Symbol
Parameter
Input−to−Output Test Voltage, Method A, V x 1.6 = V
Value
Unit
V
PR
,
2,262
V
peak
IORM
PR
Type and Sample Test with t = 10 s, Partial Discharge <5 pC
m
Input−to−Output Test Voltage, Method B, V
x 1.875 = V
,
2,651
V
peak
IORM
PR
100% Production Test with t = 1 s, Partial Discharge <5 pC
m
V
Maximum Working Insulation Voltage
Highest Allowable Over−Voltage
External Creepage
1,414
6,000
w8.0
w7.4
w10.16
w0.5
150
V
V
IORM
peak
V
IOTM
peak
mm
mm
mm
mm
°C
External Clearance
External Clearance (for Option TV, 0.4” Lead Spacing)
Distance Through Insulation (Insulation Thickness)
Case Temperature (Note 1)
DTI
T
S
I
Input Current (Note 1)
25
mA
mW
W
S,INPUT
P
Output Power (Duty Factorv2.7%) (Note 1)
Insulation Resistance at T , V = 500 V (Note 1)
250
S,OUTPUT
9
R
>10
IO
S
IO
1. Safety limit value − maximum values allowed in the event of a failure.
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2
HCPL3700M
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified.)
A
Symbol
Parameter
Value
Units
°C
T
Storage Temperature
Operating Temperature
Junction Temperature
Lead Solder Temperature
−40 to +125
−40 to +85
−40 to +125
260 for 10 s
305
STG
OPR
T
°C
T
J
°C
T
SOL
°C
P
T
Total Package Power Dissipation (Note 2)
mW
EMITTER
I
IN
Input Current
Average
50
mA
Surge, 3 ms, 120 Hz Pulse Rate
Transient, 10 ms, 120 Hz Pulse Rate
140
500
−0.5
230
V
P
Input Voltage (Pins 2−3)
V
IN
Input Power Dissipation (Note 3)
mW
IN
DETECTOR
I
Output Current (Average) (Note 4)
Supply Voltage (Pins 8−5)
30
mA
V
O
V
CC
−0.5 to 20
−0.5 to 20
210
V
Output Voltage (Pins 6−5)
V
O
P
Output Power Dissipation (Note 5)
mW
O
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Derate linearly above 70°C free−air temperature at a rate of 2.5 mW/°C.
3. Derate linearly above 70°C free−air temperature at a rate of 1.8 mW/°C.
4. Derate linearly above 70°C free−air temperature at a rate of 0.6 mA/°C.
5. Derate linearly above 70°C free−air temperature at a rate of 1.9 mW/°C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2
Max
18
70
4
Unit
V
V
CC
Supply Voltage
T
A
Ambient Operating Temperature
Operating Frequency
0
°C
f
0
kHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
HCPL3700M
ELECTRICAL CHARACTERISTICS (T = 0°C to 70°C unless otherwise specified)
A
Symbol
Parameter
Input Threshold Current
Test Conditions
= V V = 4.5 V
TH+, CC
Min.
1.96
1.00
3.35
Typ.
2.40
1.20
3.80
Max.
3.11
1.62
4.05
Unit
I
I
V
V
mA
TH+
IN
= 0.4 V, I w4.2 mA (Note 6)
TH−
O
O
V
V
V
V
Input Threshold Voltage
DC (Pins 2, 3)
AC (Pins 1, 4)
V
V
I
= V − V (Pins 1 & 4 Open)
V
V
V
V
TH+
TH−
TH+
TH−
HYS
IN
2
3
= 4.5 V, V = 0.4 V (Note 6)
CC
O
w4.2 mA
O
V
V
I
= V − V (Pins 1 & 4 Open)
2.01
4.23
2.87
2.50
5.00
3.70
2.86
5.50
4.20
IN
2
3
= 4.5 V, V = 2.4 V (Note 6)
CC
O
w100 mA
O
lV = V − V l (Pins 2 & 3 Open)
IN
1
4
V
I
= 4.5 V, V = 0.4 V (Note 6)
CC
O
w4.2 mA
O
lV = lV − V l (Pins 2 & 3 Open)
IN
1
4
V
I
= 4.5 V, V = 2.4 V (Note 6)
CC
O
v100 mA
O
I
Hysteresis
I
= I
TH+
− I
TH−
−
−
1.2
1.3
6.3
mA
V
HYS
V
HYS
V
V
= V − V
TH+ TH−
HYS
V
IHC1
Input Clamp Voltage
= V − V , V = GND
5.4
6.6
V
IHC1
2
3
3
I
IN
= 10 mA
Pins 1 & 4 Connected to PIN 3
V
V
V
= lV − V l, lI l = 10 mA
6.1
7.0
7.3
V
V
IHC2
IHC2
1
4
IN
(Pins 2 & 3 Open)
V
IN
= V − V , V = GND
−
12.5
13.4
IHC3
IHC3
2
3
3
I
= 15 mA
(Pins 1 & 4 Open)
V
ILC
V
IN
= V − V , V = GND
−
−0.75
−
V
ILC
2
3
3
I
= −10 mA
I
IN
Input Current
V
= V − V = 5.0 V
3.0
3.7
4.4
mA
IN
2
3
(Pins 1 & 4 Open)
V
V
Bridge Diode Forward Voltage
I
I
= 3 mA
= 3 mA
−
−
−
−
−
0.65
0.65
0.04
−
V
V
D1,2
IN
IN
D3,4
V
Logic LOW Output Voltage
Logic HIGH Output Current
Logic LOW Supply Current
V
V
= 4.5 V, I = 4.2 mA (Note 6)
0.4
100
4
V
OL
CC
OH
OL
I
= V = 18 V (Note 6)
mA
mA
OH
CC
I
V
V
− V = 5.0 V V = Open
1.0
CCL
2
3
O
= 5 V
CC
I
Logic HIGH Supply Current
Input Capacitance
V
= 18 V, V = Open
−
−
0.01
50
4
mA
CCH
CC
O
C
f = 1 mHz, V = 0 V
(Pins 2 & 3, Pins 1 & 4 Open)
pF
IN
IN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Logic LOW output level at pin 6 occurs when V wV
and when V uV
once V exceeds V
.
IN
TH+
TH−
IN
TH−
TH+
IN
TH+
Logic HIGH output level at pin 6 occurs when V vV
and when V tV
once decreases below V
.
IN
IN
TH−
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4
HCPL3700M
SWITCHING CHARACTERISTICS (T = 25°C, V = 5 V unless otherwise specified)
A
CC
Symbol
Parameter
Test Conditions
R = 4.7 kW, C = 30 pF (Note 7)
Min.
Typ.
Max.
Units
t
Propagation Delay Time
(to Output Low Level)
6.0
15
ms
PHL
L
L
t
Propagation Delay Time
(to Output High Level)
R = 4.7 kW, C = 30 pF (Note 7)
25.0
40
ms
PLH
L
L
t
Output Rise Time (10%−90%)
Output Fall Time (90%−10%)
R = 4.7 kW, C = 30 pF
45
0.5
ms
ms
R
L
L
t
R = 4.7 kW, C = 30 pF
F
L
L
lCM l
Common Mode Transient
Immunity (at Output High Level)
I
= 0 mA, R = 4.7 kW,
4000
V/ms
H
IN
L
V
= 2.0 V, V
= 1400 V (Notes 8, 9)
Omin
CM
lCM l
Common Mode Transient
Immunity (at Output Low Level)
I
= 3.11 mA, R = 4.7 kW,
600
V/ms
L
IN
L
V
= 0.8 V, V
= 1400 V (Notes 8, 9)
Omax
CM
ISOLATION CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
ISO
Withstand Isolation Voltage
RH≤50%, I ≤10 mA,
5,000
−
−
VAC
RMS
I−O
t = 1 min, f = 50 Hz (Note 10, 11)
12
R
C
Resistance (Input to Output)
Capacitance (Input to Output)
V
= 500 V (Note 10)
−
−
10
−
−
W
I−O
I−O
IO
DC
f = 1 MHz, V = 0 V
0.6
pF
IO
DC
7. T
propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 ms rise time) to the 1.5 V level on the
PHL
leading edge of the output pulse. T
propagation delay is measured on the trailing edges of the input and output pulse. (Refer to Fig. 10)
PLH
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV /dt on the leading edge of the common mode
cm
pulse signal V , to assure that the output will remain in a logic high state (i.e., V u2.0 V). Common mode transient immunity in logic low
CM
O
level is the maximum tolerable (negative) dV /dt on the trailing edge of the common mode pulse signal, V , to assure that the output will
cm
CM
remain in a logic low state (i.e., V t0.8 V). Refer to Fig. 11.
O
9. In applications where dV /dt may exceed 50,000 V/ms (Such as static discharge), a series resistor, R , should be included to protect the
cm
CC
detector chip from destructive surge currents. The recommended value for R is 240 V per volt of allowable drop in V (between pin 8
CC
CC
and V ) with a minimum value of 240 W.
CC
10.Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
11. The 5000 VAC /1 min. capability is validated by a 6000 VAC /1 sec. dielectric voltage withstand test.
RMS
RMS
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5
HCPL3700M
TYPICAL PERFORMANCE CURVES
50
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
DC (Pins 1,2 Shorted Together
Pins 3,4 Shorted Together)
40
30
20
10
0
DC (Pins 1 & 4 Open)
AC (Pins 2 & 3 Open)
−10
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
V
CC,
OPERATING SUPPLY VOLTAGE (V)
V
IN,
INPUT VOLTAGE (V)
Figure 2. Logic Low Supply Current vs.
Operating Supply Voltage
Figure 3. Input Current vs. Input Voltage
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
120
110
100
90
80
70
60
50
40
30
20
10
0
3.2
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
V
I
TH+
I
V
IN
TH+
= 5.0 V
IN
(Pins 2 & 3)
V
TH−
V
V
OL
I
TH−
= 5.0 V
CC
= 4.2 mA
I
OL
−40
−20
0
20
40
60
80
100
−40
−20
0
20
T TEMPERATURE (°C)
A,
40
60
80
100
T
A,
TEMPERATURE (°C)
Figure 4. Input Current/Low Level Output Voltage
vs. Temperature
Figure 5. Current Threshold/Voltage Threshold vs.
Temperature
0.5
0.4
0.3
0.2
0.1
0.0
100
90
80
70
60
50
40
30
20
10
0
30
25
20
t
t
F
t
PLH
15
10
5
R
t
PHL
0
−40
−20
0
20
40
60
80
100
−40
−20
0
20
T TEMPERATURE (°C)
A,
40
60
80
100
T
TEMPERATURE (°C)
A,
Figure 6. Propagation Delay vs. Temperature
Figure 7. Rise and Fall Time vs. Temperature
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6
HCPL3700M
TYPICAL PERFORMANCE CURVES (continued)
300
250
100
10
1
V
V
= 18 V
= Open
= 0 A
CC
O
I
IN
V+ (AC)
200
V+ (DC)
V− (AC)
V− (DC)
150
100
50
0.1
−40
0
−20
0
20
40
60
80
100
0
40
80
120
160
200
240
T
A,
TEMPERATURE (°C)
R
EXTERNAL SERIES RESISTOR (kW)
X,
Figure 8. Logic High Supply Current vs. Temperature
Figure 9. External Threshold Characteristics V+/V−
vs. Rx
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7
HCPL3700M
TEST CIRCUITS
+5 V
5 V
2.5 V
0 V
Input
(V
)
AC
V
CC
1
2
3
4
8
7
6
5
IN
Pulse
Generator
tr = 5 ns
0.1 mF
bypass
t
t
PLH
PHL
R
L
DC+
DC−
AC
V
O
Output
(V )
O
Vo
Output
(V )
O
90%
10%
90%
Z
O
= 50 W
C
L
1.5 V
GND
10%
V
OL
t
F
t
R
V
IN
Pulse Amplitude = 50 V
Pulse Width = 1 ms
f = 100 Hz
T = T = 1.0 ms (10% − 90%)
r
f
Figure 10. Switching Test Circuit
1400 V
I
IN
R
CC
*
+5 V
AC
V
CC
1
2
3
4
8
7
6
5
A
B
0.1 mF
bypass
R
DC+
DC−
AC
L
V
0 V
V
CM
Output
(V )
O
Vo
V
FF
GND
V
O
OH
C **
L
Switching Pos. (A)
= 0 mA
I
IN
V
CM
−
+
V
O
(Min)
* SEE NOTE 8
Pulse Gen
V
O
(Max)
** C IS 30 pF, WHICH INCLUDES PROBE
L
AND STRAY WIRING CAPACITANCE
Switching Pos. (B)
= 3.11 mA
I
IN
V
O
V
OL
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
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8
HCPL3700M
REFLOW PROFILE
Max. Ramp−up Rate = 3°C/s
Max. Ramp−down Rate = 6°C/s
T
P
260
240
220
200
180
160
140
120
100
80
t
P
T
L
Tsmax
t
L
Preheat Area
Tsmin
t
S
60
40
20
0
120
240
360
Time 25°C to Peak
Time (s)
Profile Freature
Pb−Free Assembly Profile
150°C
Temperature Minimum (Tsmin)
Temperature Maximum (Tsmax)
200°C
Time (t ) from (Tsmin to Tsmax)
60 to 120 s
S
Ramp−up Rate (t to t )
3°C/s maximum
217°C
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60 to 150 s
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
260°C +0°C/–5°C
30 s
P
Ramp−down Rate (T to T )
6°C/s maximum
8 minutes maximum
P
L
Time 25°C to Peak Temperature
Figure 12. Reflow Profile
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9
HCPL3700M
ORDERING INFORMATION
Part Number
†
Package
DIP 8−Pin
Packing Method
50 Units / Tube
50 Units / Tube
HCPL3700M
HCPL3700SM
SMT 8−Pin (Lead Bend)
HCPL3700SDM
HCPL3700VM
SMT 8−Pin (Lead Bend)
1000 / Tape & Reel
50 Units / Tube
DIP 8−Pin, DIN EN/IEC60747−5−5 option
SMT 8−Pin (Lead Bend), DIN EN/IEC 60747−5−5 option
SMT 8−Pin (Lead Bend), DIN EN/IEC 60747−5−5 option
HCPL3700SVM
HCPL3700SDVM
50 Units / Tube
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 9.655x6.6, 2.54P
CASE 646CQ
ISSUE O
DATE 18 SEP 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13446G
PDIP8 9.655X6.6, 2.54P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 GW
CASE 709AC
ISSUE O
DATE 31 JUL 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13447G
PDIP8 GW
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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相关型号：
HCPL3700WV
8-pin DIP AC/DC To Logic Interface Optocoupler, 8LD,MDIP,OPTO, .4" LEAD SPACING, BLACK, 1000/BULK
FAIRCHILD
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