HUF75639S3ST [ONSEMI]
N 沟道，UltraFET 功率 MOSFET，100V，56A，25mΩ;
| 型号： | HUF75639S3ST |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，UltraFET 功率 MOSFET，100V，56A，25mΩ 开关 晶体管 |
| 文件： | 总15页 (文件大小：843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Power, N-Channel,
Ultrafet
100 V, 56 A, 25 mW
HUF75639G3, HUF75639P3,
HUF75639S3S, HUF75639S3
These N−Channel power MOSFETs are manufactured using the
innovative Ultrafet process. This advanced process technology
achieves the lowest possible on− resistance per silicon area, resulting
in outstanding performance. This device is capable of withstanding
high energy in the avalanche mode and the diode exhibits very low
reverse recovery time and stored charge. It was designed for use in
applications where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay drivers,
low−voltage bus switches, and power management in portable and
battery− operated products.
TO−247−3LD
CASE 340CK
TO−220−3LD
CASE 340AT
D2PAK−3
CASE 418AJ
I2PAK
CASE 418AV
Formerly developmental type TA75639.
MARKING DIAGRAMS
Features
• 56 A, 100 V
• Simulation Models
®
♦ Temperature Compensated PSPICE and SABER™ Electrical
$Y&Z&3&K
75639G
$Y&Z&3&K
75639P
Models
♦ Spice and Saber Thermal Impedance Models
♦ www.onsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
$Y&Z&3&K
75639S
$Y&Z&3&K
75639S
• Related Literature
♦ TB334, “Guidelines for Soldering Surface Mount Components to
PC Boards”
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
&Y
= onsemi Logo
&Z
&3
&K
75639x
x
= Assembly Plant Code
= 3−Digit Date Code
= 2−Digit Lot Traceability Code
= Specific Device Code
= G/P/S
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
February, 2023 − Rev. 5
HUF75639G3/D
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
ORDERING INFORMATION
PART NUMBER
HUF75639G3
HUF75639P3
HUF75639S3ST
HUF75639S3
PACKAGE
TO−247
BRAND
75639G
75639P
75639S
75639S
TO−220AB
TO−263AB
TO−262AA
PACKAGING
Figure 1.
ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise specified
C
Description
Symbol
Ratings
100 V
100 V
20 V
Units
Drain to Source Voltage (Note 1)
V
V
V
V
DSS
DGR
Drain to Gate Voltage (R = 20 kW) (Note 1)
V
GS
Gate to Source Voltage
V
GS
Drain Current
Continuous (Figure 2)
Pulsed Drain Current
I
56
Figure 4
A
D
I
DM
Pulsed Avalanche Rating
E
AS
Figures 6, 14, 15
Power Dissipation
P
D
200
W
Derate Above 25°C
1.35
W/°C
Operating and Storage Temperature
T , T
−55 to 175°C
°C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6 mm) from Case for 10s
Package Body for 10 s, See Techbrief 334
T
300
260
°C
L
T
pkg
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. TJ = 25°C to 150°C.
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
ELECTRICAL SPECIFICATION T = 25 °C unless otherwise specified
J
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
OFF STATE SPECIFICATIONS
BV Drain to Source Breakdown Voltage
I
= 250 mA, V = 0 V (Figure 11)
100
−
−
−
−
−
−
V
D
GS
DSS
Zero Gate Voltage Drain Current
V
V
V
= 95 V, V = 0 V
1
mA
mA
nA
I
DSS
DS
DS
GS
GS
= 90 V, V = 0 V, T = 150°C
−
250
100
GS
C
=
20 V
I
Gate to Source Leakage Current
−
GSS
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
V
= V , I = 250 mA (Figure 10)
DS D
V
2
−
4
V
GS
GS(TH)
mW
R
I
D
= 56 A, V = 10 V (Figure 9)
−
21
25
DS(on)
GS
°C/W
°C/W
°C/W
R
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
(Figure 3)
−
−
−
−
−
−
0.74
30
θ
JC
JA
R
TO−247
θ
TO−220, TO−263, TO−262
62
SWITCHING SPECIFICATIONS (V = 10 V)
GS
t
Turn−On Time
Turn−On Delay Time
Rise Time
−
−
−
−
−
−
−
110
−
ns
ns
ns
ns
ns
ns
ON
V
V
= 50 V, I ≅ 56 A, R = 0.89 W,
D L
DD
= 10 V, R = 5.1 W
t
td
t
GS
GS
15
60
20
25
−
d(ON)
t
r
−
Turn−Off Delay Time
Fall Time
−
(OFF)
t
f
−
Turn−Off Time
70
OFF
GATE CHARGE SPECIFICATIONS
V
= 50 V, I ≅ 56 A,
D
Q
Total Gate Charge
V
GS
V
GS
V
GS
= 0 V to 20 V
= 0 V to 10 V
= 0 V to 2 V
−
−
−
−
−
110
57
130
75
4.5
−
nC
nC
nC
nC
nC
DD
L
g(TOT)
R = 0.89 W
Q
Gate Charge at 10 V
g(10)
I
= 1.0 mA
g(REF)
(Figure 13)
Q
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
3.7
9.8
24
g(TH)
Q
Q
gs
−
gd
CAPACITANCE SPECIFICATIONS
C
Input Capacitance
V
= 25 V, V = 0 V,
−
−
−
2000
500
65
−
−
−
pF
pF
pF
ISS
DS
GS
f = 1 MHz
(Figure 12)
C
Output Capacitance
OSS
RSS
C
Reverse Transfer Capacitance
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
−
TYP
−
MAX
1.25
110
UNITS
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
V
SD
I
I
I
= 56 A
V
SD
SD
SD
= 56 A, dI /dt = 100 A/ms
t
rr
−
−
ns
nC
SD
= 56 A, dI /dt = 100 A/ms
Q
−
−
320
SD
RR
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TYPICAL PERFORMANCE CURVES
60
50
40
30
20
10
0
1.2
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
T , CASE TEMPERATURE (5C)
C
T , CASE TEMPERATURE (5C)
C
Figure 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
Figure 2. MAXIMUM CONTINUOUS DRAIN
CURRENT vs CASE TEMPERATURE
2
DUTY CYCLE − DESCENDING ORDER
0.5
0.2
0.1
1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R
+ T
JC C
q
JC
q
J
DM
0.01
−5
10
−4
−3
10
−2
10
−1
10
0
1
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
100
10
o
T
C
= 25 C
FOR TEMPERATURES
ABOVE 255C DERATE PEAK
CURRENT AS FOLLOWS:
175 − T
C
I = I
25
150
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
−5
10
−4
10
−3
10
−2
10
−1
0
1
10
10
10
t, PULSE WIDTH (s)
Figure 4. PEAK CURRENT CAPABILITY
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
1000
100
300
If R = 0
T
C
= MAX RATED
J
tAV = (L)(IAS)/(1.3yRATED BVDSS − VDD)
o
T
= 25 C
If R p 0
tAV = (L/R)ln[(IASyR)/(1.3yRATED BVDSS − VDD) +1]
100
STARTING T = 255C
J
100ms
STARTING T = 1505C
J
10
1
1ms
OPERATION IN THIS
AREA MAY BE
10ms
V
= 100V
LIMITED BY r
DS(ON)
DSS(MAX)
10
0.001
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100 200
0.01
0.1
1
t , TIME IN AVALANCHE (ms)
AV
V
DS
Figure 5. FORWARD BIAS SAFE OPERATING AREA
Figure 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
100
100
V
= 6V
o
GS
175 C
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
V
= 15V
80
60
40
20
0
80
60
40
20
0
DD
V
= 20V
= 10V
= 7V
GS
V
GS
V
GS
V
GS
= 5V
PULSE DURATION = 80 ms
o
o
DUTY CYCLE = 0.5% MAX
25 C
−55 C
o
T
C
= 25 C
0
1.5
3.0
4.5
6.0
7.5
0
1
2
3
4
5
6
7
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
Figure 7. SATURATION CHARACTERISTICS
Figure 8. TRANSFER CHARACTERISTICS
1.2
3.0
2.5
2.0
1.5
1.0
0.5
0
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250 mA
V
GS
= 10V, I = 56A
D
1.0
0.8
0.6
−80
−40
0
40
80
120
160
200
−80
−40
0
40
80
120
160
200
T , JUNCTION TEMPERATURE (5C)
J
T , JUNCTION TEMPERATURE (5C)
J
Figure 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Figure 10. NORMALIZED GATE THRESHOLD VOLTAGE
vs JUNCTION TEMPERATURE
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
3000
1.2
VGS = 0 V, f = 1 MHz
CISS = CGS + CGD
CRSS = CGD
I
D
= 250 mA
2500
2000
1500
1000
500
COSS = CDS + CGD
1.1
1.0
0.9
C
ISS
C
OSS
C
RSS
0
−80
−40
0
40
80
120
160
200
0
10
V
20
30
40
50
60
T , JUNCTION TEMPERATURE (5C)
J
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 11. NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE vs JUNCTION
TEMPERATURE
Figure 12. CAPACITANCE vs DRAIN TO SOURCE
VOLTAGE
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
= 56A
D
D
D
2
I
I
= 37A
= 18A
V
= 50V
DD
0
0
10
20
30
40
50
60
Qg, GATE CHARGE (nC)
Figure 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TEST CIRCUITS AND WAVEFORMS
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
−
V
GS
DUT
t
P
I
AS
0V
0
0.01 W
t
AV
Figure 14. UNCLAMPED ENERGY TEST CIRCUIT
Figure 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
L
g(TOT)
V
DS
V
= 20V
GS
V
GS
Q
g(10)
+
V
DD
V
= 10V
V
GS
GS
−
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. GATE CHARGE WAVEFORM
Figure 16. GATE CHARGE TEST CIRCUIT
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
−
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 18. SWITCHING TIME TEST CIRCUIT
Figure 19. RESISTIVE SWITCHING WAVEFORMS
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
PSPICE Electrical Model
SUBCKT HUF75639 2 1 3 ;
rev Oct. 98
CA 12 8 2.8e−9
CB 15 14 2.65e−9
CIN 6 8 1.9e−9
LDRAIN
DPLCAP
DRAIN
2
5
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
DBREAK
51
EBREAK 11 7 17 18 110
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
+
RSLC2
5
51
ESLC
11
−
50
+
−
17
18
−
DBODY
RDRAIN
6
EBREAK
ESG
8
IT 8 17 1
EVTHRES
+
+
16
21
−
19
8
MWEAK
LDRAIN 2 5 2e−9
LGATE 1 9 1e−9
LSOURCE 3 7 0.47e−9
LGATE
EVTEMP
+
RGATE
GATE
1
6
−
18
22
MMED
9
20
MSTRO
8
RLGATE 1 9 10
RLDRAIN 2 5 20
RLSOURCE 3 7 4.69
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
RBREAK
12
15
13
14
13
17
18
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.3e−2
RGATE 9 20 0.7
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.5e−3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
−
+
+
VBAT
6
8
−
5
8
EGS
EDS
+
−
8
22
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V (5,51)))*(PWR(V(5,51)/(1e−6*115),4))}
.MODEL DBODYMOD D (IS = 1.4e−12 RS = 3.3e−3 XTI = 4.7 TRS1 = 2e−3 TRS2 = 0.1e−5 CJO = 3.3e−9 TT = 6.1e−8 M = 0.7)
.MODEL DBREAKMOD D (RS = 3.5e− 1TRS1 = 1e− 3TRS2 = 1e−6)
.MODEL DPLCAPMOD D (CJO = 2.2e− 9IS = 1e−3 0N = 10 M = 0.95 vj = 1.0)
.MODEL MMEDMOD NMOS (VTO = 3.5 KP = 4.8 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u Rg = 0.7)
.MODEL MSTROMOD NMOS (VTO = 3.97 KP = 56.5 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO =3.11 KP = 0.085 IS = 1e−3
.MODEL RBREAKMOD RES (TC1 = 0.8e− 3TC2 = 1e−6)
.MODEL RDRAINMOD RES (TC1 = 1e−2 TC2 = 1.75e−5)
.MODEL RSLCMOD RES (TC1 = 2.8e−3 TC2 = 14e−6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
0 N = 10 TOX = 1 L = 1u W = 1u RG = 7 RS = 0.1)
.MODEL RVTHRESMOD RES (TC = −2.0e−3 TC2 = −1.75e−5)
.MODEL RVTEMPMOD RES (TC1 = −2.75e− 3TC2 = 0.05e−9)
.MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −6.0 VOFF = −3.5)
.MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −3.5 VOFF = −6.0)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −2.5 VOFF = 4.95)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 4.95 VOFF = −2.5)
.ENDS
NOTE:
For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
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HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
SABER Electrical Model
nom temp=25 deg c 100v Ultrafet
REV Oct. 98
template huf75639 n2,n1,n3
electrical n2,n1,n3
{
LDRAIN
RLDRAIN
RDBODY
var i iscl
DPLCAP
DRAIN
2
5
d..model dbodymod = (is=1.4e−12, xti=4.7, cjo=33e−10,tt=6.1e−8, m=0.7)
d..model dbreakmod = ()
10
d..model dplcapmod = (cjo=22e−10,is=1e−30,n=10,m=0.95, vj=1.0)
m..model mmedmod = (type=_n,vto=3.5,kp=4.8,is=1e−30, tox=1)
m..model mstrongmod = (type=_n,vto=3.97,kp=56.5,is=1e−30, tox=1)
m..model mweakmod = (type=_n,vto=3.11,kp=0.085,is=1e−30, tox=1)
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−6.0,voff=−3.5)
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−6.0)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−2.5,voff=4.95)
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=4.95,voff=−2.5)
RSLC1
51
RDBREAK
72
RSLC2
ISCL
DBREAK
50
−
71
RDRAIN
6
11
ESG
8
c.ca n12 n8 = 28.5e−10
c.cb n15 n14 = 26.5e−10
c.cin n6 n8 = 19e−10
EVTHRES
+
+
16
21
−
19
8
MWEAK
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
−
18
22
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
EBREAK
+
MMED
9
20
MSTRO
17
18
−
RLGATE
LSOURCE
CIN
SOURCE
3
i.it n8 n17 = 1
8
7
l.ldrain n2 n5 = 2.0e−9
l.lgate n1 n9 = 1e−9
RSOURCE
RLSOURCE
18
l.lsource n3 n7 = 4.69e−10
S1A
S2A
RBREAK
12
15
13
14
13
17
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
8
RVTEMP
19
S1B
S2B
13
CB
CA
res.rbreak n17 n18 = 1, tc1=0.8e−3,tc2=−1e−6
res.rdbody n71 n5 = 3.3e−3, tc1=2.0e−3, tc2=0.1e−5
res.rdbreak n72 n5 = 3.5e−1, tc1=1e−3, tc2=1e−6
res.rdrain n50 n16 = 13e−3, tc1=1e−2,tc2=1.75e−5
res.rgate n9 n20 = 0.7
IT
14
−
+
+
VBAT
6
8
−
5
8
EGS
EDS
+
−
8
22
res.rldrain n2 n5 = 20
RVTHRES
res.rlgate n1 n9 = 10
res.rlsource n3 n7 = 4.69
res.rslc1 n5 n51 = 1e−6, tc1=2.8e−3,tc2=14e−6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4.5e−3, tc1=0,tc2=0
res.rvtemp n18 n19 = 1, tc1=−2.75e−3,tc2=0.05e−9
res.rvthres n22 n8 = 1, tc1=−2e−3,tc2=−1.75e−5
spe.ebreak n11 n7 n17 n18 = 110
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/115))** 4))
}
}
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9
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
Spice Thermal Model
JUNCTION
TH
REV APRIL 1998
HUF75639
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 TH 6 2.8e−3
CTHERM2 6 5 4.6e−3
CTHERM3 5 4 5.5e−3
CTHERM4 4 3 9.2e−3
CTHERM5 3 2 1.7e−2
CTHERM6 2 TL 4.3e−2
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 TH 6 5.0e−4
RTHERM2 6 5 1.5e−3
RTHERM3 5 4 2.0e−2
RTHERM4 4 3 9.0e−2
RTHERM5 3 2 1.9e−1
RTHERM6 2 TL 2.9e−1
5
Saber Thermal Model
Saber thermal model HUF75639
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.8e−3
ctherm.ctherm2 6 5 = 4.6e−3
ctherm.ctherm3 5 4 = 5.5e−3
ctherm.ctherm4 4 3 = 9.2e−3
ctherm.ctherm5 3 2 = 1.7e−2
ctherm.ctherm6 2 tl = 4.3e−2
rtherm.rtherm1 th 6 = 5.0e−4
rtherm.rtherm2 6 5 = 1.5e−3
rtherm.rtherm3 5 4 = 2.0e−2
rtherm.rtherm4 4 3 = 9.0e−2
rtherm.rtherm5 3 2 = 1.9e−1
rtherm.rtherm6 2 tl = 2.9e−1
}
TL
CASE
PSPICE is a trademark of MicroSim Corporation.
Saber is a registered trademark of Sabremark Limited Partnership.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220−3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO−220−3LD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ = Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb−Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
DESCRIPTION:
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
I2PAK (TO−262 3 LD)
CASE 418AV
ISSUE A
DATE 30 AUG 2022
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXXXX
XXXXXXXXX
XXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ
= Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13814G
I2PAK (TO−262 3 LD)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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