J112-D74Z [ONSEMI]
5 mA, 35 V, N-Channel JFET Transistor;
| 型号： | J112-D74Z |
| 厂家： | 
ONSEMI |
| 描述： | 5 mA, 35 V, N-Channel JFET Transistor 开关 小信号场效应晶体管 |
| 文件： | 总5页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
J111, J112
JFET Chopper Transistors
N−Channel — Depletion
Features
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• Pb−Free Packages are Available*
1 DRAIN
MAXIMUM RATINGS
Rating
Drain−Gate Voltage
Symbol
Value
Unit
3
GATE
V
−35
Vdc
DG
Gate−Source Voltage
Gate Current
V
−35
50
Vdc
GS
I
mAdc
G
2 SOURCE
Total Device Dissipation @ T = 25°C
P
350
2.8
mW
mW/°C
A
D
Derate above = 25°C
Lead Temperature
T
300
°C
°C
L
Operating and Storage Junction
Temperature Range
T , T
−65 to +150
J
stg
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
TO−92
CASE 29−11
STYLE 5
1
2
3
MARKING DIAGRAM
J11x
AYWW G
G
J11x = Device Code
x = 1 or 2
A
Y
= Assembly Location
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 2
J111/D
J111, J112
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
V
35
−
−
Vdc
nAdc
Vdc
(BR)GSS
(I = −1.0 mAdc)
G
Gate Reverse Current
I
−ꢀ1.0
GSS
(V = −15 Vdc)
GS
Gate Source Cutoff Voltage
V
GS(off)
(V = 5.0 Vdc, I = 1.0 mAdc)
J111
J112
−ꢀ3.0
−ꢀ1.0
−ꢀ10
−ꢀ5.0
DS
D
Drain−Cutoff Current
I
−
1.0
nAdc
D(off)
(V = 5.0 Vdc, V = −10 Vdc)
DS
GS
ON CHARACTERISTICS
(1)
Zero−Gate−Voltage Drain Current
(V = 15 Vdc)
I
mAdc
DSS
J111
J112
20
5.0
2.0
−
−
−
DS
Static Drain−Source On Resistance
r
W
DS(on)
(V = 0.1 Vdc)
DS
J111
J112
−
−
30
50
Drain Gate and Source Gate On−Capacitance
C
−
28
pF
dg(on)
+
(V = V = 0, f = 1.0 MHz)
DS
GS
C
C
sg(on)
Drain Gate Off−Capacitance
−
−
5.0
5.0
pF
pF
dg(off)
(V = −10 Vdc, f = 1.0 MHz)
GS
Source Gate Off−Capacitance
C
sg(off)
(V = −10 Vdc, f = 1.0 MHz)
GS
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
ORDERING INFORMATION
†
Device
J111RL1
Package
Shipping
TO−92
2000 Units / Tape & Reel
2000 Units / Tape & Reel
2000 Units / Tape & Reel
1000 Units / Bulk
J111RL1G
TO−92
(Pb−Free)
J111RLRA
TO−92
J111RLRAG
TO−92
(Pb−Free)
J111RLRP
TO−92
J111RLRPG
TO−92
(Pb−Free)
J112
TO−92
J112G
TO−92
(Pb−Free)
J112RL1
TO−92
2000 Units / Tape & Reel
2000 Units / Tape & Reel
J112RL1G
TO−92
(Pb−Free)
J112RLRA
TO−92
J112RLRAG
TO−92
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
J111, J112
TYPICAL SWITCHING CHARACTERISTICS
1000
500
1000
T = 25°C
J
T = 25°C
J
500
J111
J112
J113
V
= 12 V
= 7.0 V
= 5.0 V
GS(off)
R
= R ′
D
K
R
= R ′
D
J111
J112
J113
V
= 12 V
= 7.0 V
= 5.0 V
K
GS(off)
200
100
50
200
100
50
20
10
20
10
R
= 0
K
R
= 0
K
5.0
5.0
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
I , DRAIN CURRENT (mA)
D
I , DRAIN CURRENT (mA)
D
Figure 1. Turn−On Delay Time
Figure 2. Rise Time
1000
500
1000
500
T = 25°C
T = 25°C
J
J
R
= R ′
D
K
J111
J112
J113
V
= 12 V
= 7.0 V
= 5.0 V
J111
J112
J113
V
= 12 V
GS(off)
GS(off)
200
100
50
200
100
50
= 7.0 V
= 5.0 V
R
= R ′
D
K
20
10
20
10
R
= 0
K
R
= 0
K
5.0
5.0
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
I , DRAIN CURRENT (mA)
D
I , DRAIN CURRENT (mA)
D
Figure 3. Turn−Off Delay Time
Figure 4. Fall Time
NOTE 1
+V
DD
The switching characteristics shown above were measured using a test
circuit similar to Figure 5. At the beginning of the switching interval,
the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source
Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due
to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or
R
D
SET V
= 10 V
DS(off)
INPUT
R
K
R
T
Gate−Drain Capacitance (Cgd) is charged to VGG + VDS
.
R
GEN
OUTPUT
During the turn−on interval, Gate−Source Capacitance (Cgs)
discharges through the series combination of RGen and RK. Cgd must
discharge to VDS(on) through RG and RK in series with the parallel
combination of effective load impedance (R′D) and Drain−Source
Resistance (rds). During the turn−off, this charge flow is reversed.
50 W
R
GG
50 W
50 W
V
GEN
V
GG
Predicting turn−on time is somewhat difficult as the channel resistance
rds is a function of the gate−source voltage. While Cgs discharges, VGS
approaches zero and rds decreases. Since Cgd discharges through rds,
turn−on time is non−linear. During turn−off, the situation is reversed
with rds increasing as Cgd charges.
INPUT PULSE
≤ 0.25 ns
R
GG
& R
K
t
r
R (R ) 50)
T
t ≤ 0.5 ns
D
f
R Ȁ +
D
PULSE WIDTH = 2.0 ms
R
) R ) 50
T
D
DUTY CYCLE ≤ 2.0%
The above switching curves show two impedance conditions; 1) RK
is equal to RD, which simulates the switching behavior of cascaded
stages where the driving source impedance is normally the load
impedance of the previous stage, and 2) RK = 0 (low impedance) the
driving source impedance is that of the generator.
Figure 5. Switching Time Test Circuit
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3
J111, J112
20
15
10
J112
J111
C
gs
10
7.0
5.0
7.0
5.0
J113
T
C
gd
= 25°C
channel
V
= 15 V
DS
3.0
2.0
T
= 25°C
(C IS NEGLIGIBLE)
channel
ds
3.0
2.0
1.5
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
0.03 0.05 0.1
0.3 0.5
1.0
3.0 5.0
10
30
I , DRAIN CURRENT (mA)
D
V , REVERSE VOLTAGE (VOLTS)
R
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
200
160
120
80
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
I
25 50ꢁmA 75ꢁmA 100ꢁmA
mA
125ꢁmA
DSS
I
= 1.0 mA
= 0
D
= 10
mA
V
GS
T
= 25°C
channel
40
0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
−ꢀ70
−ꢀ40
−ꢀ10
20
50
80
110
140
170
V
, GATE−SOURCE VOLTAGE (VOLTS)
T
channel
, CHANNEL TEMPERATURE (°C)
GS
Figure 8. Effect of Gate−Source Voltage
On Drain−Source Resistance
Figure 9. Effect of Temperature On
Drain−Source On−State Resistance
NOTE 2
100
90
10
The Zero−Gate−Voltage Drain Current (IDSS), is the
principle determinant of other J-FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
Voltage (VGS(off) and Drain−Source On Resistance
(rds(on)) to IDSS. Most of the devices will be within 10%
of the values shown in Figure 10. This data will be useful
in predicting the characteristic variations for a given part
number.
T
= 25°C
channel
9.0
8.0
7.0
80
70
r
@ V = 0
GS
DS(on)
60
50
40
30
20
10
0
6.0
5.0
4.0
3.0
2.0
V
GS(off)
For example:
Unknown
r
ds(on) and VGS range for an J112
1.0
0
The electrical characteristics table indicates that an J112
has an IDSS range of 25 to 75 mA. Figure 10, shows
rds(on) = 52 W for IDSS = 25 mA and 30 W for
10 20 30 40 50 60
80
100
90 110 120 130 140 150
70
I
, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA)
DSS
I
DSS = 75 mA. The corresponding VGS values are 2.2 V
and 4.8 V.
Figure 10. Effect of IDSS On Drain−Source
Resistance and Gate−Source Voltage
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4
J111, J112
PACKAGE DIMENSIONS
TO−92 (TO−226)
CASE 29−11
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
B
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
R
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
P
L
SEATING
PLANE
INCHES
DIM MIN MAX
MILLIMETERS
K
MIN
4.45
4.32
3.18
MAX
5.20
5.33
4.19
0.533
1.39
2.66
0.50
−−−
A
B
C
D
G
H
J
0.175
0.170
0.125
0.016
0.045
0.095
0.015
0.500
0.250
0.080
0.205
0.210
0.165
0.021 0.407
D
X X
0.055
0.105
0.020
−−− 12.70
−−−
0.105
1.15
2.42
0.39
G
J
H
V
K
L
6.35
2.04
−−−
2.93
3.43
−−−
C
N
P
R
V
2.66
2.54
−−−
−−− 0.100
SECTION X−X
0.115
0.135
−−−
−−−
1
N
−−−
N
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
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J111/D
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TRANSISTOR 40 V, N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-92, FET General Purpose Small Signal
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