KAE02150_16 [ONSEMI]
Interline CCD Image Sensor;
| 型号： | KAE02150_16 |
| 厂家： | 
ONSEMI |
| 描述： | Interline CCD Image Sensor CD |
| 文件： | 总40页 (文件大小：817K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KAE-02150
1920 (H) x 1080 (V)
Interline CCD Image Sensor
The KAE−02150 Image Sensor is a 1080p (1920 × 1080) CCD in
a 2/3″ optical format that provides exceptional imaging performance
in extreme low light applications. Each of the sensor’s four outputs
incorporate both a conventional horizontal CCD register and a high
gain EMCCD register.
www.onsemi.com
An intra-scene switchable gain feature samples each charge packet
on a pixel-by-pixel basis. This enables the camera system to determine
whether the charge will be routed through the normal gain output or
the EMCCD output based on a user selectable threshold. This feature
enables imaging in extreme low light, even when bright objects are
within a dark scene, allowing a single camera to capture quality
images from sunlight to starlight.
This image sensor is based on the 5.5-micron Interline Transfer
CCD Platform, and features extended dynamic range, excellent
imaging performance, and a flexible readout architecture that enables
use of 1, 2, or 4 outputs. A vertical overflow drain structure suppresses
image blooming, provides excellent MTF, and enables electronic
shuttering for precise exposure control.
Figure 1. KAE−02150 Interline CCD
Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Typical Value
Interline CCD; with EMCCD
2004 (H) × 1144 (V)
Features
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
• Intra-Scene Switchable Gain
• Wide Dynamic Range
• Low Noise Architecture
• Exceptional Low Light Imaging
• Global Shutter
• Excellent Image Uniformity and MTF
• Bayer Color Pattern and Monochrome
1960 (H) × 1120 (V)
1920 (H) × 1080 (V)
5.5 mm (H) × 5.5 mm (V)
Active Image Size
10.56 mm (H) × 5.94 mm (V)
12.1 mm (Diag.), 2/3″ Optical Format
Aspect Ratio
16:9
Number of Outputs
Charge Capacity
Output Sensitivity
1, 2, or 4
−
20,000 e
Applications
−
44 mV/e
Quantum Efficiency
Mono/Color (RGB)
• Surveillance
50% / 33%, 41%, 43%
• Scientific Imaging
• Medical Imaging
• Intelligent Transportation
Read Noise (20 MHz)
Normal Mode (1× Gain)
Intra-Scene Mode (20× Gain)
−
9 e rms
−
< 1 e rms
Dark Current (0°C)
Photodiode, VCCD
−
−
< 0.1 e /s, 6 e /s
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Dynamic Range
Normal Mode (1× Gain)
Intra-Scene Mode (20× Gain)
68 dB
86 dB
Charge Transfer Efficiency
Blooming Suppression
Smear
0.999999
> 1000 X
−100 dB
−
Image Lag
< 1 e
Maximum Pixel Clock Speed
40 MHz
Maximum Frame Rate
Normal Mode, Intra-Scene Mode 60 fps (40 MHz), 30 fps (20 MHz)
Package
Cover Glass
135 pin PGA
Clear Glass, Taped
NOTE: All Parameters are specified at T = 0°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
February, 2016 − Rev. 2
KAE−02150/D
KAE−02150
ORDERING INFORMATION
US export controls apply to all shipments of this product
designated for destinations outside of the US and Canada,
requiring ON Semiconductor to obtain an export license
from the US Department of Commerce before image sensors
or evaluation kits can be exported.
Table 2. ORDERING INFORMATION
Part Number
Description
Marking Code
KAE−02150−ABB−JP−FA
KAE−02150−ABB−JP−EE
KAE−02150−FBB−JP−FA
KAE−02150−FBB−JP−EE
Monochrome, Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Standard Grade
KAE−02150−ABB
Serial Number
Monochrome, Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Grade
Color (Bayer RGB), Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Standard Grade
KAE−02150−FBB
Serial Number
Color (Bayer RGB), Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Grade
Table 3. EVALUATION SUPPORT
Part Number
Description
KAE−02150−AB−A−GEVK
KAE−02150 Evaluation Kit
Lens Mount Kit for IT−CCD Evaluation Hardware
LENS−MOUNT−KIT−C−GEVK
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAE−02150
DEVICE DESCRIPTION
Architecture
VOUT
VOUT
D3
C3
2072
2072
8
1
4
28
1
10 24
8
960
960
24 10
1
28
1
4
14
8
1920 y 1080
24 8
8
24
5.5 mm Pixels
8
14
4
1
4
1
28
1
10 24
8
960
960
8
24 10
1
28
2072 2070
2070 2072
VOUT
VOUT
B3
A3
Figure 2. Block Diagram
Dark Reference Pixels
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photo-site. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming
There are 14 dark reference rows at the top and bottom of
the image sensor, as well as 24 dark reference columns on the
left and right sides. However, the rows and columns at the
very edges should not be included in acquiring a dark
reference signal, since they may be subject to some light
leakage.
Active Buffer Pixels
8 unshielded pixels adjacent to any leading or trailing dark
reference regions are classified as active buffer pixels. These
pixels are light sensitive but are not tested for defects and
non-uniformities.
ESD Protection
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power-Up and Power-Down Sequence section.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
www.onsemi.com
3
KAE−02150
Bayer Color Filter Pattern
VOUT
VOUT
D3
C3
2072
2072
8
1
4
28
1
10 24
8
960
960
24 10
1
28
1
4
14
8
1920 y 1080
24 8
8
24
5.5 mm Pixels
8
14
4
1
4
1
28
1
10 24
8
960
960
8
24 10
1
28
2072 2070
2070 2072
VOUT
VOUT
B3
A3
Figure 3. Bayer Color Filter Pattern
www.onsemi.com
4
KAE−02150
Physical Description
Pin Grid Array and Pin Description
H
G
F
E
D
C
B
A
17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
Figure 4. PGA Package Designations (Bottom View)
Table 4. PIN DESCRIPTION
Pin
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
B01
B02
B03
Label
V3B
Description
VCCD Bottom Phase 3
N/C
No Connection
RG2a
N/C
Amplifier 2 Reset, Quadrant A
No Connection
VDD23ab
H1BEMa
H2Ba
GND
Amplifier 2 and 3 Supply, Quadrants A, B
EMCCD Barrier Phase 1, Quadrant A
HCCD Barrier Phase 2, Quadrant A
Ground
H2Bb
H1BEMb
VDD23ab
N/C
HCCD Barrier Phase 2, Quadrant B
EMCCD barrier phase 1, Quadrant B
Amplifier 2 and 3 Supply, Quadrants A, B
No Connection
RG2a
N/C
Amplifier 2 Reset, Quadrant B
No Connection
V3B
VCCD Bottom Phase 3
ESD
ESD Protection Disable
DEVID
V4B
Device ID Resistor
VCCD Bottom Phase 4
VOUT1a
Amplifier 1 Output, Quadrant A
www.onsemi.com
5
KAE−02150
Table 4. PIN DESCRIPTION (continued)
Pin
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
Label
VOUT2a
H2SW3a
VOUT3a
H2BEMa
H1Ba
Description
Video Output 2, Quadrant A
HCCD Output 3 Selector, Quadrant A
Video Output 3, Quadrant A
EMCCD Barrier Phase 2, Quadrant A
HCCD Barrier Phase 1, Quadrant A
Ground
GND
H1Bb
HCCD Barrier Phase 1, Quadrant B
EMCCD Barrier Phase 2, Quadrant B
Video Output 3, Quadrant B
HCCD Output 3 Selector, Quadrant B
Video Output 2, Quadrant B
Amplifier 1 Output, Quadrant B
VCCD Bottom Phase 4
H2BEMb
VOUT3b
H2SW3b
VOUT2b
VOUT1b
V4B
SUB
Substrate
V1B
VCCD Bottom Phase 1
N/C
No Connection
VSS1a
VDD23ab
H2SW2a
N/C
Amplifier 1 Return, Quadrant A
Amplifier 2 and 3 Supply, Quadrants A, B
HCCD Output 2 Selector, Quadrant A
No Connection
H1SEMa
H2Sa
EMCCD Storage Multiplier Phase 1, Quadrant A
HCCD Storage Phase 2, Quadrant A
Ground
GND
H2Sb
HCCD Storage Phase 2, Quadrant B
EMCCD Storage Multiplier Phase 1, Quadrant B
No Connection
H1SEMb
N/C
H2SW2b
VDD23ab
VSS1b
N/C
HCCD Output 2 Selector, Quadrant B
Amplifier 2 and 3 Supply, Quadrants A, B
Amplifier 1 Return, Quadrant B
No Connection
V1B
VCCD Bottom Phase 1
V2B
VCCD Bottom Phase 2
VDD1a
RG1a
Amplifier 1 Supply, Quadrant A
Amplifier 1 Reset, Quadrant A
H2Xa
Floating Gate Exit HCCD Gate, Quadrant A
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant A
Amplifier 3 Reset, Quadrant A
H2La
RG3a
H2SEMa
H1Sa
EMCCD Storage Multiplier Phase 2, Quadrant A
HCCD Storage Phase 1, Quadrant A
Ground
GND
H1Sb
HCCD Storage Phase 1, Quadrant B
EMCCD Storage Multiplier Phase 2, Quadrant B
Amplifier 3 Reset, Quadrant B
H2SEMb
RG3b
H2Lb
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant B
Floating Gate Exit HCCD Gate, Quadrant B
H2Xb
www.onsemi.com
6
KAE−02150
Table 4. PIN DESCRIPTION (continued)
Pin
D15
D16
D17
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
G01
G02
G03
G04
G05
G06
G07
G08
Label
RG1b
VDD1b
V2B
Description
Amplifier 1 Reset, Quadrant B
Amplifier 1 Supply, Quadrant B
VCCD Bottom Phase 2
V2T
VCCD Top Phase 2
VDD1c
RG1c
Amplifier 1 Supply, Quadrant C
Amplifier 1 Reset, Quadrant C
Floating Gate Exit HCCD Gate, Quadrant C
H2Xc
H2Lc
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant C
Amplifier 3 Reset, Quadrant C
EMCCD Storage Multiplier Phase 2, Quadrant C
HCCD Storage Phase 1, Quadrant C
Ground
RG3c
H2SEMc
H1Sc
GND
H1Sd
HCCD Storage Phase 1, Quadrant D
EMCCD Storage Multiplier Phase 2, Quadrant D
Amplifier 3 Reset, Quadrant D
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant D
Floating Gate Exit HCCD Gate, Quadrant D
Amplifier 1 Reset, Quadrant D
Amplifier 1 Supply, Quadrant D
VCCD Top Phase 2
H2SEMd
RG3d
H2Ld
H2Xd
RG1d
VDD1d
V2T
V1T
VCCD Top Phase 1
N/C
No Connection
VSS1c
VDD23cd
H2SW2c
N/C
Amplifier 1 Return, Quadrant C
Amplifier 2 and 3 Supply, Quadrants C, D
HCCD Output 2 Selector, Quadrant C
No Connection
H1SEMc
H2Sc
EMCCD Storage Multiplier Phase 1, Quadrant C
HCCD Storage Phase 2, Quadrant C
Ground
GND
H2Sd
HCCD Storage Phase 2, Quadrant D
EMCCD Storage Multiplier Phase 1, Quadrant D
No Connection
H1SEMd
N/C
H2SW2d
VDD23cd
VSS1d
N/C
HCCD Output 2 Selector, Quadrant D
Amplifier 2 and 3 Supply, Quadrants C, D
Amplifier 1 Return, Quadrant D
No Connection
V1T
VCCD Top Phase 1
ESD
ESD Protection Disable
V4T
VCCD Top Phase 4
VOUT1c
VOUT2c
H2SW3c
VOUT3c
H2BEMc
H1Bc
Amplifier 1 Output, Quadrant C
Video Output 2, Quadrant C
HCCD Output 3 Selector, Quadrant C
Video Output 3, Quadrant C
EMCCD Barrier Phase 2, Quadrant C
HCCD Barrier Phase 1, Quadrant C
www.onsemi.com
7
KAE−02150
Table 4. PIN DESCRIPTION (continued)
Pin
G09
G10
G11
G12
G13
G14
G15
G16
G17
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
Label
GND
Description
Ground
H1Bd
HCCD Barrier Phase 1, Quadrant D
EMCCD Barrier Phase 2, Quadrant D
Video Output 3, Quadrant D
HCCD Output 3 Selector, Quadrant D
Video Output 2, Quadrant D
Amplifier 1 Output, Quadrant D
VCCD Top Phase 4
H2BEMd
VOUT3d
H2SW3d
VOUT2d
VOUT1d
V4T
SUB
Substrate
TD
Temperature Diode Sensor
VCCD Top Phase 3
V3T
N/C
No Connection
RG2c
Amplifier 2 Reset, Quadrant C
No Connection
N/C
VDD23cd
H1BEMc
H2Bc
Amplifier 2 and 3 Supply, Quadrants C, D
EMCCD Barrier Phase 1, Quadrant C
HCCD Barrier Phase 2, Quadrant C
Ground
GND
H2Bd
HCCD Barrier Phase 2, Quadrant D
EMCCD Barrier Phase 1, Quadrant D
Amplifier 2 and 3 Supply, Quadrants C, D
No Connection
H1BEMd
VDD23cd
N/C
RG2d
N/C
Amplifier 2 Reset, Quadrant D
No Connection
V3T
VCCD Top Phase 3
SUBREF
Substrate Voltage Reference
www.onsemi.com
8
KAE−02150
IMAGING PERFORMANCE
Table 5. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Description
Light Source
Condition
Continuous Red, Green and Blue LED Illumination
Nominal Operating Voltages and Timing
0°C
Notes
1
Operation
Temperature
1. For monochrome sensor, only green LED used.
Table 6. SPECIFICATIONS
Sampling
Plan
Temperature
Tested at (5C)
Description
Symbol
Min.
Nom.
Max.
Units
Notes
Dark Field Global
Non-Uniformity
DSNU
−
−
2.0
mV pp
Die
TBD
TBD
TBD
TBD
Bright Field Global
Non-Uniformity
−
−
−
−
2.0
5.0
1.0
2
5.0
15.0
2.0
−
% rms
% pp
% rms
%
Die
1
1
1
2
Bright Field Global Peak to
Peak Non-Uniformity
PRNU
Die
Bright Field Center
Non-Uniformity
Die
Maximum Photoresponse
Nonlinearity
(EMCCD Gain = 1)
NL
DG
Design
Maximum Gain Difference
Between Outputs
(EMCCD Gain = 1)
−
−
10
1
−
−
%
%
Design
Design
2
2
Maximum Signal Error due
to Nonlinearity Differences
(EMCCD Gain = 1)
DNL
−
Horizontal CCD Charge
Capacity
H
Ne
V
Ne
P
Ne
−
30
30
−
−
ke
Design
Design
Die
−
Vertical CCD Charge
Capacity
−
ke
−
Photodiode Charge
Capacity
−
20
−
ke
TBD
3
Horizontal CCD Charge
Transfer Efficiency
HCTE
VCTE
0.999995
0.999995
−
0.999999
0.999999
0.1
−
Die
Vertical CCD Charge
Transfer Efficiency
−
Die
−
Photodiode Dark Current
(Average)
I
70
e /p/s
Die
0
0
PD
Vertical CCD Dark Current
Image Lag
−
6
−
−
< 1
−
TBD
−
Lag
−
1,000
−
e
Design
Design
Design
Design
Antiblooming Factor
Vertical Smear (blue light)
X
AB
−
Smr
−100
9
−
dB
−
−
Read Noise
n
−
−
e rms
4
e T
(EMCCD Gain = 1)
−
Read Noise
(EMCCD Gain = 20)
−
−
< 1
1.4
−
−
e rms
EMCCD Excess Noise
Factor (Gain = 20x)
Design
0
www.onsemi.com
9
KAE−02150
Table 6. SPECIFICATIONS (continued)
Sampling
Plan
Temperature
Tested at (5C)
Description
Dynamic Range
Symbol
Min.
Nom.
Max.
Units
Notes
DR
−
68
−
dB
Design
4, 5
(ECCD Gain = 1)
Dynamic Range
(High Gain)
−
−
60
86
−
−
dB
dB
V
Dynamic Range
(Intra-Scene)
Output Amplifier DC Offset
(VOUT2, VOUT3)
V
V
8.0
−0.5
−
10
12.0
2.5
−
Die
Die
TBD
TBD
ODC
ODC
−3dB
Output Amplifier DC Offset
(VOUT1)
1.0
250
140
44
V
Output Amplifier
Bandwidth
f
MHz
W
Die
6
Output Amplifier
Impedance
R
−
−
Die
OUT
−
Output Amplifier
DV/DN
−
−
mV/e
Design
Design
Sensitivity (Normal output)
−
Output Amplifier
Sensitivity
DV/DN
(FG)
−
6.2
−
mV/e
(Floating Gate Amplifier)
Quantum Efficiency (Peak)
Monochrome
Red
Green
Blue
QE
%
W
Design
Design
MAX
−
−
−
−
50%
33%
41%
43%
−
−
−
−
Power
4-Output Mode
(20MHz)
(40MHz)
−
−
0.8
0.7
−
−
2-Output Mode
(20MHz)
(40MHz)
−
−
0.5
0.5
−
−
1-Output Mode
(20MHz)
(40MHz)
−
−
0.4
0.4
−
−
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate reference voltage, V , can be read from pin 60.
AB
4. At 40 MHz.
5. Uses 20LOG (P / n ).
Ne
e−T
6. Calculated from f
= 1 / 2p ⋅ R
⋅ C
LOAD
where C
= 5 pF.
−3dB
OUT
LOAD
www.onsemi.com
10
KAE−02150
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
60
50
40
30
20
10
0
1,000
300
400
500
600
700
800
900
Wavelength (nm)
Figure 5. Monochrome QE with Microlens
Color (Bayer RGB) with Microlens
45
40
35
30
Red
Green
Blue
25
20
15
10
5
0
1,000
350
400
450
500
550
600
650
700 750
800
850
900
950
Wavelength (nm)
Figure 6. Color (Bayer RGB) QE with Microlens
www.onsemi.com
11
KAE−02150
Angular Response
The incident light angle is varied in a plane parallel to the HCCD.
Monochrome with Microlens
100
90
80
70
60
50
40
30
20
10
0
−30
−20
−10
0
10
20
30
Angle (Deg)
Figure 7. Monochrome with Microlens Angle Response
Color (Bayer RGB) with Microlens
100
90
80
70
60
50
40
30
20
10
0
Red
Green
Blue
−30
−20
−10
0
10
20
30
Angle (Deg)
Figure 8. Color with Microlens Angle Response
www.onsemi.com
12
KAE−02150
Frame Rates
80
70
60
50
40
30
20
10
0
Quad
Dual
Single
10
15
20
25
30
35
40
Frequency (MHz)
Figure 9. Frame Rates vs. Frequency
www.onsemi.com
13
KAE−02150
DEFECT DEFINITIONS
Table 7. DEFECT DEFINITIONS
Description
Threshold/Definition
≥ 10 mV
Maximum Number Allowed
Notes
Major Dark Field Defective Bright Pixel
Major Bright Field Defective Dark Pixel
Minor Dark Field Defective Bright Pixel
Cluster Defect
20
1, 2
≥ 12%
≥ 5 mV
200
8
A Group of 2 to 10 Contiguous Major Defective
Pixels No Greater than 2 Pixels in Width
3
Column Defect
A Group of More than 10 Contiguous Major
Dark Defective Pixels along a Single Column or
10 Contiguous Bright Defective Pixels along
a Single Column
0
3, 4
1. The thresholds are defined for an operating temperature of 0°C, quad output mode, gain of 20X and a readout rate of 20 MHz. For operation
at 22°C, thresholds of 30 mV for major bright pixels and 10 mV for minor bright pixels would give approximately the same numbers of defects.
2. For the color device, a bright field defective pixel deviates by 12% with respect to pixels of the same color.
3. Column and cluster defects are separated by no less than 2 good pixels in any direction (excluding single pixel defects).
4. Low exposure dark column defects are not counted at temperatures above 0°C.
www.onsemi.com
14
KAE−02150
OPERATION
Table 8. ABSOLUTE MAXIMUM RATINGS
(Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the
condition is exceeded, the device will be degraded and may be damaged. Operation at these values will reduce MTTF.)
Description
Operating Temperature
Humidity
Symbol
Minimum
Maximum
Units
°C
Notes
T
OP
−70
5
40
90
5
1
2
3
RH
%
Output Bias Current
Off-Chip Load
I
−
mA
pF
OUT
CL
−
10
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 9. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description
Minimum
−0.4
Maximum
17.5
Units
Notes
VDD23ab, VDD23cd
VOUT2, VOUT3
VDD1, VOUT1
V1B, V1T
V
V
V
V
V
V
1
−0.4
15
−0.4
7.0
ESD – 0.4
ESD – 0.4
– 0.4
ESD + 22.0
ESD + 14.0
10
V2B, V2T, V3B, V3T, V4B, V4T
H1S, H1B, H2S, H2B, H1BEM, H2BEM, H2SL, H2X,
H2SW2, H2SW3, RG1, RG2, RG3
1
H1SEM, H2SEM
−0.4
−9.0
6.5
20
0.0
40
V
V
V
ESD
SUB
2, 3
1. “a” denotes a, b, c or d.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
3. The measured value for VSUB is a diode drop higher than the recommended minimum VSUB bias.
REF
Power-Up and Power-Down Sequence
SUB and ESD power up first, then power up all other
biases in any order. No pin may have a voltage less than ESD
at any time. All HCCD pins must be greater than or equal to
until VDD23ab has been powered, therefore the SUB
voltage cannot be directly derived from the SUB
pin.
REF
The SUB pin should be at least 4 V before powering up
VDD23ab or VDD23cd.
GND at all times. The SUB
pin will not become valid
REF
Table 10. DC BIAS OPERATING CONDITIONS
Maximum
DC Current
Description
Output Amplifier Return
Output Amplifier Supply
Output Amplifier Supply
Ground
Pins
VSS1
VDD1
VDD23
GND
Symbol
Minimum
−8.3
Nominal
−8.0
Maximum
−7.7
Units
Notes
V
SS1
V
V
V
V
V
4 mA
V
DD1
4.5
5.0
6.0
15 mA
V
DD23
+14.7
0.0
+15.0
0.0
+15.3
0.0
37.0 mA
17.0 mA
1
2
GND
Substrate
SUB
V
SUB
6.5
VSUB
VSUB
REF
+ 28
Up to 1 mA
(Determined by
Photocurrent)
REF
− 0.5
ESD Protection Disable
Output Bias Current
ESD
ESD
−8.3
2.0
−8.0
−7.7
5.0
V
0.25 mA
VOUT
I
2.5
mA
OUT
1. VDD bias pins for all four quadrants must be maintained at 15 V during operation.
2. For each image sensor the voltage output on the VSUB pin is programmed to be one diode drop, 0.5 V, above the nominal SUB voltage.
REF
The voltage output on VSUB
is unique to each image sensor and may vary from 6.5 to 10.0 V. The output impedance of VSUB
is
REF
REF
approximately 100 k. The applied VSUB should be one diode drop lower than the VSUB
value measured on the device, when V
REF
DD23
is at the specified voltage.
www.onsemi.com
15
KAE−02150
AC Operating Conditions
Table 11. CLOCK LEVELS
HCCD and RG
Low Level
Nominal
0.0
Amplitude
Low
−0.2
−0.2
−0.2
−0.2
−0.2
−0.2
−0.2
High
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Low
3.1
3.1
3.1
3.1
3.1
3.1
6.0
3.1
3.1
4.6
4.6
7.0
7.0
Nominal
3.3
3.3
3.3
3.3
3.3
3.3
6.4
3.3
3.3
5.0
5.0
−
High
3.6
3.6
3.6
3.6
3.6
3.6
6.8
3.6
3.6
5.4
5.4
18.0
18.0
Pin
Function
H2B(a,b,c,d)
Reversible HCCD Barrier 2
Reversible HCCD Barrier 1
Reversible HCCD Storage 2
Reversible HCCD Storage 1
HCCD Switch 2 and 3
HCCD Last Gate
H1B(a,b,c,d)
0.0
H2S(a,b,c,d)
0.0
H2B(a,b,c,d)
0.0
H2SW(2,3)(a,b,c,d)
H2L(a,b,c,d)
0.0
0.0
H2X(a,b,c,d)
Floating Gate Exit
0.0
RG1(a,b,c,d)
Floating Gate Reset
Cap
Cap
0.0
RG(2,3)(a,b,c,d)
H1BEM(a,b,c,d)
H2BEM(a,b,c,d)
H1SEM(a,b,c,d)
H2SEM(a,b,c,d)
Floating Diffusion Reset
Multiplier Barrier 1
−0.2
−0.2
−0.3
−0.3
0.2
0.2
0.3
0.3
Multiplier Barrier 2
0.0
Multiplier Storage 1
0.0
Multiplier Storage 2
0.0
−
1. HCCD Operating Voltages. There can be no overshoot on any horizontal clock below −0.4 V: the specified absolute minimum. The H1SEM
and H2SEM clock amplitudes need to be software programmable to adjust the charge multiplier gain.
2. Reset Clock Operation: The RG1, RG2, and RG3 signals must be capacitive coupled into the image sensor with a 0.01 mF to 0.1 mF capacitor.
The reset clock overshoot can be no greater than 0.3 V, as shown in Figure 10, below:
3.1 V Minimum
0.3 V Maximum
Figure 10. RG Clock Overshoot
Clock Capacitances
Capacitance
(pF)
Capacitance
(pF)
Capacitance
(pF)
Capacitance
(pF)
Pin
Pin
Pin
Pin
H1Sa
H1Sb
H1Sc
H1Sd
H2Sa
H2Sb
H2Sc
H2Sd
76
76
76
76
76
76
76
76
H1Ba
H1Bb
H1Bc
H1Bd
H2Ba
H2Bb
H2Bc
H2Bd
39
39
39
39
39
39
39
39
H1BEMa
H1BEMb
H1BEMc
H1BEMd
H2BEMa
H2BEMb
H2BEMc
H2BEMd
56
56
56
56
56
56
56
56
H1SEMa
H1SEMb
H1SEMc
H1SEMd
H2SEMa
H2SEMb
H2SEMc
H2SEMd
66
66
66
66
66
66
66
66
NOTE: The capacitances of all other HCCD pins is 15 pF or less.
www.onsemi.com
16
KAE−02150
H1SEMa
H2SEMa
High
Low
+18 V
H1SEMb
H2SEMb
High
Low
A
B
4 Output
DAC
C
D
H1SEMc
H2SEMc
High
Low
H1SEMd
H2SEMd
High
Low
Figure 11. EMCCD Clock Adjustable Levels
For the EMCCD clocks, each quadrant must have
independently adjustable high levels. All quadrants have
a common low level of GND. The high level adjustments
must be software controlled to balance the gain of the four
outputs.
3.3 V
0 to 75 W
RG1 Clock
Generator
RG1
0.01 to 0.1 mF
3.3 V
0 to 75 W
RG2
RG2,3 Clock
Generator
RG3
0.01 to
0.1 mF
Figure 12. Reset Clock Drivers
The reset clock drivers must be coupled by capacitors to
the image sensor. The capacitors can be anywhere in the
vary between 0 and 75 W depending on the layout of the
circuit board.
range 0.01 to 0.1 mF. The damping resistor values would
www.onsemi.com
17
KAE−02150
Table 12. VCCD
Pin
Function
Low
−8.0
−0.2
8.5
Nominal
−8.0
0
High
−6
V(1,2,3,4)(T,B)
V(1,2,3,4)(T,B)
V(1)(T,B)
Vertical CCD Clock, Low Level
Vertical CCD Clock, Mid Level
0.2
rd
Vertical CCD Clock, High (3 ) Level
9.0
12.5
1. The Vertical CCD operating voltages. The VCCD low level will be −8.0 V for operating temperatures of 0°C and above. Below 0°C the VCCD
low level should be increased for optimum noise performance.
Table 13. BIAS VOLTAGES
Pin
Function
Low
Nominal
−8.0
−
High
ESD
ESD
−8.3
−7.7
SUB (Notes 1, 2)
VDD1(a,b,c,d)
Electronic Shutter
VSUB
+ 22
VSUB
+ 28
REF
REF
Floating Gate Power
4.5
5.0
6.0
VSS1(a,b,c,d)
Floating Gate Return
−8.3
14.7
−0.5
8.0
−8.0
15.0
1.0
−7.7
15.3
2.5
VDD(2,3)(a,b,c,d)
VOUT1(a,b,c,d)
VOUT(2,3)(a,b,c,d)
Floating Diffusion Power
Floating Gate Output Range
Floating Diffusion Output Range
10.0
12.0
1. Caution: Do not clock the EMCCD register while the electronic shutter pulse is high.
2. The substrate bias (SUB) should normally be kept at V , which can be read from Pin 60. However, this value was determined from operation
AB
at 0°C, and has an approximate temperature dependence of 0.01 V/degree.
Device Identification
The device identification pin (DevID) may be used to
determine which ON Semiconductor 5.5 micron pixel
interline CCD sensor is being used.
Table 14. DEVICE IDENTIFICATION
Maximum
DC Current
Description
Pins
Symbol
Minimum
Nominal
Maximum
Units
Notes
Device Identification
DevID
DevID
44,000
50,000
56,000
W
0.3 mA
1, 2, 3
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor.
Recommended Circuit
V1
V2
R_External
DevID
GND
ADC
R_DeviceID
KAE−02150
Figure 13. Device Identification Recommended Circuit
www.onsemi.com
18
KAE−02150
THEORY OF OPERATION
Image Acquisition
Photo
Diode
Figure 14. Illustration of 2 Columns and 3 Rows of Pixels
This image sensor is capable of detecting up to
20,000 electrons with a small signal noise floor of 1 electron
all within one image. Each 5.5 mm square pixel, as shown in
Figure 14 above, consists of a light sensitive photodiode and
a portion of the vertical CCD (VCCD). Not shown is
a microlens positioned above each photodiode to focus light
away from the VCCD and into the photodiode. Each photon
incident upon a pixel will generate an electron in the
photodiode with a probability equal to the quantum
efficiency.
The VCCD is shielded from light by metal to prevent
detection of more photons. For very bright spots of light,
some photons may leak through or around the metal light
shield and result in electrons being transferred into the
VCCD. This is called image smear.
Image Readout
At the start of image readout, the voltage on the V1T and
V1B pins is pulsed from 0 V up to the high level for at least
1 ms and back to 0 V, which transfers the electrons from the
photodiodes into the VCCD. If the VCCD is not empty, then
the electrons will be added to what is already in the VCCD.
The VCCD is read out one row at a time. During a VCCD
row transfer, the HCCD clocks are stopped. All gates of type
H1 stop at the high level and all gates of type H2 stop at the
low level. After a VCCD row transfer, charge packets of
electrons are advanced one pixel at a time towards the output
amplifiers by each complimentary clock cycle of the H1 and
H2 gates.
The charge multiplier has a maximum charge handling
capacity (after gain) of 20,000 electrons. This is not the
average signal level. It is the maximum signal level.
Therefore, it is advisable to keep the average signal level at
15,000 electrons or less to accommodate a normal
distribution of signal levels. For a charge multiplier gain of
20x, no more than 15,000/20 = 750 electrons should be
allowed to enter the charge multiplier. Overfilling the charge
multiplier beyond 20,000 electrons will shorten its useful
operating lifetime. In addition, sending signals larger than
180–200 electrons into the EMCCD will produce images
with lower signal-to-noise ratio than if they were read out of
the normal floating diffusion output. See Application Note
AND9244.
The photodiode may be cleared of electrons (electronic
shutter) by pulsing the SUB pin of the image sensor up to
a voltage of 30 V to 40 V (VSUB
+ 22 V to VSUB
REF
REF
+ 28 V) for a time of at least 1 ms. When the SUB pin is
above 30 V, the photodiode can hold no electrons, and the
electrons flow downward into the substrate. When the
voltage on SUB drops below 30 V, the integration of
electrons in the photodiode begins. The HCCD clocks
should be stopped when the electronic shutter is pulsed, to
avoid having the large voltage pulse on SUB coupling into
the video outputs and altering the EMCCD gain.
It should be noted that there are certain conditions under
which the device will have no anti-blooming protection:
when the V1T and V1B pins are high, very intense
illumination generating electrons in the photodiode will
flood directly into the VCCD. When the electronic shutter
pulse overlaps the V1T and V1B high-level pulse that
transfers electrons from the photodiode to the VCCD, then
photo-electrons will flow to the substrate and not the VCCD.
This condition may be desirable as a means to obtain very
short integration times.
www.onsemi.com
19
KAE−02150
To prevent overfilling the charge multiplier,
a non-destructive floating gate output amplifier (VOUT1) is
provided on each quadrant of the image sensor as shown in
Figure 15.
To VOUT2
VOUT1
4 Clock Cycles
28 Clock Cycles
1 Clock Cycle
1 Clock
Cycle
10 Clock Cycles
24 Clock Cycles
From the Dark
VCCD Columns
From the Photo-Active
VCCD Columns
SW
Empty Pixels
FG
Empty Pixels
Charge Transfer
2072 Clock Cycles
To the Charge Multiplier
and VOUT3
Figure 15. The Charge Transfer Patch of One Quadrant
The non-destructive floating gate output amplifier is able
to sense how much charge is present in a charge packet
without altering the number of electrons in that charge
packet. This type of amplifier has a low charge-to-voltage
The transfer sequence of a charge packet through the
floating gate amplifier is shown in Figure 16 below.
The time steps of this sequence are labeled A through D, and
are indicated in the timing diagram shown as Figure 17.
The RG1 gate is pulse high during the time that the H2X gate
is pulsed high. This holds the floating gate at a constant
voltage so the H2X gate can pull the charge packet out of the
floating gate. The RG1 pulse should be at least as wide as the
H2X pulse. The H2X pulse width should be at least 12 ns.
The rising edge of H2X relative to the falling edge of H1S
is critical. The H2X pulse cannot begin its rising edge
transition until the H1S edge is less than 0.4 V. If the H2X
rising edge comes too soon then there may be some
backwards flow of charge for signals above
10,000 electrons.
−
conversion gain (about 6.2 mV/e ) and high noise (about
60 electrons), but it is being used only as a threshold
detector, and not an imaging detector. Even with
60 electrons of noise, it is adequate to determine whether
a charge packet is greater than or less than the recommended
threshold of 180 electrons.
After one row has been transferred from the VCCD into
the HCCD, the HCCD clock cycles should begin. After 10
clock cycles, the first dark VCCD column pixel will arrive
at VOUT1. After another 24 (34 total) clock cycles, the first
photo-active charge packet will arrive at VOUT1.
VDD1
Floating Gate Amp
V
REF
VOUT1
RG1
H2S
H1S
H2X
OG1
H2L
H1S
A
B
C
D
Channel
Potential
NOTE: The blue and green rectangles represent two separate charge packets. The direction of charge transfer is from right to left.
Figure 16. Charge Packet Transfer Sequence through the Floating Gate Amplifier
www.onsemi.com
20
KAE−02150
A
B
C
D
H1S
50%
50%
10%
90%
H2S
H2X
10%
RG1
VOUT1
Figure 17. Timing Signals that Control the Transfer of Charge through the Floating Gate Amplifier
The charge packet is transferred under the floating gate on
the falling edge of H2L. When this transfer takes place the
floating gate is not connected to any voltage source.
The presence of charge under the gate causes a change in
voltage on the floating gate according to V = Q / C, where
Q is the size of the charge packet and C is the capacitance of
H2SW3 pins to route the charge packet to the charge
multiplier. This action must take place 28 clock cycles after
the charge packet was under the floating gate amplifier.
The 28 clock cycle delay is to allow for pipeline delays of the
A/D converter inside the analog front end. The timing
generator must examine the output of the analog front end
and dynamically alter the timing on H2SW2 and H2SW3. To
route a charge packet to the charge multiplier (VOUT3),
H2SW2 is held at GND and H2SW3 is clocked with the
same timing as H2S for that one clock cycle. To route
a charge packet to the low gain output amplifier (VOUT2),
H2SW3 is held at GND and H2SW2 is clocked with the
same timing as H2S for that one clock cycle.
−
the floating gate. With an output sensitivity of 6.2 mV/e ,
each electron on the floating gate would give a 6.2 mV
change in VOUT1 voltage. Therefore if the decision
threshold is to only allow charge packets of 180 electrons or
less into the charge multiplier, this would correspond to
180 × 6.2 = 1.1 mV. If the video output is less than 1.1 mV,
then the camera must set the timing of the H2SW2 and
www.onsemi.com
21
KAE−02150
EMCCD OPERATION
H1BEM H2SEM
H2BEM H1SEM H1BEM H2SEM H2BEM H1SEM
A
B
C
Channel
Potential
D
NOTE: Charge flows from right to left.
Figure 18. The Charge Multiplication Process
The charge multiplication process, shown in Figure 18
above, begins at time step A, when an electron is held under
the H1SEM gate. The H2BEM and H1BEM gates block the
electron from transferring to the next phase until the H2SEM
has reached its maximum voltage. When the H2BEM is
clocked from 0 to 5 V, the channel potential under H2BEM
increases until the electron can transfer from H1SEM to
H2SEM. When the H2SEM gate is above 10 V, the electric
field between the H2BEM and H2SEM gates gives the
electron enough energy to free a second electron which is
collected under H2SEM. Then the voltages on H2BEM and
H2SEM are both returned to 0 V at the same time that
H1SEM is ramped up to its maximum voltage. Now the
process can repeat again with charge transferring into the
H1SEM gate.
The alignment of clock edges is shown in Figure 19.
The rising edge of the H1BEM and H2BEM gates must be
delayed until the H1SEM or H2SEM gates have reached
their maximum voltage. The falling edge of H1BEM and
H2BEM must reach 0 V before the H1SEM or H2SEM
reach 0 V. There are a total of 1,800 charge multiplying
transfers through the EMCCD on each quadrant.
www.onsemi.com
22
KAE−02150
A
B
C
D
H2S
100%
H2SEM
H2BEM
0%
100%
H1SEM
H1BEM
0%
Figure 19. The Timing Diagram for Charge Multiplication
The amount of gain through the EMCCD will depend on
temperature and H1SEM and H2SEM voltage as shown in
Figure 20. Gain also depends on substrate voltage, as shown
in Figure 21, and on the input signal, as shown in Figure 22.
100
10
0
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
EMCCD Voltage
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 20. The Variation of Gain vs. EMCCD High Voltage and Temperature
www.onsemi.com
23
KAE−02150
15.4
15.2
T = 0°C
15.0
14.8
14.6
14.4
14.2
6
7
8
9
10
11
12
13
VSUB (V)
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 21. The Change in the Required EMCCD Voltage for a Gain of 20x vs. the Substrate Voltage
22
21
20
19
18
17
16
0
50
100
150
200
250
300
Input Signal (e)
NOTE: The EMCCD voltage was set to provide 20x gain with an input of 180 electrons.
Figure 22. EMCCD Gain vs. Input Signal
If more than one output is used, then the EMCCD high
level voltage must be independently adjusted for each
quadrant. This is because each quadrant will require
a slightly different voltage to obtain the same gain. In
addition, the voltage required for a given gain differs
unpredictably from one image sensor to the next, as in
Figure 23. Because of this, the gain vs. voltage relationship
must be calibrated for each image sensor, although within
each quadrant, the H1SEM and H2SEM high level voltage
should be equal.
www.onsemi.com
24
KAE−02150
100
10
1
9
10
11
12
13
14
15
H1SEM, H2SEM High Level (V)
Figure 23. An Example Showing How Two Image Sensors Can Have Different Gain vs. Voltage Curves
The effective output noise of the image sensor is defined
as the noise of the output signal divided by the gain. This is
measured with zero input signal to the EMCCD. Figures 24
and 25 show the EMCCD by itself has a very low noise that
goes as the noise at gain = 1 divided by the gain. The
EMCCD has very little clock-induced charge and does not
require elaborate sinusoidal waveform clock drivers.
Simple square wave clock drivers with a resistor between the
driver and sensor for a small RC time constant are all that is
needed. However, the pixel array may acquire spurious
charge as a function of VCCD clock driver characteristics.
Also, the VCCD is sensitive to hot electron luminescence
emitted from the output amplifiers during image readout.
These two factors limit the noise floor of the total imaging
array.
10
1
0.1
0.01
1
10
100
Gain
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 24. EMCCD Output Noise vs. EMCCD Gain in Single Output Mode at −50 to 225C
www.onsemi.com
25
KAE−02150
10
1
0.1
0.01
1
10
100
Gain
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 25. EMCCD Output Noise vs. EMCCD Gain in Quad Output Mode at −50 to 225C
Because of these pixel array noise sources, it is
recommended that the maximum gain used be 40x at 0°C,
which typically gives a noise floor between 1e and 0.4e.
Using higher gains will provide limited benefit and will
degrade the signal to noise ratio due to the EMCCD excess
noise factor. Furthermore, the image sensor is not limited by
dark current noise sources when the temperature is below
25°C. Therefore, cooling below 25°C will not provide
a significant improvement to the noise floor. Lower
temperatures will reduce the number of hot pixel defects
observed only during image integration times longer than
1 s. Note the useful plot below:
1,000
100
10
1
13.0
13.5
14.0
14.5
15.0
15.5
EMCCD Voltage
CAUTION: The EMCCD should not be operated near saturation for an extended period, as this may result in gain aging and
permanently reduce the gain. It should be noted that device degradation associated with gain aging is not covered under
the device warranty.
Figure 26. Gain vs. Voltage with Maximum Recommended Operating Gains Marked
www.onsemi.com
26
KAE−02150
Choosing the Operating Temperature
The reasons for lowering the operating temperature are to
reduce dark current noise and to reduce image defects.
The average dark signal from the VCCD and photodiodes
must be less than 1e in order to have a total system noise less
than 1e when using the EMCCD. Figures 27 and 28 illustrate
how the amount of dark signal in the VCCD is dependent on
both temperature and voltage, and may be used to choose the
operating temperature and VCCD clock low level voltage.
When operating in quad output mode at 0°C either −6 V
or −8 V may be used for the VCCD clock low level voltage
because the dark signal will be equal. But if the operating
temperature is −20°C then the VCCD clock low level
voltage should be set to −6 V for the lowest VCCD dark
signal. For single output mode, the VCCD clock low level
voltage should be set to −6 V for temperatures of −10°C or
lower and −8 V for temperatures of −10°C or higher.
1.0
0.8
0.6
0.4
0.2
0.0
−50
−40
−30
−20
−10
0
10
20
Temperature (5C)
NOTE: Both are for a HCCD frequency of 20 MHz. The VCCD low level voltage is shown for each curve.
Figure 27. Dark Signal from VCCD in Quad and Single Output Modes
1.0
0.8
0.6
0.4
0.2
0.0
−50
−40
−30
−20
−10
0
10
20
Temperature (5C)
Figure 28. Dark Signal from VCCD in Dual Output Mode at HCCD Frequency 20 MHz
The reason for the different temperature dependencies
with the VCCD low level voltage at −6 V vs. −8 V is spurious
charge generation (sometimes called clock-induced charge).
When the VCCD low level is at −8 V, the VCCD is
accumulated with holes, which reduces the rate of dark
current signal generation. However, the amount of clock
induced charge is greater. At VCCD low level of −6 V,
the VCCD is no longer accumulated with holes. So,
clock-induced charge generation is less, but dark current is
increased.
www.onsemi.com
27
KAE−02150
In quad output mode, the clock induced charge generated
In addition to dark noise, image defects also impact the
optimum operating temperature. Although the average
photodiode dark current is negligible at temperatures below
20°C, as shown by Figure 29, the number of photodiode
hot-pixel defects is a function of temperature and will
decrease with lower temperature.
and the dark current signal are equal at T = 0°C. Below
T = 0°C, the dark current signal is smaller than the clock
induced charge, so −6 V is the best voltage. Above T = 0°C,
the dark current signal dominates, and −8 V is the best
voltage. The dark signal stops decreasing below T = −20°C
because the VCCD is detecting hot electron luminescence
from the output amplifiers during image readout.
0.1000
0.0100
0.0010
0.0001
−30
−20
−10
0
10
20
Temperature (5C)
Figure 29. Photodiode Dark Current vs. Temperature
−
Note that the preceding figures are representative data
only, and are not intended as a defect specification.
to at least 3 times the floating gate amplifier noise, or 180 e .
−
Sending signals larger than 180 e into the EMCCD will
produce images with lower S/N than if they were read out of
the normal floating diffusion output of VOUT2. See
Application Note AND9244.
Choosing the Charge Switch Threshold
The floating gate output amplifier (VOUT1) is used to
decide the routing of a pixel at the charge switch. Pixels with
large signals should be routed to the normal floating
diffusion amplifier at VOUT2. Pixels with small signals
should be routed to the EMCCD and VOUT3. The routing
of pixels is controlled by the timing on H2SW2 and H2SW3.
The optimum signal threshold for that transition between
VOUT2 and VOUT3 is when the signal to noise ratio (S/N)
of VOUT2 is equal to the S/N of VOUT3. This signal is
given by
Temperature Diode
There is a diode integrated on the same silicon die as the
image sensor that can be used to assist temperature
regulation. It is not accurate enough to provide a calibrated
temperature value, but it can be used to maintain a constant
temperature.
The temperature is sensed by forward biasing the diode
with 50 mA of current and measuring the resulting voltage
drop. The current value most preferred is 50 mA. It is
recommended that it not be less than 40 mA or more than
60 mA.
The primary source of inaccuracy in temperature
measurement is noise contributed by other clock inputs to
the image sensor. The small amount of coupling of the other
clocks to the temperature diode is rectified by the
temperature diode and causes an offset error in the voltage
reading. The magnitude of the offset error is dependent upon
factors such as the number of outputs used, and the layout of
the camera circuit board. While the error frustrates obtaining
G ) 1
S + s2T
@
(eq. 1)
G
where G is the EMCCD gain, S is the signal level, and s is
T
the total system noise on VOUT2 in the dark. For values of
G greater than 10, the optimum signal threshold occurs when
then signal equals the square of the total system noise floor
s . Depending on the skill of the camera designer, s will
T
T
−
range from 8 to 12 e . If the camera has a total system noise
−
−
of 10 e , then the threshold should be set to 100 e . However,
the floating gate amplifier noise is approximately 60 e−, and
so would dominate, making it preferable to set the threshold
www.onsemi.com
28
KAE−02150
an accurate absolute temperature value, it is expected to be
constant and allow the diode to be used for maintaining
a constant temperature.
Figure 30 shows the forward biased voltage drop across
the diode vs. temperature with a current of 50 mA. There are
two curves showing the offset error. One curve shows the
temperature dependence with all image sensor clocks
stopped, and the second with all clocks operating at 20 MHz,
The offset between the clocks-on and clocks-off curves will
be different for every camera design.
−0.55
−0.60
−0.65
−0.70
−0.75
−0.80
−0.85
−50
−40
−30
−20
−10
0
10
20
30
40
50
Temperature (5C)
NOTE: The “clocks on” voltage curve will vary significantly from one camera design to the next.
Figure 30. Voltage Drop across Temperature Sensing Diode with Current of 50 mA
www.onsemi.com
29
KAE−02150
TIMING DIAGRAMS
Pixel Timing
50 ns
H2S, H2L
H1S
H2X
RG1
RG2
H2SEM
H2BEM
H1SEM
H1BEM
NOTE: The minimum time for one pixel is 50 ns.
Figure 31. Pixel Timing Pattern P1
www.onsemi.com
30
KAE−02150
Black Clamp, VOUT1, VOUT2, and VOUT3 Alignment
at Line Start
VOUT3 on the same clock cycle and exactly two rows after
they would have arrived at VOUT2.Changing the number of
HCCD clock cycles with introduce an offset between when
pixels arrive at VOUT2 or VOUT3.
When in single mode, each row must have exactly 2,072
HCCD clock cycles. The pixels arrive at VOUT3 on the
same clock cycle and exactly one row after they would have
arrived at VOUT2.Changing the number of HCCD clock
cycles with introduce an offset between when pixels arrive
at VOUT2 or VOUT3.
The black level clamp should start 3 clock cycles into the
line and be active for 28 clock cycles of each row. The first
photoactive pixel will arrive at the VOUT1 (floating gate)
output after 34 clock cycles. The first photoactive pixel will
arrive at either the VOUT2 or VOUT3 after 68 clock cycles,
depending on the timing of H2SW2 and H2SW3.
When in dual or quad output mode, each row must have
exactly 1,036 HCCD clock cycles. The pixels arrive at
Black Clamp
H2L
VOUT1
VOUT2, VOUT3
active pixel 1
68 pixels
34 pixels
active pixel 1
1036 H2L clock cycles
28 pixels
0.0
0.5
1.0
1.5
2.0
Time (ms)
2.5
3.0
3.5
4.0
Figure 32. Video Output at Each Line Start
H2L, VOUT1, VOUT2, and VOUT3 Alignment at End of
Line
output mode, the pixels arrive at VOUT3 one line delayed
from when they would have arrived at VOUT2. When in
dual or quad output modes, the pixels arrive at VOUT3 two
lines delayed from when they would have arrived at
VOUT2.
The last active pixel (the center column of the image),
th
arrives at VOUT2 or VOUT3 on the 1,036 clock cycle of
the HCCD. The last photoactive pixel arrives at VOUT1 34
clock cycles before VOUT2 or VOUT3. When in single
H2L
VOUT1
VOUT2, VOUT3
active pixel 968
active pixel 968
34 pixels
H2L clock cycle 1036
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Time (ms)
Figure 33. Video Output at End of Each Line for Dual or Quad Output Modes
www.onsemi.com
31
KAE−02150
VCCD Timing
Table 15. TIMING DEFINITIONS
Symbol
Note
Minimum
Nominal
0.50
1.30
1.5
Maximum
0.50
Units
ms
t
VA
VCCD Transfer Time A
0.46
0.46
1.0
t
VB
VCCD Transfer Time B
7.50
ms
t
Electronic Shutter Pulse
10.0
ms
SUB
t
3
Photodiode to VCCD Transfer Time
1.0
1.5
5.0
ms
V1, V2, V3, V4 Alignment
V1B, V1T
V2B, V4T
V3B, V3T
V4B, V2T
t
VB
t
VB
t
3
t
VB
t
VB
t
VB
t
VA
t
VA
t
VA
t
VA
Figure 34. Timing Pattern F1. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD
when Using the Bottom HCCD, Outputs A or B
V1B
V2B, V3T
V3B, V4T
V4B
V1T
V2T
t
VB
t
VB
t
3
t
VB
t
VB
t
VB
t
VA
t
VA
t
VA
t
VA
Figure 35. Timing Pattern F2. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD
when Using All Four Outputs in Quad Mode
www.onsemi.com
32
KAE−02150
V1B, V1T
V2B, V4T
V3B, V3T
V4B, V2T
t
VB
t
VB
t
VB
t
VB
t
VA
t
VA
t
VA
t
VA
Figure 36. Line Timing L1. VCCD Line Timing to Transfer One Line of Charge from VCCD to the HCCD
when Using the Bottom HCCD, Outputs A or B in Single or Dual Output Modes
V1B, V2T
V2B, V3T
V3B, V4T
V4B, V1T
t
VB
t
VB
t
VB
t
VB
t
VA
t
VA
t
VA
t
VA
Figure 37. Line Timing L2. VCCD Line Timing to Transfer One Line of Charge from VCCD to the HCCD
when Using All Four Outputs in Quad Mode
www.onsemi.com
33
KAE−02150
Electronic Shutter
V
AB
+ V
ES
VSUB
V
AB
3.3 V
0 V
HCCD
VCCD
0 V
−8 V
t
VB
t
t
VB
SUB
Last HCCD
Clock Edge
First VCCD
Clock Edge
CAUTION: Do not clock the EMCCD register while the electronic shutter pulse is high.
Figure 38. Electronic Shutter Timing Pattern S1
Clock
State
H1S
High
H2S
H2SW
H2L
Low
Low
Low
Low
High
High
Low
Low
H2X
H1SEM
H1BEM
H2SEM
H2BEM
Figure 39. The State of the HCCD and EMCCD Clocks during the Frame, Line,
and Electronic Shutter Timing Sequences
www.onsemi.com
34
KAE−02150
HCCD Timing
To reverse the direction of charge transfer in a Horizontal
CCD, exchange the timing pattern of the H1B and H2B
inputs of that HCCD. If a HCCD is not used, hold all of its
gates at the high level.
When operating in single or dual output modes,
the VDD23cd, VDD1c, and VDD1d amplifiers must still be
powered. The outputs VOUT1, VOUT2, and VOUT3 for
quadrants c and d may be left unloaded.
Table 16. HCCD TIMING
Mode
HCCD a, b Timing
H1Ba = H2Bb = H1Sa = H1Sb
HCCD c, d Timing
Single
3.3 V
H2Ba = H1Bb = H2Sa = H2Sb
Dual
H1Ba = H1Bb = H1Sa = H1Sb
H2Ba = H2Bb = H2Sa = H2Sb
3.3 V
Quad
H1Ba = H1Bb = H1Sa = H1Sb
H2Ba = H2Bb = H2Sa = H2Sb
H1Bc = H1Bd = H1Sc = H1Sd
H2Bc = H2Bd = H2Sc = H2Sd
Image Exposure and Readout
The flowchart for image exposure and readout is shown in
Figure 40. The electronic shutter timing may be omitted to
obtain an exposure time equal to the image read out time.
NEXP is the number of lines exposure time and NV is the
number of VCCD clock cycles (row transfers).
Table 17. IMAGE EXPOSURE AND READOUT
Mode
Single
Dual
NH
NV
1,124
562
Line Timing
Frame Timing
Pixel Timing
2,072
1,036
1,036
L1
L1
L2
F1
F1
F2
P1
P1
P1
Quad
562
Frame Timing
Line Timing
Pixel Timing
Line Timing
Pixel Timing
Repeat NH Times
Repeat NH Times
Repeat NV − NEXP
Times
Repeat NEXP Times
Electronic
Shutter Timing
Figure 40. The Image Readout Timing Flow Chart
www.onsemi.com
35
KAE−02150
Long Integrations and Readout
output SUBV will be invalid. For cameras with long
integration times, the value of SUBV will have to digitized
by and ADC and stored at the time when VDD23 is +15 V.
The SUB pin voltage would be set by a DAC. The HCCD
and EMCCD may be continue to clock during integration.
If they are stopped during integration then the EMCCD
should be re-started at +7 V to flush out any undesired signal
before increasing the voltage to charge multiplying levels.
The timing flow chart for long integration time is shown
in Figure 41.
For extended integrations the output amplifiers need to be
powered down. When powered up, the output amplifiers
emit near infrared light that is sensed by the photodiodes. It
will begin to be visible in images of 30 second integrations
or longer.
To power down the output amplifiers set VDD1 and VSS1
to 0 V, and VDD23 to +5 V. Do not set VDD23 to 0 V during
the integration of an image. During the time the VDD2
supply is reduced to +5 V the substrate voltage reference
Stop All VCCD Clocks at
the V (−8 V) Level.
LOW
Pulse the Electronic Shutter on VSUB
to Empty All Photodiodes.
Integration Begins on the Falling Edge
of the Electronic Shutter Pulse.
Set VDD23 = +5.0 V
Set VDD1 = 0.0 V
Set VSS1 = 0.0 V
Wait…
Set VDD23 = +15.0 V
Set VDD1 = +5.0 V
Set VSS1 = −8.0 V
Begin Normal Line Timing
Repeat for at Least 2,048 Lines
in Single or Dual Output Mode,
1,024 Lines in Quad Output
Mode.
Readout the Photodiodes
and One Image.
Figure 41. Timing Flow Chart for Long Integration Time
www.onsemi.com
36
KAE−02150
STORAGE AND HANDLING
Table 18. STORAGE CONDITIONS
Description
Storage Temperature
Humidity
Symbol
Minimum
Maximum
Units
°C
Notes
T
ST
−55
5
80
90
1
2
RH
%
1. Long-term storage toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade Mean Time to Failure (MTTF).
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
www.onsemi.com
37
KAE−02150
MECHANICAL INFORMATION
PGA Completed Assembly
Notes:
1. Substrate is a 141-pin ceramic PGA package.
2. Body is black alumina.
3. Pins are Kovar or equivalent, plated with 1.00 microns of gold over 2.00 microns of nickel.
4. Wire is wedge bonded aluminum (1% Si).
5. Ablebond 967−1 epoxy for die attach.
6. No materials to obstruct the clearance through the package holes.
7. Exposed metal is 1.00 micron minimum gold over 2.00 micron minimum nickel.
8. Glass lid is Schott E263Teco, n 1.5231. Thickness 0.76 0.05 mm.
D
9. Recommended mounting screws: 1.6 × 0.35 mm (ISO standard), 0−80 (unified fine thread standard).
Figure 42. Completed Assembly (1/2)
www.onsemi.com
38
KAE−02150
Notes:
1. Die is standard thickness for 150 mm silicon wafer: 0.675 0.020 mm.
2. Singulated die is approximately 12.910 × 8.500 mm, for a 50 micron saw kerf.
3. The optical center of the image area is at the center of the die and the center of the package.
Figure 43. Completed Assembly (2/2)
www.onsemi.com
39
KAE−02150
PGA Clear Cover Glass
Notes:
1. Dust and Scratch: 10 micron maximum (“A” zone)
2. Glass Material: Schott D263T eco
Figure 44. PGA Clear Cover Glass
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
KAE−02150/D
相关型号：
©2020 ICPDF网 联系我们和版权申明