KAI-50140-AXA-JD-AE [ONSEMI]
10440 (H) x 4800 (V) Interline CCD Image Sensor;
| 型号： | KAI-50140-AXA-JD-AE |
| 厂家： | 
ONSEMI |
| 描述： | 10440 (H) x 4800 (V) Interline CCD Image Sensor CD |
| 文件： | 总27页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KAI-50140
10440 (H) x 4800 (V)
Interline CCD Image Sensor
Description
The KAI−50140 image sensor is a 50 megapixel Interline Transfer
CCD in a 2.18 to 1 aspect ratio, making it well suited to inspect
displays commonly found on modern smartphones. Leveraging
a 4.5 mm pixel design that provides a 70% resolution increase
compared to the KAI−29050 and KAI−29052 devices, the KAI−50140
provides excellent image uniformity and broad dynamic range.
A flexible output architecture supports 1, 2, or 4 outputs for full
resolution readout of up to 4 frames per second, and a true electronic
shutter enables image capture without motion artifacts across a broad
range of exposure times.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Typical Value
Interline CCD, Progressive Scan
10560 (H) × 4920 (V)
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
10480 (H) × 4840 (V)
Figure 1. KAI−50140 CCD Image Sensor
10440 (H) × 4800 (V)
4.5 mm (H) × 4.5 mm (V)
Features
Active Image Size
46.98 mm (H) × 21.60 mm (V)
51.71 mm (Diag.)
• True Electronic Shutter with Broad
Exposure Latitude
• Low Noise Architecture
• Excellent Smear Performance
• Monochrome and Bayer Color CFA
Configurations
645 1.3× Optical Format
Aspect Ratio
2.175:1
Number of Outputs
Charge Capacity
Output Sensitivity
1, 2 or 4
13,000 electrons
−
42 mV/e
Quantum Efficiency
Pan (−AXA, −QXA)
R, G, B (−FXA, −QXA)
45%
27%, 34%, 37%
Applications
• Industrial Imaging and Inspection
• Security and Surveillance
Read Noise (f = 40 MHz)
13 electrons rms
Dark Current
Photodiode
VCCD
7 electrons/s
50 electrons/s
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Dynamic Range
60 dB
Charge Transfer Efficiency
Blooming Suppression
Smear
0.999999
> 300 X
−98 dB
Image Lag
< 10 electrons
60 MHz
Maximum Pixel Clock Speed
Maximum Frame Rates
Quad Output
3.9 fps
2.0 fps
1.1 fps
Dual Output
Single Output
Package
72 pin PGA
Cover Glass
AR coated, 2 Sides, Sealed
Clear Glass, Taped
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
March, 2019 − Rev. 0
KAI−50140/D
KAI−50140
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
Description
Marking Code
KAI−50140−AXA−JD−B1
KAI−50140−AXA−JD−B2
KAI−50140−AXA−JD−AE
KAI−50140−AXA−JP−B1
KAI−50140−AXA−JP−B2
KAI−50140−AXA−JP−AE
KAI−50140−FXA−JD−B1
KAI−50140−FXA−JD−B2
KAI−50140−FXA−JD−AE
Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR
coating (both sides), Grade 1
KAI−50140−AXA
Serial Number
Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR
coating (both sides), Grade 2
Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR
coating (both sides), Engineering Grade
Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass
(no coatings), Grade 1
KAI−50140−AXA
Serial Number
Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass
(no coatings), Grade 2
Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass
(no coatings), Engineering Grade
Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover
Glass with AR coating (both sides), Grade 1
KAI−50140−FXA
Serial Number
Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover
Glass with AR coating (both sides), Grade 2
Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover
Glass with AR coating (both sides), Grade 2
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−50140
DEVICE DESCRIPTION
Architecture
RDcd
Rc
RDcd
Rd
VDDc
VOUTc
VDDd
VOUTd
1
11 40
8
12
5220
5220
12
8
40 11
1
FLD
GND
OGc
GND
OGd
H2SLd
40
H2SLc
8
12
V4T
V3T
V2T
V4T
V3T
V2T
V1BT
V1BT
DevID
10440H x 4800V
4.5 mm x 4.5 mm Pixels
ESD
40
8
12
12
8
40
ESD
V1BT
V2B
V3B
V4B
V1BT
V2B
V3B
V4B
12 Inner Buffer
8 Outer Buffer
RDab
Ra
RDab
Rb
40 Dark
FLD
VDDa
VDDb
1
11 40
8
12
5220
5220
12
8
40 11
1
VOUTa
VOUTb
GND
OGa
GND
OGb
H2SLa
H2SLb
Figure 2. Block Diagram
Dark Reference Pixels
sensitive than the inner buffer pixels. The inner buffer pixels
have the same sensitivity as the 10440 by 4800 active pixels.
There are 40 dark reference rows at the top and 40 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 40 dark columns on the left or right side of the
image sensor as a dark reference. Under normal
circumstances use only the center 38 columns of the 40
column dark reference due to potential light leakage.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron*hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photo−site. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non*linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Dummy Pixels
Within each horizontal shift register there are 12 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level. In addition, there is one dummy row of
pixels at the top and bottom of the image.
Active Buffer Pixels
ESD Protection
20 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non*uniformities. The 8 outer buffer pixels are less
Adherence to the power*up and power*down sequence
is critical. Failure to follow the proper power*up and
power*down sequences may cause damage to the sensor.
See Power*Up and Power*Down Sequence section.
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3
KAI−50140
Bayer Color Filter
RDcd
Rc
RDcd
Rd
VDDc
VOUTc
VDDd
VOUTd
1
11 40
8
12
5220
5220
12
8
40 11
1
FLD
GND
OGc
GND
OGd
H2SLd
40
H2SLc
8
12
V4T
V3T
V2T
V4T
V3T
V2T
V1BT
B G
B G
R
R
G
G
V1BT
DevID
10440H x 4800V
4.5 mm x 4.5 mm Pixels
ESD
40
8
12
12
8
40
ESD
V1BT
V2B
V3B
V4B
V1BT
V2B
V3B
V4B
B G
B G
R
G
R
G
12 Inner Buffer
8 Outer Buffer
RDab
Ra
RDab
Rb
40 Dark
FLD
VDDa
VDDb
1
11 40
8
12
5220
5220
12
8
40 11
1
VOUTa
VOUTb
GND
OGa
GND
OGb
H2SLa
H2SLb
Figure 3. Bayer Color Filter Pattern
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4
KAI−50140
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37
72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38
Pixel
(1,1)
4
3
6
5
8
7
10 12 14 16 18 20 22 24 26 28 30 32 34 36
9 11 13 15 17 19 21 23 25 27 29 31 33 35
1
Figure 4. Package Pin Description − Top View
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5
KAI−50140
Table 3. PIN DESCRIPTION
Pin
Name
Description
Pin
72
Name
ESD
V3T
Description
ESD Protection Disable
1
V3B
Vertical CCD Clock, Phase 3, Bottom
71
Vertical CCD Clock, Phase 3, Top
Vertical CCD Clock, Phase 4, Top
3
4
V1BT
V4B
Vertical CCD Clock, Phase 1, Bottom and Top
Vertical CCD Clock, Phase 4, Bottom
70
69
V4T
V1BT
Vertical CCD Clock, Phase 1, Bottom and
Top
5
6
VDDa
V2B
Output Amplifier Supply, Quadrant a
Vertical CCD Clock, Phase 2, Bottom
Ground
68
67
66
65
64
63
62
V2T
VDDc
VOUTc
GND
RDcd
Rc
Vertical CCD Clock, Phase 2, Top
Output Amplifier Supply, Quadrant c
Video Output, Quadrant c
Ground
7
GND
8
VOUTa
Ra
Video Output, Quadrant a
Reset Gate, Quadrant a
9
Reset Drain, Quadrants c and d
Reset Gate, Quadrant c
Output Gate, Quadrant c
10
11
RDab
H2SLa
Reset Drain, Quadrants a and b
Horizontal CCD Clock, Phase 2, Storage, Last
Phase, Quadrant a
OGc
12
13
14
15
16
OGa
H1Ba
H2Ba
H2Sa
H1Sa
Output Gate, Quadrant a
61
60
59
58
57
H2SLc
H2Bc
H1Bc
H1Sc
H2Sc
Horizontal CCD Clock, Phase 2, Storage,
Last Phase, Quadrant c
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant a
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant c
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant a
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant c
Horizontal CCD Clock, Phase 2, Storage,
Quadrant a
Horizontal CCD Clock, Phase 1, Storage,
Quadrant c
Horizontal CCD Clock, Phase 1, Storage,
Quadrant a
Horizontal CCD Clock, Phase 2, Storage,
Quadrant c
17
18
19
20
21
SUB
FDGab
N/C
Substrate
56
55
54
53
52
FDGcd
N/C
Fast Line Dump Gate, Top
No Connect
Fast Line Dump Gate, Bottom
No Connect
FDGcd
SUB
Fast Line Dump Gate, Top
Substrate
FDGab
H2Sb
Fast Line Dump Gate, Bottom
Horizontal CCD Clock, Phase 2, Storage,
Quadrant b
H1Sd
Horizontal CCD Clock, Phase 1, Storage,
Quadrant d
22
23
24
25
26
H1Sb
H1Bb
H2Bb
H2SLb
OGb
Horizontal CCD Clock, Phase 1, Storage,
Quadrant b
51
50
49
48
47
H2Sd
H2Bd
H1Bd
OGd
Horizontal CCD Clock, Phase 2, Storage,
Quadrant d
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant b
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant d
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant b
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant d
Horizontal CCD Clock, Phase 2, Storage, Last
Phase, Quadrant b
Output Gate, Quadrant b
Output Gate, Quadrant b
H2SLd
Horizontal CCD Clock, Phase 2, Storage, Last
Phase, Quadrant d
27
28
29
30
31
32
33
34
35
36
Rb
RDab
GND
VOUTb
VDDb
V2B
Reset Gate, Quadrant b
46
45
44
43
42
41
40
39
38
37
RDcd
Rd
Reset Drain, Quadrants c and d
Reset Gate, Quadrant d
Reset Drain, Quadrants a and b
Ground
VOUTd
GND
V2T
Video Output, Quadrant d
Video Output, Quadrant b
Ground
Output Amplifier Supply, Quadrant b
Vertical CCD Clock, Phase 2, Bottom
Vertical CCD Clock, Phase 1, Bottom and Top
Vertical CCD Clock, Phase 4, Bottom
Vertical CCD Clock, Phase 3, Bottom
ESD Protection Disable
Vertical CCD Clock, Phase 2, Top
Output Amplifier Supply, Quadrant d
Vertical CCD Clock, Phase 4, Top
Vertical CCD Clock, Phase 1, Bottom and Top
Device Identification
VDDd
V4T
V1BT
V4B
V1BT
DevID
V3T
V3B
ESD
Vertical CCD Clock, Phase 3, Top
1. Like named pins are internally connected and should have a common drive signal.
2. N/C pins (19, 55) should be left floating.
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KAI−50140
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Description
Light Source
Operation
Condition
Notes
Continuous Red, Green and Blue LED Illumination
Nominal operating voltages and timing
For monochrome sensor, only green LED used
Table 5. PERFORMANCE PARAMETERS
Performance parameters are by design
Description
Maximum Photo−response Nonlinearity
Horizontal CCD Charge Capacity
Vertical CCD Charge Capacity
Photodiode Charge Capacity
Image Lag
Symbol
NL
Nom.
2
Units
Notes
%
2
−
HNe
VNe
PNe
Lag
40
ke
−
16
ke
−
13
ke
3
−
< 10
> 300X
−98
13
e
Anti−blooming Factor
Xab
Vertical Smear
Smr
dB
7
4
−
Read Noise
n
e−T
e rms
Dynamic Range
DR
60
dB
V
4, 5
Output Amplifier DC Offset
Output Amplifier Bandwidth
Output Amplifier Impedance
Output Amplifier Sensitivity
Vodc
8
f
398
80
MHz
W
6
−3db
Rout
−
DV/DN
QEmax
42
mV/e
Peak Quantum Efficiency
45
%
(KAI*50140*AXA and KAI*50140*QXA Configurations)
Peak Quantum Efficiency
Blue
Green
Red
QEmax
37
34
27
%
(KAI*50140*AXA and KAI*50140*QXA Configurations)
Table 6. PERFORMANCE SPECIFICATIONS
Temperature
Tested At
(5C)
Description
Dark Field Global Non−Uniformity
Bright Field Global Non−Uniformity
Bright Field Global Peak to Peak Non−Uniformity
Maximum Gain Difference Between Outputs
Horizontal CCD Charge Transfer Efficiency
Vertical CCD Charge Transfer Efficiency
Photodiode Dark Current
Symbol
DSNU
BSNU
PRNU
DG
Min.
Nom.
Max.
Units
mVpp
%rms
%pp
%
Notes
−
−
5
5
40
−
−
20, 40
20, 40
20, 40
20, 40
20, 40
20, 40
20, 40
1
1
2
−
−
30
10
−
−
−
0.999999
0.999999
7
HCTE
VCTE
Ipd
0.999995
0.999995
−
−
−
50
200
e/p/s
e/p/s
Vertical CCD Dark Current
Ivd
50
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is 546 mV.
4. At 60 MHz.
5. Uses 20 × LOG (PNe/ n ).
e−T
⋅ C
6. f−
= 1 / (2p ⋅ R
) where C
= 5 pF.
3dB
OUT
LOAD
LOAD
7. Green LED illumination.
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7
KAI−50140
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Measured with AR
coated cover glass
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000 1050 1100
Wavelength (nm)
Figure 5. Monochrome with Microlens Quantum Efficiency
Gen2 Color (Bayer RGB) with Microlens
0.50
Measured with AR
coated cover glass
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000 1050 1100
Wavelength (nm)
Red
Green
Blue
Figure 6. Gen2 Color (Bayer RGB) with Microlens Quantum Efficiency
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8
KAI−50140
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
100
90
80
70
60
50
40
30
20
10
0
−25
−20
−15
−10
−5
0
5
10
15
20
25
Angle (degrees)
Horizontal QE: KAI−43140−AXA
Vertical QE: KAI−43140−AXA
Figure 7. Monochrome with Microlens Angular Quantum Efficiency
Dark Current versus Temperature
10000
1000
100
10
1
0.1
1000/T (K)
2.9
3.0
60
3.1
50
3.2
40
3.3
30
3.4
20
T (°C)
72
Photodiode
VCCD
Figure 8. Dark Current vs. Temperature
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KAI−50140
Power-Estimated
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
10
15
20
25
30
35
40
45
50
55
60
HCCD Frequency (MHz)
Single
Dual (Left/Right)
Quad
Figure 9. Power
Frame Rates
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10
15
20
25
30
35
40
45
50
55
60
HCCD Frequency (MHz)
Single
Dual (Left/Right)
Quad
Figure 10. Frame Rates
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KAI−50140
DEFECT DEFINITIONS
Table 7. OPERATING CONDITIONS
Description
Condition
Notes
Light Source
Continuous Red, Green, Blue, and/or Blue LED Illumination
For the monochrome sensor, only the
green LED is used
Operation
Nominal Operating Voltages and Timing
Table 8. OPERATING PARAMETERS
Description
1 Output
20 MHz
10560
4 Outputs
20 MHz
5280
HCCD Clock Frequency
Pixels Per Line
Lines Per Frame
4920
2460
Line Time
549.6 ms
2704.1 ms
285.6 ms
702.7 ms
Frame Time
Table 9. TIMING MODES
Timing Modes
Conditions
Mode A
Mode B
1 Output, no electronic shutter used. Photodiode integration time is equal to the Frame Time
4 Outputs, no electronic shutter used. Photodiode integration time is equal to the Frame time
Table 10. DEFECT DEFINITIONS
Description
Grade 1 Grade 2 Grade 2
(mono)
(color)
Definition
Column
Defect
A group of more than 10 contiguous pixels along a single column that deviate
from the neighboring columns by:
• more than 97 mV in the dark field using Timing Mode A at 40°C
• more than 97 mV in the dark field using Timing Mode A at 20°C
• more than −12% or +16% in the bright field using Timing Mode A at 20°C or 40°C
0
7
2
Cluster
Defect
A group of 2 to N contiguous defective pixels, but no more than W adjacent defects
horizontally, that deviate from the neighboring pixels by:
• more than 570 mV in the dark field using Timing Mode A at 40°C
• more than 268 mV in the dark field using Timing Mode A at 20°C
• more than −12% or +16% in the bright field using Timing Mode A at 20°C or 40°C
30
W = 4
N−19
70
W = 5
N−38
70
W = 5
N−38
Major Point
Defect
A single defective pixel that deviates from the neighboring pixels by:
• more than 570 mV in the dark field using Timing Mode A at 40°C
• more than 268 mV in the dark field using Timing Mode A at 20°C
• more than −12% or +16% in the bright field using Timing Mode A at 20°C or 40°C
400
800
800
Minor Point
Defect
A single defective pixel that deviates from the neighboring pixels by:
• more than 285 mV in the dark field using Timing Mode A at 40°C
4000
8000
8000
1. Bright field is define as where the average signal level of the sensor is 382 mV, with the substrate voltage set to the recommend VAB setting
such that the capacity of the photodiodes is 546 mV (13,000 electrons).
2. For the color devices (KAI−50140−FXA or KAI−50140−QXA), a bright field defective pixel is with respect to pixels of the same color.
3. Column and cluster defects are separated by no less than two (2) non−defective pixels in any direction (excluding single pixel defects).
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KAI−50140
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps.
VOUTa
VOUTb
40 dark rows
20 buffer rows
1, 1
Pixel
21 ,
21
Pixel
10440 x 4800
Active Pixels
20 buffer rows
40 dark rows
VOUTc
VOUTd
Figure 11. Pixel 1, 1 Location
OPERATION
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded, the
device will be degraded and may be damaged. Operation at
these values will reduce MTTF.
and may allow moisture ingress over time, depending on the
storage environment. As a result, care must be taken to avoid
cooling the device below the dew point inside the package
cavity, since this may result in condensation on the sensor.
For all KAI−50140 configurations, no warranty, expressed
or implied, covers condensation.
The KAI−50140 image sensors have configurations with
epoxy sealed cover glass. The seal formed is non−hermetic,
Table 11. ABSOLUTE MAXIMUM RATINGS
Description
Operating Temperature
Symbol
Top
Minimum
Maximum
+60
Units
°C
Notes
−50
+20
−
1
2
3
Parameter Specification Temperature Range
Output Bias Current, Total for Each Output
TPSR
Iout
+40
°C
−15
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Device degradation is not evaluated outside of these temperature ranges.
2. The device will operate effectively within a specified temperature range. Performance may not be guaranteed per the PERFORMANCE
SPECIFICATION table for temperatures that are different than those specified within. Noise performance may degrade beyond the
specification at die temperatures higher than specified here. Additionally, charge transfer may degrade beyond the specification at
temperatures lower than specified here.
3. Avoid shorting output pins to ground or any low impedance source during operation. Irreparable damage will occur and is not covered by
warranty. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
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KAI−50140
Table 12. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description
Minimum
−0.4
Maximum
+17.5
Units
V
Notes
VDDa, VOUTa
RDa
1
1
−0.4
+15.5
V
V1TB
ESD − 0.4
ESD − 0.4
ESD − 0.4
ESD − 0.4
ESD − 0.4
−10.0
ESD + 24.0
ESD + 14.0
ESD + 15.0
ESD + 14.0
ESD + 20.0
0.0
V
V2B, V2T, V3B, V3T, V3B, V3T
V
FDGab, FDGcd
V
H1a, H2a, H2La
V
1
1
Ra
V
ESD
V
SUB
−0.4
40.0
V
2
1. a refers to a, b, c, or d.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Power-Up and Power-Down Sequence
Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down
sequences may cause damage to the sensor.
Do Not Pulse the Electronic Shutter
until ESD is Stable
V+
VDD
SUB
HCCD
High
Time
VCCD
Low
ESD
V−
Activate All Other Biases when
ESD is Stable and Sub is above 3 V
NOTES:
1. Activate all other biases when ESD is stable and SUB is above 3 V.
2. Do not pulse the electronic shutter until ESD is stable.
3. VDD cannot be +15 V when SUB is 0 V.
4. The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. See Figure 13.
5. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground
will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See Figure 14.
Figure 12. Power-Up and Power-Down Sequence
www.onsemi.com
13
KAI−50140
The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage.
0.0 V
ESD
ESD − 0.4 V
All VCCD and FDG Clocks
absolute maximum overshoot of 0.4 V.
Figure 13. VCCD Clock Overshoots
VDDa
GND
ESD
SUB
Figure 14. External Diode Protection
Table 13. DC BIAS OPERATING CONDITIONS
Max. DC
Current
Description
Reset Drain
Pins
RDa
Symbol
RD
Minimum
+12.3
+2.0
Nominal
+12.5
+2.2
Maximum
+12.7
+2.4
Units
V
Notes
10 mA
10 mA
1
1
Output Gate
OGa
OG
V
Output Amplifier Supply
Ground
VDDa
GND
SUB
VDD
GND
VSUB
ESD
Iout
+14.5
+0.0
+15.0
+0.0
+15.5
+0.0
V
11 mA
−1.0 mA
50 mA
1, 2
V
Substrate
+5.0
VAB
VDD
V
3, 8
6, 7
ESD Protection Disable
Output Bias Current
1. a denotes a, b, c, or d.
ESD
−9.2
−9.0
−8.8
V
50 mA
VOUTa
−3.0
−5.0
−10.0
mA
1, 4, 5
2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 15.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
4. An output load sink must be applied to each VOUT pin to activate each output amplifier.
5. Nominal value required for 60 MHz operation per output. May be reduced for slower data rates and lower noise.
6. Adherence to the power-up and power-down sequence is critical. See Power−Up and Power−Down Sequence section.
7. ESD maximum value must be less than or equal to V1_L − 0.4 V and V2_L − 0.4 V.
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
www.onsemi.com
14
KAI−50140
I
DD
HCCD
Floating
Diffusion
I
OUT
VOUTa
I
SS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 15. Output Amplifier
www.onsemi.com
15
KAI−50140
AC Operating Conditions
Table 14. CLOCK LEVELS
Pins
Capacitance
(Note 1)
(Note 2)
Description
Symbol
V1_L
Level
Low
Mid
Minimum
Nominal
−8.0
0.0
Maximum
−7.8
0.2
Units
Vertical CCD Clock, Phase 1
V1B, V1T
−8.2
−0.2
+10.3
−8.2
−0.2
−8.2
−0.2
−8.2
−0.2
−0.2
+4.8
−0.2
+4.8
−0.2
+4.8
−0.2
+4.8
−0.2
4.8
V
490 nF
V1_M
V1_H
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
+10.5
−8.0
0.0
+10.7
−7.8
+0.2
−7.8
+0.2
−7.8
+0.2
+0.2
+5.2
+0.2
+5.2
+0.2
+5.2
+0.2
+5.2
+0.2
+5.2
+3.2
Vertical CCD Clock, Phase 2
Vertical CCD Clock, Phase 3
Vertical CCD Clock, Phase 4
V2B, V2T
V3B, V3T
V4B, V4T
H1Sa
V2_L
V
V
V
V
V
V
V
V
V
280 nF
300 nF
280 nF
840 pF
880 pF
720 pF
600 pF
20 pF
V2_H
V3_L
−8.0
0.0
V3_H
V4_L
−8.0
0.0
V4_H
Horizontal CCD Clock,
Phase 1 Storage
H1S_L
H1S_H
H1B_L
H1B_H
H2S_L
H2S_H
H2B_L
H2B_H
H2SL_L
H2LS_A
0.0
+5.0
0.0
Horizontal CCD Clock,
Phase 1 Barrier
H1Ba
+5.0
0.0
Horizontal CCD Clock,
Phase 2 Storage
H2Sa
+5.0
0.0
Horizontal CCD Clock,
Phase 2 Barrier
H2Ba
+5.0
0.0
Horizontal CCD Clock,
Last Phase (Note 3)
H2SLa
Ra
+5.0
+.3.0
Reset Gate
R_L
(Note 4)
+2.0
20 pF
R_H
VES
High
High
+6.8
−
+7.0
−
+7.2
+40
−
Electronic Shutter (Note 5, 8)
SUB
V
V
14 nF
VES_
Offset
Offset
VAB+24
VAB+25
Fast Line Dump Gate
FDGab,
FDGcd
FDG_L
FDG_H
Low
−8.2
−8.0
−7.8
V
260 pF
High
+4.5
+5.0
+5.5
1. a denotes a, b, c, or d.
2. Capacitance is total for all like named pins.
3. Use separate clock driver for improved speed performance.
4. Reset low should be set to +2.0 volts for signal levels greater than 26,000 electrons.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
6. Capacitance values are estimated.
7. If the minimum horizontal clock low level is used (–0.2 V), then the maximum horizontal clock amplitude should be used (5 V amplitude) to
create a –2.0 V to 4.8 V clock.
8. Figure 16 shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground.
The VES_Offset is referenced to VSUB.
VES
VES_Offset
VSUB
GND
GND
Figure 16. VSUB and VES Reference
www.onsemi.com
16
KAI−50140
Device Identification
The device identification pin (DevID) may be used to
determine which ON Semiconductor 4.5 micron pixel
interline CCD sensor is being used.
Table 15. DEVICE IDENTIFICATION
Max. DC
Current
Description
Pins
Symbol
Minimum
Nominal
Maximum
Units
Notes
Device Identification
DevID
DevID
4,000
5,000
6,000
W
50 mA
1, 2, 3
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor.
Recommended Circuit
Note that V1 must be a different value than V2.
V1
V2
R_external
DevID
ADC
R_DeviceID
GND
KAI−50140
Figure 17. Device Identification Recommended Circuit
www.onsemi.com
17
KAI−50140
TIMING
Table 16. REQUIREMENTS AND CHARACTERISTICS
Description
Photodiode Transfer
Symbol
Minimum
Nominal
Maximum
Units
ms
ms
ms
ms
ms
%
Notes
T
PD
6
16
−
−
−
−
VCCD Leading Pedestal
VCCD Trailing Pedestal
VCCD Transfer Delay
VCCD Transfer
T
3P
T
3D
16
−
−
T
4
−
−
D
V
T
10
−
−
VCCD Clock Cross-Over
VCCD Rise, Fall Time
FDG Delay
V
VCR
75
−
100
10
−
1
T , T
VR VF
5
−
%
1, 2
T
FDG
5
−
ms
ms
ns
ms
ms
ns
ns
ns
ms
HCCD Delay
T
HS
1
−
−
HCCD Transfer
T
E
16.66
1
−
−
Shutter Transfer
Shutter Delay
T
SUB
−
−
T
HD
1
−
−
Reset Pulse
T
R
2.5
−
−
−
Reset − Video Delay
H2SL − Video Delay
Line Time
T
2.2
3.1
−
−
RV
HV
T
−
−
T
LINE
104.2
192.2
256.4
512.7
945.7
−
Dual/Quad HCCD Readout
Single HCCD Readout
Quad HCCD Readout
Dual HCCD Readout
Single HCCD Readout
−
−
Frame Time
T
−
−
ms
FRAME
−
−
−
−
1. Refer to Figure 22: VCCD Clock Rise Time, Fall Time and Edge Alignment.
2. Relative to the pulse width.
www.onsemi.com
18
KAI−50140
Timing Flow Charts
The timing sequence for the clocked device pins may be represented as one of seven patterns (P1*P7) as shown in the table
below. The patterns are defined in Figure 18 and Figure 19. Contact ON Semiconductor Application Engineering for other
readout modes.
Table 17. TIMING SEQUENCES
Dual Readout
VOUTa, VOUTb
Dual Readout
VOUTa, VOUTc
Single Readout
VOUTa
Device Pin
V1BT
Quad Readout
P1BT
P2T
P3T
P4T
P1BT
P4B
P3B
P2B
P1BT
P2T
P3T
P4T
P1BT
P4B
P3B
P2B
V2T
V3T
V4T
V1BT
P1BT
P2B
P3B
P4B
P5
V2B
V3B
V4B
H1Sa
H1Ba
H2Sa (Note 2)
H2Ba
P6
P7
Ra
H1Sb
P5
P6
P7
P5
P6
P6
P5
H1Bb
H2Sb (Note 2)
H2Bb
Rb
P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3)
H1Sc
P5
P6
P5 (Note 1) or Off (Note 3)
P5
P5 (Note 1) or Off (Note 3)
P6 (Note 1) or Off (Note 3)
H1Bc
H2Sc (Note 2)
H2Bc
P6 (Note 1) or Off (Note 3)
P6
Rc
P7
P5
P7 (Note 1) or Off (Note 3)
P5 (Note 1) or Off (Note 3)
P7
P5
P6
P6
P5
P7 (Note 1) or Off (Note 3)
P5 (Note 1) or Off (Note 3)
H1Sd
H1Bd
H2Sd (Note 2)
H2Bd
P6
P6 (Note 1) or Off (Note 3)
P6 (Note 1) or Off (Note 3)
Rd
P7
P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3)
# Lines/Frame
(Minimum)
2460
4920 2460 4920
# Pixels/Line
(Minimum)
5292
10572
1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should
be a multiple of the frequency used on the a and b register.
2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver.
3. Off = R_H for the Reset Gate and H_H for the Horizontal CCD gates. Note that there may be operating conditions (high temperature and/or
very bright light sources) that will cause blooming from the unused c/d register into the image area.
www.onsemi.com
19
KAI−50140
Photodiode Transfer Timing
A row of charge is transferred to the HCCD on the falling
edge of V1 as indicated in the P1 pattern below. Using this
timing sequence, the leading dummy row or line is
combined with the first dark row in the HCCD. The “Last
Line” is dependent on readout mode – either 5292 or 10572
minimum counts required. It is important to note that, in
general, the rising edge of a vertical clock (patterns P1*P4)
should be coincident or slightly leading a falling edge at the
same time interval. This is particularly true at the point
rd
where P1 returns from the high (3 level) state to the
mid*state when P4 transitions from the low state to the high
state.
Pattern
td
t3p
tpd
t 3d
td
tv
tv
P1BT
tv /2
tv /2
P2T
P3T
P4T
tv /2
tv /2
tv
tv
P1BT
P2B
P3B
P4B
tv /2
tv /2
ths
ths
L2
Last Line
L1 + Dummy Line
P5
P6
P7
Figure 18. Photodiode Transfer Timing
Line and Pixel Timing
Each row of charge is transferred to the output, as
illustrated below, on the falling edge of H2SL (indicated as
P6 pattern). The number of pixels in a row is dependent on
readout mode – either 5292 or 10572 minimum counts
required.
Pattern
tline
P1BT
P2T
P3T
P4T
P1BT
P2B
tv
P3B
tv
P4B
te/2
ths
te/2
ths
P5
P6
te
tr
P7
VOUT
Pixel
1
Pixel
53
Pixel
n
Figure 19. Line and Pixel Timing
www.onsemi.com
20
KAI−50140
Pixel Timing Detail
P5
P6
P7
VOUT
trv
thv
Figure 20. Pixel Timing Detail
Frame/Electronic Shutter Timing
The SUB pin may be optionally clocked to provide
electronic shuttering capability as shown below. The
resulting photodiode integration time is defined from the
falling edge of SUB to the falling edge of V1 (P1 pattern).
tframe
Pattern
P1T/B
thd
tint
tsub
SUB
thd
P6
Figure 21. Electronic Shutter Timing
VCCD Clock Edge Alignment
VVCR
90%
10%
tVF
tVR
tV
tVR
tVF
Figure 22. VCCD Clock Rise Time, Fall Time and Edge Alignment
www.onsemi.com
21
KAI−50140
Line and Pixel Timing − Vertical Binning by 2
tv
tv
tv
P1BT
P2T
P3T
P4T
P1BT
P2B
P3B
P4B
t /2
e
ths
P5
P6
P7
Figure 23. Line and Pixel Timing − Vertical Binning by 2
Fast Line Dump Timing
The FDG pins may be optionally clocked to efficiently
remove unwanted lines in the image resulting for increased
frame rates at the expense of resolution. Below is an example
of a 2 line dump sequence followed by a normal readout line.
tv
tv
tv
tv
tv
P1BT
P2T
P3T
P4T
TFDG
TFDG
FDGcd
P1BT
P2B
P3B
P4B
FDGab
P5
t /2
e
t hs
P6
P7
Figure 24. Fast Line Dump Timing
www.onsemi.com
22
KAI−50140
STORAGE AND HANDLING DETAILS
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com. Please note that CCD products are not
shipped or stored in Moisture Barrier Bags (MBB) and
Moisture Sensitivity Level (MSL) ratings are not specified.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on charge binning, please download the
KAE−08151 Charge Binning Application Note
(AND9569/D) from www.onsemi.com.
www.onsemi.com
23
KAI−50140
MECHANICAL INFORMATION
Cover Glass Transmission
100
90
80
70
60
50
40
30
20
10
0.0
200
300
400
500
600
700
800
900
Wavelength (nm)
MAR
Clear
Figure 29. Cover Glass Transmission
www.onsemi.com
24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
CPGA71, 60.60x45.34
CASE 107FJ
ISSUE O
DATE 25 JUN 2018
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84713G
CPGA71, 60.60x45.34
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
CPGA71, 60.60x45.34
CASE 107FJ
ISSUE O
DATE 25 JUN 2018
4X (C2.50)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84713G
CPGA71, 60.60x45.34
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
www.onsemi.com
2
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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