KLI-2113-AAB-ED-AA [ONSEMI]
线性 CCD 图像传感器;型号: | KLI-2113-AAB-ED-AA |
厂家: | ONSEMI |
描述: | 线性 CCD 图像传感器 CD 传感器 换能器 图像传感器 |
文件: | 总19页 (文件大小:1154K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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KLI-2113
Linear CCD Image Sensor
Description
The KLI−2113 Image Sensor is a high dynamic range, multispectral,
linear CCD image sensor ideally suited for demanding color scanner
applications.
The imager consists of three parallel 2098-element photodiode
arrays − one for each primary color. The KLI−2113 sensor offers high
sensitivity, a high data rate, low noise, and negligible lag. Independent
exposure control for each channel allows color balancing at the front
end. CMOS-compatible 5 V clocks, and single 12 V DC supply are all
that are required to drive the KLI−2113 sensor, simplifying the design
of interface electronics.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Typical Value
3 Channel, RGB Tri-linear CCD
2098 × 3
Pixels Count
Figure 1. KLI−2113 Linear CCD
Image Sensor
Pixel Size
14 mm (H) × 14 mm (V)
14 mm
Pixel Pitch
Inter-Array Spacing
Active Image Size
112 mm (8 Lines Effective)
Features
29.37 mm (H) × 0.24 mm (V)
29.4 mm (Diagonal)
• High Resolution
• Wide Dynamic Range
• High Sensitivity
−
Saturation Signal
Dynamic Range
170,000 e
76 dB
• High Operating Speed
• High Charge Transfer Efficiency
• No Image Lag
Responsivity (Wavelength)
R, G, B (−RAA)
R, G, B (−DAA)*
2
62, 42, 37 V/mJ/cm
2
60, 40, 36 V/mJ/cm
2
Mono (−AAA, −AAB)
66 V/mJ/cm
• Electronic Exposure Control
• Pixel Summing Capability
• Up to 2.0 V Peak-Peak Output
• 5.0 V Clock Inputs
−
Output Sensitivity
Dark Current
11.5 mV/e
0.02 pA/Pixel
Dark Current Doubling Rate
Charge Transfer Efficiency
Photoresponse Non-Uniformity
Lag (First Field)
9°C
0.99999/Transfer
5% Peak-Peak
0.6%
• Two-Phase Register Clocking
• On-Chip Dark Reference
Applications
Maximum Data Rate
Package
20 MHz/Channel
CERDIP (Sidebrazed, CuW)
AR Coated, 2 Sides
• Digitization
• Machine Vision
• Mapping/Aerial
• Photography
Cover Glass
* Configuration KLI-2113-DAA uses Gen1 color filter set and is not recommended
for new designs.
NOTE: Parameters above are specified at T = 25°C and 2 MHz clock rates unless
ORDERING INFORMATION
otherwise noted.
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
November, 2015 − Rev. 5
KLI−2113/D
KLI−2113
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KLI−2113 IMAGE SENSOR
Part Number
Description
Marking Code
KLI−2113−AAA−ER−AA
Monochrome, No Microlens, CERDIP Package (Leadframe),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
KLI−2113 Lot Number
Serial Number
KLI−2113−AAA−ER−AE
KLI−2113−AAB−ED−AA
KLI−2113−AAB−ED−AE
KLI−2113−RAA−ED−AA
KLI−2113−RAA−ED−AE
KLI−2113−DAA−ED−AA*
KLI−2113−DAA−ED−AE*
Monochrome, No Microlens, CERDIP Package (Leadframe),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
Monochrome, No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KLI−2113 Lot Number
Serial Number
Monochrome, No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KLI−2113 Lot Number
Serial Number
Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KLI−2113 Lot Number
Serial Number
Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
Description
KLI−2113−12−5−A−EVK
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KLI−2113
DEVICE DESCRIPTION
LS
LOGn
Photodiode Array
12 Test
2098 Active Pixels
12 Dark
RD
f R
VDD
TG2
IG
ID
2 Blank
4 Blank
FD
CCD Cells
CCD Cells
f2
f1
VIDn
SUB
f2s
SUB
Figure 2. Single Channel Schematic
Exposure Control
Pixel Summing
Exposure control is implemented by selectively clocking
the LOG gates during portions of the scanning line time. By
applying a large enough positive bias to the LOG gate,
the channel potential is increased to a level beyond the
‘pinning level’ of the photodiode. (The ‘pinning’ level is the
maximum channel potential that the photodiode can achieve
and is fixed by the doping levels of the structure.) With TG1
in an ‘off’ state and LOG strongly biased, all of the
photocurrent will be drawn off to the LS drain. Referring to
Figure 9, one notes that the exposure can be controlled by
pulsing the LOG gate to a ‘high’ level while TG1 is turning
‘off’ and then returning the LOG gate to a ‘low’ bias level
The effective resolution of this sensor can be varied by
enabling the pixel summing feature. A separate pin is
provided for the last shift register gate labeled f2s. This
gate, when clocked appropriately, stores the summation of
signal from adjacent pixels. This combined charge packet is
then transferred onto the sense node. As an example,
the sensor can be operated in 2-pixel summing mode
(1,049 pixels), by supplying a f2s clock which is a 75% duty
cycle signal at 1/2 the frequency of the f2 signal, and
modifying the fR clock as depicted in Figure 10.
Applications that require full resolution mode
(2,098 pixels), must tie the f2s pin to the f2 pin. Refer to
Figure 9 and Figure 10 for additional details.
sometime during the line scan. The effective exposure (t
)
EXP
is the net time between the falling edge of the LOG gate and
the falling edge of the TG1 gate (end of the line). Separate
LOG connections for each channel are provided, enabling
on-chip light source and image spectral color balancing. As
a cautionary note, the switching transients of the LOG gates
during line readout may inject an artifact at the sensor
output. Rising edge artifacts can be avoided by switching
LOG during the photodiode-to-CCD transfer period,
preferably, during the TG1 falling edge. Depending on
clocking speeds, the falling edge of the LOG should be
synchronous with the f1/f2 shift register readout clocks.
For very fast applications, the falling edge of the LOG gate
may be limited by on-chip RC delays across the array. In this
case, artifacts may extend across one or more pixels.
Correlated double sampling (CDS) processing of the output
waveform can remove the first order magnitude of such
artifacts. In high dynamic range applications, it may be
advisable to limit the LOG fall times to minimize the current
transients in the device substrate and limit the magnitude of
the artifact to an acceptable level.
Image Acquisition
During the integration period, an image is obtained by
gathering electrons generated by photons incident upon the
photodiodes. The charge collected in the photodiode array
is a linear function of the local exposure. The charge is stored
in the photodiode itself and is isolated from the CCD shift
registers during the integration period by the transfer gates
TG1 and TG2, which are held at barrier potentials. At the
end of the integration period, the CCD register clocking is
stopped with the f1 and f2 gates being held in a ‘high’ and
‘low’ state respectively. Next, the TG gates are turned ‘on’
causing the charge to drain from the photo-diode into the
TG1 storage region. As TG1 is turned back ‘off’, charge is
transferred through TG2 and into the f1 storage region.
The TG2 gate is then turned ‘off’, isolating the shift registers
from the accumulation region once again. Complementary
clocking of the f1 and f2 phases now resumes for readout
of the current line of data while the next line of data is
integrated.
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3
KLI−2113
Charge Transport
Readout of the signal charge is accomplished by
two-phase, complementary clocking of the Phase 1 and
Phase 2 gates (f1 and f2) in the horizontal (output) shift
register. The register architecture has been designed for high
speed clocking with minimal transport and output signal
a parallel format at the falling edge of the f2s clock.
Resettable floating diffusions are used for the charge to
voltage conversion while source followers provide
buffering to external connections. The potential change on
the floating diffusion is dependent on the amount of signal
degradation, while still maintaining low (4.75 V min)
charge and is given by DV = DQ / C , where DV is the
FD FD FD
P−P
clock swings for reduced power dissipation, lower clock
noise and simpler driver design. The data in all registers is
clocked simultaneously toward the output structures.
The signal is then transferred to the output structures in
change in potential on the floating diffusion, DQ is the
amount of charge, and C is the capacitance of the floating
FD
diffusion node. Prior to each pixel output, the floating
diffusion is returned to the RD level by the reset clock, fR.
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4
KLI−2113
Physical Description
Pin Description and Device Orientation
VIDR
1
2
3
28
27
26
VIDG
SUB
VDD
SUB
RD
fR
LOGR
LOGG
SUB
4
5
6
7
25
24
23
22
VIDB
SUB
N/C
LOGB
N/C
8
21
N/C
LS
IG
9
20
19
18
17
16
15
N/C
ID
10
11
12
13
14
TG2
N/C
f2s
f2
TG1
N/C
N/C
f1
Figure 3. KLI−2113 Pinout
Table 4. PACKAGE PIN DESCRIPTION
Pin
1
Name
VIDR
SUB
RD
Description
Red Output Video
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
Description
f1
N/C
Phase1 Shift Register Clock
No Connection
2
Substrate
3
Reset Drain
N/C
No Connection
4
fR
Reset Clock
TG1
ID
Inner Transfer Gate
Input Diode Test Pin
No Connection
5
LOGR
LOGG
SUB
N/C
LS
Red Overflow Gate
Green Overflow Gate
Substrate
6
N/C
7
N/C
No Connection
8
No Connection
LOGB
N/C
Blue Overflow Gate
No Connection
9
Light Shield/Exposure Drain
Input Gate/LOG Test Pin
Outer Transfer Gate
No Connection
10
11
12
13
14
IG
SUB
VIDB
VDD
SUB
VIDG
Substrate
TG2
N/C
f2s
Blue Output Video
Amplifier Supply
Substrate
Phase2 Shift Register Summing Gate Clock
Phase2 Shift Register Clock
f2
Green Output Video
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5
KLI−2113
IMAGING PERFORMANCE
Typical Operational Conditions
Specifications given under nominal operating conditions @25°C ambient, f
=2 MHz and nominal external VIDn load
CLK
resistors unless otherwise specified.
Table 5. SPECIFICATIONS
Verification
Plan
Description
Saturation Output Voltage
Output Sensitivity
Symbol
Min.
−
Nom.
2.0
Max.
−
Units
Notes
1, 7
7
8
V
SAT
V
P−P
Die
−
9
9
9
9
DV /DN
−
11.5
170k
75
−
mV/e
Design
Design
Design
Design
O
e
−
Saturation Signal Charge
Output Buffer Bandwidth
Dynamic Range
N
−
−
e
e,SAT
f
−
−
MHz
@ C
= 10 pF
−3dB
LOAD
DR
−
76
−
dB
3
8
Dark Current
I
−
0.02
0.99999
0.6
−
pA/Pixel
4
Die
DARK
9
9
9
9
9
Charge Transfer Efficiency
Lag
CTE
−
−
−
%
V
5
Design
Design
Design
Design
Design
st
L
−
1
1
Field
7
DC Output Offset
V
6
7
9
ODC
Register Clock Capacitance
Transfer Gate Capacitance
C
−
500
400
−
pF
pF
per Phase
f
C
−
−
TG
KLI−2113−RAA CONFIGURATION GEN2 COLOR
2
9
Responsivity
Red Channel
Green Channel
Blue Channel
R
V/mJ/cm
Design
Design
MAX
−
−
−
62
42
37
−
−
−
9
Peak Responsivity Wavelength
Red Channel
Green Channel
lR
nm
−
−
−
650
540
460
−
−
−
Blue Channel
8
Photoresponse Uniformity
PRNU
−
7
14
%p−p
Die
KLI−2113−DAA CONFIGURATION GEN1 COLOR (Note 10)
2
9
9
Responsivity
Red Channel
Green Channel
Blue Channel
R
V/mJ/cm
Design
Design
MAX
−
−
−
60
40
36
−
−
−
Peak Responsivity Wavelength
Red Channel
Green Channel
lR
nm
−
−
−
650
540
460
−
−
−
Blue Channel
8
Photoresponse Uniformity
PRNU
−
5
10
%p−p
Die
KLI−2113−AAA AND KLI−2113–AAB CONFIGURATION MONOCHROME
2
9
9
Responsivity
Monochrome, All Channels
R
V/mJ/cm
nm
Design
MAX
−
66
−
Peak Responsivity Wavelength
Monochrome, All Channels
lR
Design
−
−
675
5
−
8
Photoresponse Uniformity
PRNU
10
%p−p
Die
1. Defined as the maximum output level achievable before linearity or PRNU performance is degraded.
2. With color filter. Values specified at filter peaks. 50% bandwidth = 30 nm.
3. This device utilizes 2-phase clocking for cancellation of driver displacement currents. Symmetry between f1 and f2 phases must be
maintained to minimize clock noise.
4. Dark current doubles approximately every 9°C.
5. Measured per transfer. For total line h < (0.99999)
4256
= 0.96
6. Low frequency response across array with color filter array.
7. Decreasing external VIDn load resistors to improve signal bandwidth will decrease these parameters.
8. A parameter that is measured on every sensor during production testing.
9. A parameter that is quantified during the design verification activity.
10.Configuration KLI−2113−DAA uses Gen1 color filter set and is not recommended for new designs.
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6
KLI−2113
TYPICAL PERFORMANCE CURVES
(2 MHz Operation, Emitter Follower Buffered, 3/4 VSAT, Dark to Bright Transition)
VIDR Output
(1 V/DIV)
f2 Clock
(2 V/DIV)
Time (200 ns/DIV)
Figure 4. Output Waveforms
70
60
50
40
30
20
10
0
Wavelength (nm)
Figure 5. Typical Responsivity
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7
KLI−2113
DEFECT DEFINITIONS
Table 6. OPERATING CONDITION SPECIFICATIONS
(Test Conditions: T = 25°C, f
= 2 MHz, t
= 1.066 ms)
CLK
INT
Field
Dark
Defect Type
Bright
Threshold
Units
mV
%
Notes
1, 2
Number
8.0
10
0
0
Bright
Bright
Bright/Dark
Exposure Control
1, 3
4.0
mV
1, 4, 5
≤ 16
1. Defective pixels will be separated by at least one non-defective pixel within and across channels.
2. Pixels whose response is greater than the average response by the specified threshold. See Figure 6 below.
3. Pixels whose response is greater or less than the average response by the specified threshold. See Figure 6 below.
4. Pixels whose response deviates from the average pixel response by the specified threshold when operating in exposure control mode. See
Figure 6 below.
5. Defect coordinates are available upon request.
Note 3: Bright
Field Bright Pixel
Note 4: Bright Field
Exposure Control
Average
Pixel
Note 2: Dark
Field Bright
Pixel
Bright Defect
Average
Pixel
Note 5: Bright Field
Field Exposure
Control Dark
Defect
Note 3: Bright
Field Dark Pixel
Exposure
Exposure
Figure 6. Illustration of Defect Classifications
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8
KLI−2113
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Gate Pin Voltage
Symbol
Minimum
Maximum
Unit
V
Notes
1, 2
1, 3
1, 4
5
V
GATE
−0.5
−
16
16
Pin-to-Pin Voltage
V
V
PIN−PIN
Diode Pin Voltage
V
DIODE
−0.5
−
16
V
Output Bias Current
Output Load Capacitance
CCD Clocking Frequency
I
−10
15
mA
pF
MHz
DD
VID,LOAD
C
−
f
C
−
20
6
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to substrate voltage.
2. Includes pins: f1, f2, f2s, TG1, TG2, fR, IG, and LOGn.
3. Voltage difference (either polarity) between any two pins.
4. Includes pins: VIDn, RD, VDD, LS and ID.
5. Care must be taken not to short output pins to ground during operation as this may cause serious damage to the output structures.
6. Charge transfer efficiency will degrade at frequencies higher than the nominal (2 MHz) clocking frequency. VIDn load resistor values may
need to be decreased as well to achieve required output bandwidths.
Device Input ESD Protection Circuit (Schematic)
To Device
I/O Pin
Function
V − 20 V
t
SUB
CAUTION: To allow for maximum performance, this device contains limited I/O protection and may be sensitive to electrostatic induced
damage. Devices should be installed in accordance with strict ESD handling procedures!
Figure 7. ESD Protection Circuit
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9
KLI−2113
DC Bias Operating Conditions
Table 8. DC BIAS OPERATING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
V
Notes
Substrate
V
SUB
−
0
−
Reset Drain Bias
V
11.5
11.5
11.5
−4.0
−
12.0
12.0
12.0
−6.0
12.0
12.0
12.5
12.5
12.5
−8.0
−
V
RD
Output Buffer Supply
V
DD
V
Light Shield/Drain Bias
Output Bias Current/Channel
Test Pin − Input Gate/LOG
Test Pin − Input Diode
V
V
LS
I
mA
V
1
DDn
V
V
IG
−
−
V
ID
1. A current sink must be supplied for each output. Load capacitance should be minimized so as not to limit bandwidth. See Figure 8.Choose
values optimized for specific operating frequency, but R2 should not be less than 75 W.
Typical Output Bias/Buffer Circuit
V
DD
0.1 mF
2N2369
or Similar*
To Device
Output Pin: VIDn
(Minimize Path Length)
Buffered Output
R2 = 120 W*
R1 = 600 W*
Figure 8. Typical Output Bias/Buffer Circuit
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10
KLI−2113
AC Operating Conditions
Table 9. CLOCK LEVELS
Description
Symbol
, V , V
f
Minimum
Nominal
Maximum
Units
Notes
CCD Readout Clocks High
CCD Readout Clocks Low
Transfer Clocks High
Transfer Clocks Low
Reset Clock High
V
4.75
−0.1
4.75
−0.1
4.75
−0.1
4.75
−0.1
5.0
0.0
5.0
0.0
5.0
0.0
5.0
0.0
5.25
0.1
V
V
V
V
V
V
V
V
f
f
1H
2H
2sH
2sL
V
, V , V
f f
2L
f
1L
V
, V
, V
5.25
0.1
TG1H
TG2H
TG2L
V
TG1L
V
f
5.25
0.1
RH
Reset Clock Low
V
f
RL
Exposure Clocks High
Exposure Clocks Low
V
, V
LOG2H
, V
LOG2L
5.25
0.1
1
1
LOG1H
V
LOG1L
1. Tie pin to 0 V for applications where exposure control is not used.
Table 10. AC TIMING LEVELS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
-
CCD Element Duration
Line/Integration Period
PD−CCD Transfer Period
Transfer Gate 1 Clear
Transfer Gate 2 Clear
LOGGate Duration
1e (= 1/f
)
50
0.108
1.0
500
500
1
50
−
−
−
−
−
−
−
−
−
−
−
ns
ms
ms
ns
ns
ms
ms
ns
ns
ns
ns
CLK
1L (= t
)
1.066
INT
t
−
−
PD
t
TG1
TG2
t
−
t
t
−
LOG1
LOG2
LOGGate Clear
1
−
Reset Pulse Duration
Clamp to f2 Delay
t
9
−
RST
t
5
−
1
1
CD
Sample to Reset Edge Delay
CCD Clock Rise Time
t
5
−
SD
t
R
−
30
Typical
1. Recommended delays for Correlated Double Sampling of output.
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KLI−2113
TIMING
Line Timing
4e 12e
4e 12e
2098e
2098e
12e 2e
12e 2e
4e 12e
4e 12e
2098e
2098e
12e 2e
12e 2e
f1
f2
TG1
t
INT
TG2
t
t
LOG1
LOG2
LOGn
t
EXP
Photodiode-to-CCD Transfer Timing
First Dark Reference
Pixel Data Valid
1e
f1
f2
t
TG1
TG2
PD
t
t
TG2
TG1
See Timing Notes
LOGn
Output Timing (Full Resolution Mode)
1e
f2s = f2
V
FEEDTHRU
V
DARK
VIDn
V
SAT
t
RST
t
t
SD
CD
fR
Clamp*
t
CLP
Sample*
t
SPL
* Required for Correlated Double Sampling.
Figure 9. Normal Mode Timing
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KLI−2113
Output Timing (2-Pixel Summing Mode)
1e
f2
f2s
fR
VIDn
V
Pixel N + Pixel (N+1)
Clamp*
Sample*
* Required for Correlated Double Sampling.
Figure 10. Binning Mode Timing
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13
KLI−2113
MECHANICAL INFORMATION
Completed Assembly
Figure 11. Completed Assembly Drawing (1 of 4)
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14
KLI−2113
Figure 12. Completed Assembly Drawing (2 of 4)
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KLI−2113
Figure 13. Completed Assembly Drawing (3 of 4)
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KLI−2113
Figure 14. Completed Assembly Drawing (4 of 4)
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REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
KLI−2113/D
相关型号:
KLI-2113-DAA-ED-AA
Linear CCD Image Sensor Gen1 Color (RGB), No Microlens, CERDIP Package (leadframe), Sealed Clear Cover Glass with AR coating (both sides), Standard Grade, 1-TUBE
ONSEMI
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