LC05732A03RATBG [ONSEMI]
Battery Protection IC, Integrated Power MOSFET, 1-Cell Lithium-Ion Battery;
| 型号： | LC05732A03RATBG |
| 厂家： | 
ONSEMI |
| 描述： | Battery Protection IC, Integrated Power MOSFET, 1-Cell Lithium-Ion Battery 电池 |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC05732ARA
Battery Protection IC,
Integrated Power MOSFET,
1-Cell Lithium-Ion Battery
Overview
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MARKING
The LC05732ARA is a protection IC for 1−cell lithium−ion
batteries with integrated power MOS FET. Also it integrates highly
accurate detection circuits and detection delay circuits to prevent
batteries from over−charging, over−discharging, over−current
discharging and over−current charging.
In addition, main system can execute the power−on reset of itself
by turning off the charge FET and discharge FET of LC05732ARA for
a certain time period, with a reset signal.
DIAGRAM
XXXXX
AYYWW
ECP30, 1.97x4.01
SUFFIX
CASE 971BC
A battery protection system can be made by only LC05732ARA and
few external parts.
A
= Assembly Location
YY = Year
WW = Work Week
Features
• Charge−and−Discharge Power MOSFET are Integrated at T = 25°C,
A
V
CC
= 4.0 V
♦ ON Resistance (Total of Charge and Discharge ) 4.8 mW (typ)
ORDERING INFORMATION
• Highly Accurate Detection Voltage/Current at T = 25°C,
A
†
Device
Package
Shipping
V
CC
= 3.7 V
LC05732A02RATBG
ECP30
(Pb−Free)
5000 / Tape &
Reel
♦ Over−Charge Detection
♦ Over−Discharge Detection
♦ Charge Over−Current Detection
25 mV
50 mV
0.7 A
LC05732A03RATBG
ECP30
(Pb−Free)
5000 / Tape &
Reel
♦ Discharge Over−Current Detection 0.7 A
• Delay Time for Detection and Release (Fixed Internally)
• Discharge/Charge Over−Current Detection is Compensated for
Temperature Dependency of Power FET
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• 0 V Battery Charging: “Inhibit”
• Auto Wake−up Function Battery Charging: “Inhibit”
• Forcible Charge−FET and Discharge−FET OFF Mode
RSTB>VDD*0.9: Charge−FET and Discharge−FET = ON
RSTB<VDD*0.1: Charge−FET and Discharge−FET = OFF
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Smart Phone
• Tablet
• Wearable Device
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
March, 2018 − Rev. 3
LC05732ARA/D
LC05732ARA
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS at T = 25°C (Notes 1, 2, 3, 5)
A
Parameter
Supply voltage
Symbol
VCC
Conditions
Ratings
−0.3 to 12.0
20.0
Unit
V
Between PAC+ and VCC : R1 = 680 W
S1 − S2 voltage
VS1−S2
CS
V
CS terminal Input voltage
RSTB input voltage
Storage temperature
V
CC
−20.0 to V +0.3
V
CC
RSTB
Tstg
−0.3 to 7
V
−55 to +125
−40 to +100
°C
°C
Operating ambient
temperature
Topr
Allowable power dissipation
Junction temperature
Pd
(Note 4)
800
125
mW
T
J
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Absolute maximum ratings represent the values which cannot be exceeded at any given time
2. If you intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used
within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for
confirmation
3. This device is made for power applications.
4. JESD 51−3 (1S)
5. Please execute appropriate test and take safety measures on your board.
PAC+
R1
VCC
VCC
RSTB
RSTB
R3
Controller IC
C1
Battery
S1
S2
CS
R2
PAC-
Figure 1. Example of Application Circuit
Components
Min
330
680
680
0.1m
Recommended Value
Max
1k
Unit
W
Description
R1
R2
R3
C1
680
1k
2k
W
1k
2k
W
1.0m
2.2m
F
*We don’t guarantee the characteristics of the circuit shown above.
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2
LC05732ARA
ELECTRICAL CHARACTERISTICS (Notes 6, 7, 8, 9)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
mV
mV
mV
mV
A
DETECTION VOLTAGE
Over−charge
detection voltage
Vov
R1 = 680 W
R1 = 680 W
R1 = 680 W
TA = 25°C
TA = −30 to 70°C
TA = 25°C
Vov_set −25
Vov_set −30
Vovr_set −40
Vovr_set −70
Vuv_set −50
Vuv_set −80
Vuvr_set −100
Vuvr_set −120
Ioc_set −0.7
Vov_set
Vov_set
Vovr_set
Vovr_set
Vuv_set
Vuv_set
Vuvr_set
Vuvr_set
Ioc_set
Vov_set +25
Vov_set +30
Vovr_set +40
Vovr_set +70
Vuv_set +50
Vuv_set +80
Vuvr_set +100
Vuvr_set +120
Ioc_set +0.7
Over−charge
release voltage
Vovr
Vuv
TA = −30 to 70°C
TA = 25°C
Over−discharge
detection voltage
TA = −30 to 70°C
TA = 25°C
Over−discharge
release voltage
Vuvr
Ioc
R1=680 W
CS =0V
TA = −30 to 70°C
Discharge
over−current
detection current
R2 = 1 kW
R2 = 1 kW
R2 = 1 kW
TA = 25°C
CC
V
= 3.7 V
TA = −30 to 70°C
= 3.7 V
Ioc_set −1.2
Ioc2_set*0.8
Ioc2_set*0.6
Ioch_set −0.7
Ioch_set −1.2
Ioc_set
Ioc2_set
Ioc2_set
Ioch_set
Ioch_set
Ioc_set +1.2
Ioc2_set*1.2
Ioc2_set*1.8
Ioch_set +0.7
Ioch_set +1.2
V
CC
Discharge
Ioc2
Ioch
TA = 25°C
V = 3.7 V
CC
A
A
over−current
detection current2
(Short circuit)
TA = −30 to 70°C
= 3.7 V
V
CC
Charge
over−current
detection current
TA = 25°C
V = 3.7 V
CC
TA = −30 to 90°C
= 3.7 V
V
CC
RESET TERMINAL
High−Level Input
Voltage
VIH
VIL
TA = −30 to 90°C
TA = −30 to 90°C
TA = −30 to 90°C
TA = −30 to 90°C
TA = −30 to 90°C
0.9*V
V
V
CC
Low−Level Input
Voltage
0.1*V
CC
High−Level Input
Leakage Current
IIH
V
= RSTB
= 3.7 V
1
mA
mA
ms
CC
Low−Level Input
Leakage Current
IIL
V
20
10
34
20
48
30
CC
RSTB = 0 V
V = 2.2 to
CC
Reset pulse width
Tw_res
4.3 V
INPUT VOLTAGE
0 V battery
charging inhibition
battery voltage
Vinh
TA = 25°C
0.4
0.9
3
1.4
V
CURRENT CONSUMPTION
Operating current
Shut down current
RESISTANCE
ICC
At normal
state
TA = 25°C
6
mA
mA
V
CC
= 3.7 V
Ishut
At shut down
state
TA = 25°C
= 2.0 V
0.1
V
CC
ON resistance 1 of
integrated power
MOSFET
Ron1
Ron2
Ron3
V
= 3.1 V
TA = 25°C
TA = 25°C
TA = 25°C
4.4
4
5.4
4.9
4.8
6.9
5.8
5.7
mW
mW
mW
CC
I = 2.0 A
V = 3.8 V
CC
ON resistance 2 of
integrated power
MOS FET
I = 2.0 A
= 4.0 V
ON resistance 3 of
integrated power
MOSFET
V
CC
3.9
I = 2.0 A
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3
LC05732ARA
ELECTRICAL CHARACTERISTICS (Notes 6, 7, 8, 9)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
RESISTANCE
ON resistance 4 of
integrated power
MOSFET
Ron4
V
= 4.5V
TA = 25°C
TA = 25°C
3.8
4.7
5.6
mW
CC
I = 2.0 A
Internal resistance
(VCC−CS)
Rcsu
V
=
300
kW
CC
Vuv_set
CS = 0 V
Internal resistance
(VSS−CS)
Rcsd
V
= 3.7 V
TA = 25°C
TA = 25°C
10
kW
CC
CS = 0.1 V
Forward Source to
Source Voltage
Vf(s−s)
V
CC
= 2.0 V
0.67
1.06
V
Is = 0.25 A
DETECTION AND RELEASE DELAY TIME
Over−charge
detection delay
time
Tov
TA = 25°C
0.8
0.6
1
1
1.2
1.5
s
TA = −30 to 70°C
Over−charge
release delay time
Tovr
Tuv
TA = 25°C
TA = −30 to 70°C
TA = 25°C
12.8
9.6
14
16
16
20
19.2
24
ms
ms
Over−discharge
detection delay
time
26
TA = −30 to 70°C
12
20
30
Over−discharge
release delay time
Tuvr
Toc1
TA = 25°C
TA = −30 to 70°C
TA = 25°C
0.9
0.6
9.6
1.1
1.1
12
1.3
1.5
ms
ms
Discharge
over−current
detection delay
time 1
V
CC
V
CC
V
CC
= 3.7 V
= 3.7 V
= 3.7 V
14.4
TA = −30 to 70°C
TA = 25°C
7.2
3.2
2.4
230
12
4
18
4.8
6
Discharge
over−current
release delay time
1
Tocr1
Toc2
ms
TA = −30 to 70°C
TA = 25°C
4
Discharge
300
420
ms
over−current
detection delay
time 2 (Short
circuit)
TA = −30 to 70°C
200
300
450
Charge
Toch
V
CC
= 3.7 V
TA = 25°C
12.8
9.6
16
16
19.2
24
ms
Over−current
detection delay
time
TA = −30 to 90°C
Charge
Over−current
release delay time
Tochr
Tres
V
V
= 3.7 V
= 3.7 V
TA = 25°C
TA = −30 to 90°C
TA = 25°C
3.2
2.4
0.8
0.6
4
4
1
1
4.8
6
ms
s
CC
Reset release time
1.2
1.5
CC
TA = −30 to 70°C
6. This device is made for power applications.
7. Please execute appropriate test and take safety measures on your board.
8. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. The specification in this parameter and all specification at high and low temperature are guaranteed by design.
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4
LC05732ARA
SELECTION GUIDE
Device
Vov (V) Vovr (V) Vuv (V) Vuvr (V) Ioc (A)
Ioch (A) Ioc2 (A) Tuv (ms) Reset Function
LC05732A02RATBG
LC05732A03RATBG
4.475
4.500
4.475
4.300
2.1
2.3
2.1
2.3
7.0
9.0
9.0
6.0
25.0
15.0
20
20
Enable
Disable
1
2
3
4
5
6
7
8
A
B
C
D
S1
S1
S2
S2
S1
S1
S2
S2
S1
S1
S2
S2
S1
S1
S2
S2
S1
S1
S2
S2
S1
S1
NC
VCC
S1
S2
S2
NC
CS
RSTB
TOP VIEW
Figure 2. Pin Functions
Pin No.
Symbol
Pin Function
Description
A1−7
B1−6
S1
Source 1
Negative power input
A8
VCC
S2
VCC terminal
Source 2
C1−6
D1−6
D7
RSTB
Charge and discharge off control terminal
(“L” = Reset )
Connected to VCC with 100 kW
D8
CS
NC
Charger minus voltage input terminal
Non connection
B7,C7
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5
LC05732ARA
VCC
Power
OSC
Control
Level
Shifter
Control Circuit
Rcsu
Rcsd
Discharge
Over− current
Detector
Over−discharge
Detector
1.2V
Short−circuit
Detector
Over− charge
Detector
Charge
Over− current
Detector
OTP
S1
S2
CS
VSS
RSTB
Figure 3. Block Diagram
Figure 4. Pdmax vs TA
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6
LC05732ARA
Figure 5. Thermal Resistance vs Time
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7
LC05732ARA
DESCRIPTION OF OPERATION
1. Normal mode
over−discharging (Tuv), discharging will be shut off,
internal power FETs as DCHG_SW is turned off.
This is the over−discharging mode.
After detecting over−discharging, CS pin will be
pulled up to VCC by an internal resistor Rcsu and
the bias of internal circuits will be shut off.
(Shut−down mode)
♦ LC05732ARA controls charging and discharging by
detecting cell voltage (VCC) and controls S2−S1
current. In case that cell voltage is between
over−discharge detection voltage (Vuv) and
over−charge detection voltage (Vov), and S2−S1
current is between charge over−current detection
current (Ioch) and discharge over−current detection
current (Ioc), internal power MOS FETs as
CHG_SW, DCHG_SW are both turned ON.
This is the normal mode, and it is possible to be
charged and discharged.
In shut−down mode, operating current is suppressed
under 0.1 uA (max).
♦ The recovery from stand−by mode will be made by
internal circuits biased after the connecting charger.
♦ By continuing to be charged, if cell voltage
increases more than over−discharge detection
voltage (Vuvr) over the delay time of
2. Over−charging mode
♦ Internal power MOSFET CHG_SW turns off if cell
voltage becomes greater than or equal to
over−charge detection voltage (Vov) over the delay
time of over−charging (Tov).
over−discharging (Tuvr), internal power MOS FETs
as DCHG_SW is turned on and normal mode will be
resumed.
This is the over−charging detection mode.
♦ The recovery from over−charging will be made after
the following two conditions are satisfied.
1. Charger is removed from IC.
♦ In over−discharge detection mode, charging
over−current detection does not operate.
By continuing to be charged, charging over−current
detection starts to operate after cell voltage goes up
more than over−discharge release voltage (Vuvr).
4. Discharging over−current detection mode 1
♦ Internal power MOS FET as DCHG_SW will be
turned off and discharging current will be shut off if
CS pin voltage becomes greater than or equal to
discharging over−current detection current (Ioc) over
the delay time of discharging over−current (Toc1).
This is the discharging over−current detection mode
1.
2. Cell voltage decreases under over−charge release
voltage (Vovr) over the delay time of over−charging
releasing (Tovr) due to discharging through a load.
Consequently, internal power MOS FET as
CHG_SW will be turned on and normal mode will
be resumed.
♦ In over−charging mode, discharging over−current
detection is made only when CS pin increases more
than discharging over−current detection current
2(Ioc2), because discharge current flows through
parasitic diode of CHG_SW FET.
In discharging over−current detection mode 1, CS
pin will be pulled down to VSS with internal resistor
Rcsd.
If CS pin voltage increases more than discharging
over−current detection current 2 (Ioc2) over the
delay time of discharging over−current 2 (Toc2),
discharging will be shut off, because internal power
FETs as DCHG_SW is turned off. (short−circuit
detection mode)
♦ The recovery from discharging over−current
detection mode will be made after the following two
conditions are satisfied.
1. Load is removed from IC.
2. CS pin voltage becomes less than or equal to
discharging over−current release current (Iocr) over
the delay time of discharging over−current release
(Tocr1) due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as
DCHG_SW will be turned on, and normal mode will
be resumed.
After detecting short−circuit, CS pin will be pulled
down to VSS by internal resistor Rcsd.
♦ The recovery from short circuit detection in
over−charging mode will be made after the
following two conditions are satisfied.
1. Load is removed from IC.
2. CS pin voltage becomes less than or equal to
discharging over−current detection current 2 (Ioc2)
due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as
DCHG_SW will be turned on, and over−charging
detection mode will be resumed.
5. Discharging over−current detection mode 2 (short
circuit detection)
♦ Internal power MOS FET as DCHG_SW will be
turned off and discharging current will be shut off if
CS pin voltage becomes greater than or equal to
discharging over−current detection current2 (Ioc2)
over the delay time of discharging over−current 2
(Toc2).
3. Over−discharging mode without Auto Wake Up
function
♦ If cell voltage drops lower than over−discharge
detection voltage (Vuv) over the delay time of
This is the short circuit detection mode.
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8
LC05732ARA
♦ In short circuit detection mode, CS pin will be
pulled down to VSS by internal resistor Rcsd.
The recovery from short circuit detection mode will
be made after the following two conditions are
satisfied.
*Internal current flows out through CS and S2
terminals.
After charger is removed, it flows through parasitic
diode of CHG_SW FET.
Therefore, CS pin voltage will go up more than
charging over−current release current (Iochr).
So CS pin voltage is not an indispensable condition
for recovery from charging over−current detection.
7. 0 V Battery Protection Function
This function protects the battery when a short circuit
in the battery (0 V battery) is detected, at which point
charging will be prohibited.
When the voltage of a battery is below 1.4 V (max), the
gate of the charging control FET is fixed to the
PAC−Terminal voltage, at which point charging will be
prohibited.
If the voltage of the battery is greater than the 0 V
battery prohibit voltage (Vinh), charging will be
enabled.
a. Load is removed from IC.
b. CS pin voltage becomes less than or equal to
discharging over−current release current (Iocr) over
the delay time of discharging over−current release
(Tocr1) due to CS pin pulled down through Rcsd.
Consequently, internal power MOS FET as
DCHG_SW will be turned on, and normal mode will
be resumed.
6. Charging over−current detection mode
♦ Internal power MOS FET as CHG_SW will be
turned off and charging current will be shut off if CS
pin voltage becomes less than or equal to charging
over−current detection current (Ioch) over the delay
time of charging over−current (Toch).
This is the charging over−current detection mode.
♦ The recoveries from charging over−current detection
mode will be made after the following two
conditions are satisfied.
8. Reset mode
♦ In case of normal mode, internal power MOS FET
as CHG_SW and DCHG_SW will be turned off and
charging and discharging current will be shut off if
RSTB pin voltage becomes less than or equal to
low−level input voltage (VIL) over the delay time of
reset pulse width(Tw_res).
This is the reset mode.
♦ The recovery from reset mode will be made itself
after the reset release time (Tres).
1. Charger is removed from IC and CS pin will
increase by load connection.
2. CS pin voltage becomes greater than or equal to
charging over−current release current (Iochr) over
the delay time of charging over−current release
(Tocrh).
Consequently, internal power MOS FET as
CHG_SW will be turned on, and normal mode will
be resumed.
Consequently, internal power MOS FET as
CHG_SW and DCHG_SW will be turned on, and
normal mode will be resumed.
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9
LC05732ARA
TIMING CHART
Charger
connection
Load
connection
Charger
connection
VCC
Vov
Vovr
Vuv/Vuvr
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Tov
Tovr
Tuv
Figure 6. Over−charge Detection/Release, Over−discharge Detection/Release (Connect Charger)
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LC05732ARA
Charger connection
Load connection
VCC
Vov
Vovr
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Tovr
Tov
Figure 7. Over−charge Detection/Release, Over−discharge Detection/Release (Non−connect Charger)
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LC05732ARA
Load connection
Load connection
VCC
Vov
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Discharge
Current
Ioc
Tocr1
Toc2
Toc1
Tocr1
Figure 8. Discharge Over−Current Detection1, Discharge Over−current Detection2 (Short Circuit)
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LC05732ARA
Charger
connection
Load connection
VCC
Vov
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
CS
VCC
S1
Charge/Discharge
Current
0
Ioch
Toch
Tochr
Figure 9. Charge Over−current Detection
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LC05732ARA
Load connection
Load connection
RSTB
VCC
Vov
Vuv
DCHG_SW (Gate)
VCC
S1
CHG_SW (Gate)
VCC
S2
Discharge
Current
Tw _res
Tres
Figure 10. Reset Function
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LC05732ARA
PACKAGE DIMENSIONS
ECP30, 1.97x4.01
CASE 971BC
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
4. DIMENSION b IS MEASURED AT THE MAXIMUM
BALL DIAMETER PARALLEL TO DATUM C.
E
A
B
ORIENTATION
MARK
MILLIMETERS
D
DIM
A
A1
A2
b
D
E
E2
E3
E4
e
MIN
0.545
0.165
0.380
0.245
MAX
0.625
0.205
0.420
0.285
2X
0.05
0.05
C
C
SUPPORT SI
ENCAPSULATION
1.970 BSC
4.010 BSC
0.860 BSC
0.100 BSC
1.405 BSC
0.400 BSC
2X
TOP VIEW
SIDE VIEW
A2
DETAIL A
A
DETAIL A
0.15
C
0.05
C
SEATING
PLANE
NOTE 3
C
A1
e
E2
E3
E4
e
e
e/2
e
D
C
B
A
30X
b
1
2
3
4
5
6
7
8
0.05
C
C
A B
0.03
IC DIE
IC DIE
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
30X
0.24
0.40
PITCH
0.10
A1
PACKAGE
OUTLINE
0.40
PITCH
0.96
0.505
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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15
LC05732ARA
ON Semiconductor and
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LC05732ARA/D
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