LC75700T [ONSEMI]
Key Scanning IC;
| 型号： | LC75700T |
| 厂家： | 
ONSEMI |
| 描述： | Key Scanning IC 光电二极管 商用集成电路 |
| 文件： | 总17页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC75700T
Key Scanning IC
Overview
The LC75700T is a key scanning LSI that accepts input from up to 30 keys
and can control up to four general purpose output ports. Therefore it can
reduce the number of lines to the front panel in application systems.
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Features
Key input function for up to 30 keys.
General-purpose output ports for up to four pins.
A key scan is performed only when a key is pressed, and thus power
dissipation is reduced.
Serial data I/O supports CCB* format communication with the system
controller.
Switching between the key scan output port and general purpose output
port functions can be controlled by the control data.
The RES pin is provided. This pin disables key scanning, and forces the
general-purpose output ports to the low level.
RC oscillator circuit
TSSOP20 4.4x6.5 / TSSOP20 (225 mil)
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
70 / Fan-Fold
TSSOP20(225mil)
(Pb-Free)
LC75700T-MPB-E
TSSOP20(225mil)
(Pb-Free)
LC75700T-TLM-E
LC75700TS-MPB-E
LC75700TS-TLM-E
2000 / Tape &Reel
70 / Fan-Fold
TSSOP20(225mil)
(Pb-Free)
TSSOP20(225mil)
(Pb-Free)
2000 / Tape &Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
© Semiconductor Components Industries, LLC, 2017
June 2017 - Rev. 1
1
Publication Order Number :
LC75700T/D
LC75700T
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
max
Conditions
Ratings
Unit
V
V
V
–0.3 to +7.0
–0.3 to +7.0
DD
DD
V
1
IN
2
IN
CE, CL, DI, RES
OSC, KI1 to KI5
DO
Input voltage
Output voltage
Output current
V
V
V
–0.3 to V + 0.3
DD
V
1
–0.3 to +7.0
OUT
OUT
V
2
OSC, KS1 to KS6, P1 to P4
KS1 to KS6
–0.3 to V + 0.3
DD
I
I
1
1
5
OUT
OUT
mA
2
P1 to P4
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
150
mW
°C
–40 to +85
–50 to +150
Tstg
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
V
min
2.7
max
5.5
5.5
Supply voltage
V
V
5.0
DD
DD
V
1
IH
2
IH
CE, CL, DI, RES
KI1 to KI5
0.8 V
0.6 V
DD
Input high level voltage
V
V
V
DD
0
DD
DD
Input low level voltage
Recommended external resistance
Recommended external capacitance
Guaranteed oscillator range
Low level clock pulse width
High level clock pulse width
Data setup time
V
CE, CL, DI, RES, KI1 to KI5
0.2 V
V
k
pF
kHz
ns
ns
ns
ns
ns
ns
ns
μs
μs
IL
Rosc
Cosc
fosc
tøL
tøH
tds
OSC
39
1000
38
OSC
OSC
19
76
CL
See figure 1.
See figure 1.
See figure 1.
See figure 1.
See figure 1.
See figure 1.
See figure 1.
160
160
160
160
160
160
160
CL
DI, CL
DI, CL
CE, CL
CE, CL
CE, CL
Data hold time
tdh
CE wait time
tcp
CE setup time
tcs
CE hold time
tch
DO output delay time
DO rise time
tdc
DO R = 4.7 k, C = 10 pF*1 See figure 1.
1.5
1.5
PU
L
tdr
DO R = 4.7 k, C = 10 pF*1 See figure 1.
PU L
Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor R and the load capacitance C .
PU
L
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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2
LC75700T
Electrical Characteristics in the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
VH
Pin Name
Conditions
Unit
min
max
Hysteresis
CE, CL, DI, RES, KI1 to KI5
CE, CL, DI, RES
CE, CL, DI, RES
KI1 to KI5
0.1 V
V
μA
μA
V
DD
Input high level current
Input low level current
Input floating voltage
I
V = 5.5 V
5
IH
I
I
IL
V = 0 V
–5
I
V
0.05 V
DD
IF
V
V
V
V
= 5.0 V
= 3.0 V
50
100
200
250
500
6
DD
Pull-down resistance
R
KI1 to KI5
DO
k
μA
PD
100
DD
Output off leakage current
I
= 5.5 V
OFFH
O
= 3.6 V to 5.5 V
= –500 μA
DD
VDD – 1.0
VDD – 0.5
VDD – 0.4
VDD – 0.2
VDD – 0.1
I
O
V
V
1
2
1
KS1 to KS6
P1 to P4
OH
Output high level voltage
Output low level voltage
V
= 2.7 V to 3.6 V
= –250 μA
V
DD
VDD – 0.8
VDD – 0.9
0.2
I
O
I
O
= –1 mA
OH
V
= 3.6 V to 5.5 V
= 25 μA
DD
0.5
0.4
1.5
1.2
I
O
V
OL
KS1 to KS6
V
= 2.7 V to 3.6 V
= 12.5 μA
DD
0.1
V
I
O
I
O
I
O
V
V
2
3
P1 to P4
DO
= 1 mA
0.9
0.5
OL
= 1 mA
0.1
38
OL
Rosc = 39 k
Cosc = 1000 pF
Oscillator frequency
Current drain
fosc
OSC
30.4
45.6
5
kHz
I
1
V
Key scan standby state
DD
DD
DD
DD
V
= 5.5 V
DD
μA
I
2
V
Output open
200
400
fosc = 38 kHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Pin Assignment
20
1
11
10
LC75700T
Top view
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3
LC75700T
1. When CL is stopped at the low level
V
1
IH
CE
V
IL
tøH
tøL
V
50%
1
IH
CL
DI
V
IL
tch
tcp tcs
V
V
1
IH
IL
tds
tdh
DO
D0
D1
tdc
tdr
2. When CL is stopped at the high level
V
1
IH
CE
V
IL
tøL
tøH
V
50%
1
IH
CL
DI
V
IL
tcp tcs
tch
V
V
1
IH
IL
tds
tdh
DO
D0
D1
tdc
tdr
Figure 1
Page 4
LC75700T
Block Diagram
V
DD
KEY SCAN
V
SS
KEY BUFFER
GENERAL PORT
CONTROL REGISTER
SHIFT REGISTER
CLOCK
GENERATOR
OSC
CCB
INTERFACE
Page 5
LC75700T
Pin Functions
Pin
Pin No.
1 to 5
Function
Active
H
I/O
I
Handling when unused
GND
KI1 to KI5
Key scan inputs. These pins have built-in pull-down resistors.
Key scan outputs. Although normal key scan timing lines require diodes to be
inserted in the timing lines to prevent shorts, since these outputs are unbalanced
CMOS transistor outputs, these outputs will not be damaged by shorting when
these outputs are used to from a key matrix.
KS1 to KS3
6 to 8
—
0
Open
Key scan outputs and general-purpose output ports shared-function pins.
KS4/P4 to KS6/P2
9 to 11 These pins can be set the key scan output ports or the general-purpose output
ports by the control data “KP1 and KP2”.
—
—
—
0
0
Open
Open
VDD
P1
12
The P1 is general-purpose output ports.
Oscillator connection. An oscillator circuit is formed by connecting an external
resistor and capacitor at this pin.
OSC
14
I/O
Reset input. that re-initializes the LSI internal states. This pin must be used.
• When RES is low (VSS
)
— Key scanning disabled: KS1 to KS3 = low (VSS).
— Key scan outputs and general output ports shared-function pins:
KS4/P4 to KS6/P2 = low (VSS).
RES
16
— General-purpose output port: P1 = low (VSS).
— All the key data is reset to low.
L
I
GND
• When RES is high (VDD
)
— The states of the pins as key scan output pins or general-purpose output
ports, must be set with the control data.
— And key scanning is a enabled.
Note that serial data must be transferred when RES is high.
Serial data interface. Connections to the controller. Note that DO, being
an open-drain output, requires a pull-up resistor.
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
CE
CL
18
19
20
17
15
13
H
I
I
▲
GND
DI
—
—
—
—
I
DO
VDD
VSS
O
—
—
Open
—
DO: Output data
Power supply. A voltage of between 2.7 V and 5.5 V must be supplied.
Ground. Must be connected to the system ground.
—
Page 6
LC75700T
Serial Data Input
1. When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
1
1
0
KC1 KC2 KC3 KC4 KC5 KC6
0
0
PC1 PC2 PC3 PC4
0
0
KP1 KP2
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
DO
2. When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
1
1
0
KC1 KC2 KC3 KC4 KC5 KC6
0
0
PC1 PC2 PC3 PC4
0
0
KP1 KP2
B0 B1 B2 B3 A0 A1 A2
CCB address
A3
Control data
DO
• CCB address: 62H
• KC1 to KC6: Key scan output state setting data
• PC1 to PC4: General-purpose output port state setting data
• KP1, KP2: Selection data between the key scan output ports and the general-purpose output ports.
Page 7
LC75700T
Control Data Functions
1.KP1, KP2: Selection data between the key scan output ports and the general-purpose output ports.
These control data bits switch the functions of the KS4/P4 to KS6/P2 output pins between the key scan output port and
the general-purpose output port.
Output pins
Maximum number
of key inputs
Number of general-purpose
output ports (+ P1)
KP1
KP2
KS4/P4 KS5/P3 KS6/P2
0
1
0
1
0
0
1
1
KS4
KS4
KS4
P4
KS5
KS5
P3
KS6
P2
30
25
20
15
0 (+1)
1 (+1)
2 (+1)
3 (+1)
P2
Note: KSn (n = 4 to 6): Key scan output ports
Pn (n = 4 to 2): General-purpose output ports
P3
P2
2.KC1 to KC6: Key scan output state setting data
These control data bits set the states of the key scan output pins KS1 to KS6.
Output pins
KS1
KC1
KS2
KC2
KS3
KC3
KS4
KC4
KS5
KC5
KS6
KC6
Key scan output state setting data
For example, if the KS4/P4 to KS6/P2 output pins are set to function as key scan output ports, when KC1 to KC3 are
set to 1 and KC4 to KC6 are set to 0, in the key scan standby state, the KS1 to KS3 output pins will output the high
level (V ) and the KS4 to KS6 pins will output the low level (V ). Note that key scan output signals are not output
DD
SS
from output pins that are set to the low level.
3.PC1 to PC4: General-purpose output port state setting data
These control data bits set the states of the general-purpose output ports P1 to P4.
Output pins
P1
P2
P3
P4
General-purpose output port state setting data
PC1
PC2
PC3
PC4
For example, if the KS4/P4 to KS6/P2 output pins are set to function as general-purpose output ports, when PC1 and
PC2 are set to 1, and PC3 and PC4 are set to 0, the P1 and P2 output pins will output the high level (V ), and P3 and
DD
P4 will output the low level (V ).
SS
Page 8
LC75700T
Serial Data Output
1. When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
1
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
DO
X
KD1 KD2 KD3
KD26 KD27 KD28 KD29 KD30
X
Output data
X : don’t care
2. When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
1
1
0
B0 B1 B2 B3 A0 A1 A2
CCB address
A3
DO
X
KD1 KD2 KD3 KD4
KD26 KD27 KD28 KD29 KD30
X
X
Output data
X : don’t care
• CCB address: 63H
• KD1 to KD30: Key data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) will be invalid.
Output Data
1.KD1 to KD30: Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 key scan output pins and the KI1 to KI5 key scan
input pins and one of those key is pressed, the key output data corresponding to that key will be set to 1. The table
shows the relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1
KS2
KS3
KS4
KS5
KS6
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
When the KS4/P4 to KS6/P2 output pins are set to function as the general-purpose output ports with the control data
“KP1 and KP2”, and a key matrix of up to 15 keys is formed from the KS1 to KS3 output pins and the KI1 to KI5 input
pins, the KD16 to KD30 key data bits will be set to 0.
Page 9
LC75700T
Key Scan Operation Functions
1.Key scan timing
The key scan period is 288T (s). To reliably determine the on/off state of the keys, this LSI scans the keys twice and
determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO)
615T (s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys
again. Thus this LSI cannot detect a key press shorter than 615T (s).
KS1
KS2
KS3
KS4
KS5
KS6
*2
*2
*2
*2
*2
*2
1
1
*2
*2
*2
*2
*2
*2
2
2
3
3
1
fosc
T=
4
4
5
5
6
6
Key on
576T[s]
*2. Not that the high/low states of these pins are determined by the control data, and that key scan output signals are not output
from pins that are set to low .
2.Key scan operation
•The pins KS1 to KS6 are set to the high or low state by the control data.
•If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC
pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are
recognized by determining whether multiple key data bits are set.
•If a key is pressed for longer than 615T (s) (where T = 1/fosc) this LSI outputs a key data read request (a low level on
DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a
serial data transfer, Do will be set high.
•After the controller reads the key data, the key data read request is cleared (DO is set high) and this LSI performs
another key scan. Also note that DO being an open-drain output, requires a pull-up resistor (between 1 kΩ and 10 kΩ) .
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
615T[s]
CE
DI
Serial data transfer
Serial data transfer Key address (63H) Serial data transfer
Key address
Key address
DO
Key data read
Key data read
Key data read
1
fosc
Key data read request
Key data read request
Key data read request
T=
Page 10
LC75700T
Example: When control data “KP1 and KP2 = 0, KC1 to KC5 = 0, KC6 = 1” are executed.
(i.e.key scanning with only KS6 high.)
[L] KS1
[L] KS2
When any one of these keys is pressed, the
oscillator on the OSC pin is started and the
keys are scanned.
[L] KS3
[L] KS4
[L] KS5
[H] KS6
*3
KI1
KI2
KI3
KI4
KI5
*3. These diodes are required to reliabled recognize multiple key presses of keys on the KS6 line when state with
only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents
in the KS6 key scan output signal keys on the KS1 to KS5 lines are pressed at the same time.
Key input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
DI
1
fosc
Serial data transfer
Serial data transfer
Key address (63H)
Serial data transfer
Key address
T=
DO
Key data read
Key data read
Key data read request
Key data read request
Multiple Key Presses
Although this LSI is capable of key scanning without inserting diodes for dual key presses, triple key presses on the
KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these
cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted
in series with each key.Applications that do not recognize multiple key presses of three or more keys should check the
key data for three or more 1 bits and ignore such data.
Page 11
LC75700T
System Reset
When the power is first applied, the state of function is undefined, so it must be initialized by RES = “L”
1.Reset methods
This LSI stopprts the reset methods described below.
When a system reset is applied, key scanning is disabeled, the key data is reset, and the general-purpose output ports
are set to and held at the low level (V ).
SS
Set RES = “H” after the RES = “L” period. And key scanning become possible by the control data are transferred.
V
min
DD
V
DD
t1
V
1
IH
RES
V
IL
t2
V
CE
IL
Control data transfer
"L"
KS1 to KS3
KS4/P4 to KS6/P2
P1
Output pins
Defined
Undefined
Notes: t1 ≥ 10 µs
t2 ≥ 10 µs
2.Internal block states during the reset period.
• CLOCK GENERATOR
Reset is applied and the basic clock is stopped. (The oscillator on the OSC pin is stopped.)
• KEY SCAN, KEY BUFFER
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
And all the key data is set to Low. Then, when the control data are transferred, the key scanning operation is enabled.
• GENERAL PORT
Reset is applied and the outputs of P1 to P4 are all set to the low level.
• CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
When a reset is applied, The CONTROL REGISTER is forcibly initialized internally. Then, when control data are
transferred, the LSI operates according to the control data.
V
DD
KEY SCAN
V
SS
KEY BUFFER
GENERAL PORT
CONTROL REGISTER
SHIFT REGISTER
CLOCK
GENERATOR
OSC
CCB
INTERFACE
Blocks to which the reset applies.
Page 12
LC75700T
3. Output pin states during a reset
Output pins
KS1 to KS3
KS4/P4 to KS6/P2
P1
State during a reset
L
L
L
DO
H *4
*4. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period even if a
key data read operation is performed.
Sample Application Circuit
OSC
+5 V
V
V
(P1)
(P2)
(P3)
(P4)
DD
P1
(General-purpose output ports)
Used with the backlight
controller or other circuit.
SS
KS6/P2
KS5/P3
KS4/P4
KS3
*7
KS2
KS1
RES *5
CE
Key matrix
(up to 30 keys)
KI5
KI4
KI3
KI2
KI1
From the controller
To the controller
CL
DI
DO
To the controller
power supply
*6
Note:*5.When the power is first applied, it must be initialized by RES = "L".
*6.The DO pin,being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 and 10 kΩ) appropriate
for the capacitance of the external wiring so that signal waveforms are not degraded.
*7.Each of The KS4/P4 to KS6/P2 pins must be set to either the key scan output port or the general-purpose output port.
Page 13
LC75700T
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
CE = "L"
NO
DO = "L"
YES
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
CE
t3
t4
t3
t3
t6
t6
t6
Key
address
DI
t5
t5
t5
Key data read
DO
Key data read request
t7
t7
t7
t7
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
t3: Key scan execution time when the key data agreed for two key scans (615T (s))
t4: Key scan execution time when the key data did not agree for two key scans and
the key scan was executed again. (1230T(s))
t5: Key address (63H) transfer time
t6: Key data read time
1
fosc
T=
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t7 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executed the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7 > t4 + t5 + t6
If a keydata read operation is executed when DO is high, the read key data (KD1 to KD30) will be invalid.
Page 14
LC75700T
2. Interrupt based key data acquisition
(1) Flowchart
CE = "L"
No
DO = "L"
YES
Key data read
processing
Wait time of
at least t8
CE = "L"
NO
DO = "H"
YES
Key OFF
(2) Timing chart
Key on
Key on
Key input
Key scan
t3
t3
t4
t3
CE
t6
t6
t6
t6
Key
address
DI
t5
t5
t5
t5
Key data read
DO
Key data read request
t8
t8
t8
t8
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
t3: Key scan execution time when the key data agreed for two key scans (615T (s))
t4: Key scan execution time when the key data did not agree for two key scans and
the key scan was executed again. (1230T(s))
t5: Key address (63H) transfer time
t6: Key data read time
1
fosc
T=
Page 15
LC75700T
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t8 has
elapsed by checking the DO state when CE is low and reading the key data.
The period t8 in this technique must satisfy the following condition.
t8 > t4
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) will be invalid.
PACKAGE DIMENSIONS
unit : mm
TSSOP20 4.4x6.5 / TSSOP20 (225 mil)
CASE 948AX
ISSUE A
SOLDERING FOOTPRINT*
5.80
(Unit: mm)
1.0
GENERIC
MARKING DIAGRAM*
0.32
XXXXXXXXXX
YMDDD
0.65
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
NOTE: The measurements are not to guarantee but for reference only.
*This information is generic. Please refer to
device data sheet for actual part marking.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
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LC75700T
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