LC75832W-TBM-E [ONSEMI]
Duty Drive General-Purpose LCD Driver;
| 型号： | LC75832W-TBM-E |
| 厂家： | 
ONSEMI |
| 描述： | Duty Drive General-Purpose LCD Driver CD |
| 文件： | 总24页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC75832E, LC75832W
Static Drive, 1/2-Duty Drive
General-Purpose LCD Driver
Overview
The LC75832E and 75832W are static drive or 1/2-duty drive,
microcontroller-controlled general-purpose LCD drivers that can be used
in applications such as frequency display in products with electronic tuning.
In addition to being capable to drive up to 108 segments directly, they can
control up to 4 general-purpose output ports. Since the LC75832E and
LC75832W use separate power supply systems for the LCD drive block
and the logic block, the LCD driver block power-supply voltage can be set
to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block
power-supply voltage.
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PQFP64 14x14 / QIP64E
[LC75832E]
Features
Serial data control of switching between static drive mode and 1/2 duty
drive mode.
Up to 54 segments can be displayed in static drive (1/1 duty) mode and up
to 108 segments can be displayed in 1/2 duty drive mode.
Serial data input supports CCB* format communication with the system
controller.
Serial data control of the power-saving mode based backup function and the
all segments forced off function.
Serial data control of switching between the segment output port and
general-purpose output port functions (up to 4 general-purpose output
ports).
SPQFP64 10x10 / SQFP64
[LC75832W]
Serial data control of the frame frequency of the common and segment
output waveforms.
Either RC oscillator operating or external clock operating mode can be
selected with the serial control data.
High generality, since display data is displayed directly without the
intervention of a decoder circuit.
Independent V
for the LCD driver block
can be set to any voltage in the range of 2.7 to 6.0 volts.)
LCD
(V
LCD
regardless of the logic block supply-voltage.
The INH pin allows the display to be forced to the off state.
Allows compatible operation with the LC75822 (822 mode transfer
function).
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
June 2017 - Rev. 1
1
Publication Order Number :
LC75832E_W/D
LC75832E, LC75832W
Specifications
Absolute Maximum Ratings at Ta = 25C, V
= 0 V
SS
Parameter
Symbol
max
Conditions
Ratings
0.3 to +7.0
Unit
V
Maximum supply voltage
V
V
V
V
V
V
I
V
DD
DD
max
V
LCD
0.3 to +7.0
0.3 to +7.0
LCD
Input voltage
Output voltage
Output current
1
IN
CE, CL, DI,
OSC
INH
V
2
IN
0.3 to V +0.3
DD
1
OSC
0.3 to V +0.3
OUT
OUT
DD
V
2
S1 to S54, COM1, COM2, P1 to P4
S1 to S54
0.3 to V
+0.3
300
3
LCD
1
A
mA
OUT
OUT
OUT
I
I
2
COM1, COM2
3
P1 to P4
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 105C
100
mW
C
40 to +105
55 to +125
Tstg
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = 40 to +105C, V
SS
= 0 V
Ratings
typ
Parameter
Supply voltage
Symbol
Conditions
unit
V
min
2.7
max
6.0
V
V
V
DD
DD
V
V
V
V
V
2.7
DD
6.0
6.0
LCD
LCD
Input high-level voltage
Input low-level voltage
1
IH
CE, CL, DI,
INH
OSC external clock operating mode
CE, CL, DI,
0.8V
0.7V
V
2
IH
V
0.2V
0.3V
DD
0
DD
DD
DD
1
INH
IL
V
2
OSC external clock operating mode
OSC RC oscillator operating mode
0
IL
Recommended external
resistor for RC oscillation
Recommended external
capacitor for RC oscillation
Guaranteed range of RC
oscillation
Rosc
Cosc
fosc
39
1000
38
k
pF
OSC RC oscillator operating mode
OSC RC oscillator operating mode
19
19
30
76
76
70
kHz
kHz
%
External clock operating
frequency
f
OSC external clock operating mode
[Figure 3]
CK
38
External clock duty cycle
D
CK
OSC external clock operating mode
[Figure 3]
50
Data setup time
Data hold time
CE wait time
tds
tdh
tcp
tcs
tch
tH
tL
tr
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure 1] [Figure 2]
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 1] [Figure 2]
[Figure 4] to [Figure 7]
CE setup time
CE hold time
High-level clock pulse width
Low-level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
160
160
Fall time
tf
switching time
tc
, CE
INH
INH
10
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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2
LC75832E, LC75832W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Hysteresis
Symbol
Pin
Conditions
unit
V
min
max
V
0.1V
DD
H
CE, CL, DI,
INH
INH
Input high-level
current
I
I
1
V = 6.0 V
I
5.0
5.0
IH
IH
CE, CL, DI,
OSC
A
A
2
V = V
I DD
external clock operating mode
Input low-level
current
I
I
1
V = 0 V
I
IL
IL
5.0
CE, CL, DI,
OSC
INH
2
V = 0 V
I
5.0
external clock operating mode
Output high-
level voltage
V
V
V
1
2
3
S1 to S54
V
V
V
I
I
I
= 20 A
= 100 A
= 1 mA
OH
OH
OH
LCD
0.9
LCD
0.9
O
O
O
COM1, COM2
P1 to P4
V
V
LCD
0.9
Output low-level
voltage
V
V
V
V
1
S1 to S54
I
I
I
= 20 A
= 100 A
= 1 mA
0.9
0.9
0.9
OL
OL
OL
O
O
O
2
COM1, COM2
P1 to P4
3
Output
middle-level
voltage
COM1, COM2
1/2 bias I = 100 A
MID
O
1/2V
1/2V
LCD
0.9
LCD
+0.9
V
Oscillator
frequency
Current drain
fosc
OSC
RC oscillator operating mode
Rosc = 39kΩ, Cosc = 1000 pF
Power-saving mode
30.4
38
45.6
10
kHz
I
I
1
V
DD
DD
2
DD
V
V
= 6.0 V output open
DD
DD
250
500
15
fosc = 38 kHz
Power-saving mode
I
I
1
2
V
V
LCD
LCD
LCD
LCD
V
= 6.0 V output open
LCD
A
100
200
Static
fosc = 38 kHz
I
3
V
V
= 6.0 V output open
LCD
LCD
LCD
1300
2600
1/2 duty
fosc = 38 kHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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3
LC75832E, LC75832W
1. When CL is stopped at the low level
V
1
IH
CE
V
1
IL
tH
tL
V
1
IH
CL 50%
V
1
IL
tr
tf
tcp tcs
tch
V
1
1
IH
DI
V
IL
tds
tdh
Figure 1
2. When CL is stopped at the high level
V
1
IH
CE
V 1
IL
tL
tH
V
50%
V
1
IH
CL
DI
1
IL
tf
tr
tcp tcs
tch
V
1
IH
V
1
IL
tds
tdh
Figure 2
3. OSC pin clock timing in external clock operating mode
t
H
t
L
CK
1
CK
f
=
[kHz]
CK
t
t
H+t
L
L
CK
CK
CK
V
2
IH
50%
OSC
t
H
V
2
IL
CK
H+t
D
=
100[%]
CK
CK
Figure 3
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4
LC75832E, LC75832W
Package Dimensions
unit : mm
[LC75832E]
PQFP64 14x14 / QIP64E
CASE 122BP
ISSUE A
17.20.2
14.00.1
1
2
0.15
0.8
0.35
0.15
(1.0)
0 to 10
0.10
GENERIC
SOLDERING FOOTPRINT*
MARKING DIAGRAM*
16.30
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.80
0.50
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
LC75832E, LC75832W
Package Dimensions
unit : mm
[LC75832W]
SPQFP64 10x10 / SQFP64
CASE 131AK
ISSUE A
12.00.2
10.00.1
1 2
0.150.05
0.5
0.18
0.10
(1.25)
0 to 10
0.10
SOLDERING FOOTPRINT*
GENERIC MARKING DIAGRAM*
11.40
XXXXXXXX
YDD
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.50
0.28
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
LC75832E, LC75832W
Pin Assignment
48
33
49
32
S49
S50
S51
S52
S53
S54
OSC
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
LC75832E
LC75832W
V
DD
INH
V
LCD
V
SS
CE
CL
DI
COM2
COM1
64
17
1
16
Top view
LC75832E : QIP64E(1414)
LC75832W : SQFP64(1010)
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER & LATCH
INH
CLOCK
GENERATOR
CONTROL
REGISTER
OSC
SHIFT REGISTER
V
DD
CCB INTERFACE
V
LCD
V
SS
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7
LC75832E, LC75832W
Pin Functions
Handling
when
Symbol
Pin No.
1 to 4
Function
Active
-
I/O
O
unused
OPEN
S1/P1 to
S4/P4
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports when so set
up by the control data.
S5 to S54
COM1
5 to 54
64
Common driver outputs. The frame frequency is fo [Hz].
-
-
O
OPEN
COM2
63
OSC
55
Oscillator connection. An oscillator circuit is formed by connecting an external
resistor and capacitor to this pin. This pin can be used as the external clock input
pin if external clock operating mode is selected with the control data.
Serial data transfer inputs. Must be connected to the controller.
CE: Chip enable
I/O
V
DD
CE
CL
DI
60
61
62
H
-
I
I
I
GND
GND
CL: Synchronization clock
DI: Transfer data
57
Display off control input
L
I
INH
• INH = low (V ) ...Display forced off
SS
S1/P1 to S4/P4 = low (V
)
SS
(These pins are forcibly set to the segment output port function
and held at the V
level.)
)
SS
S5 to S54 = low (V
SS
COM1, COM2 = low (V
)
SS
OSC = Z (high impedance)
RC oscillation stopped
Inhibits external clock input.
• INH = high (V )...Display on
DD
RC oscillation enabled (RC oscillator operating mode)
Enables external clock input (external clock operating mode).
However, serial data transfer is possible when the display is forced off.
Logic block power supply. Provide a voltage in the range 2.7 to 6.0 V.
LCD driver block power supply. Provide a voltage in the range 2.7 to 6.0 V.
Ground pin. Must be connected to ground.
V
56
58
59
-
-
-
-
-
-
-
-
-
DD
V
LCD
V
SS
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LC75832E, LC75832W
Serial Data Transfer Formats
(1) Static drive mode
1. When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D50 D51 D52 D53 D54
0
0
0
0
0
0
0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
54 bit
Control data
17 bit
DD
1 bit
2. When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D50 D51 D52 D53 D54
0
0
0
0
0
0
0
P0 P1 P2 DT FC0 FC1 FC2 OC SC BU
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
54 bit
Control data
17 bit
DD
1 bit
Note: DD is the direction data.
• CCB address ....... "A2H"
• D1 to D54 ......... Display data
• P0 to P2 .............. Segment output port/general-purpose output port switching control data
• DT ...................... Static drive or 1/2 duty drive switching control data
• FC0 to FC2 ......... Common/segment output waveform frame frequency control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
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LC75832E, LC75832W
(2) 1/2 duty drive mode
1. When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54
0
0
0
0
0
0
0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
54 bit
Control data
17 bit
DD
1 bit
0
1
0
0
0
1
0
1
D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
54 bit
Fixed data
17 bit
DD
1 bit
2. When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
17 bit
CCB address
8 bit
Display data
54 bit
DD
1 bit
0
1
0
0
0
1
0
1
D55 D56
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
54 bit
Fixed data
17 bit
DD
1 bit
Note: DD is the direction data.
• CCB address ....... "A2H"
• D1 to D108 ......... Display data
• P0 to P2 .............. Segment output port/general-purpose output port switching control data
• DT ...................... Static drive or 1/2 duty drive switching control data
• FC0 to FC2 ......... Common/segment output waveform frame frequency control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
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LC75832E, LC75832W
Serial Data Transfer Formats (When in 822 mode data transfer)
(1) Static drive mode (When in 822 mode data transfer)
1. When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D20 D21 D22 D23 D25 D26 D27 D28 D29 D30 D31 D32
D50 D51 D52 D53 D54 DT
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
DD
Display data
53 bit
1 bit
Control data
2 bit
2. When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D20 D21 D22 D23 D25 D26 D27 D28 D29 D30 D31 D32
D50 D51 D52 D53 D54 DT 0 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
53 bit
DD
1 bit
Control data
2 bit
Note: DD is the direction data.
• CCB address …………….. "A2H"
• D1 to D23, D25 to D54 …. Display data
• DT ……………………….. Static drive or 1/2 duty drive switching control data
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LC75832E, LC75832W
(2) 1/2 duty drive mode (When in 822 mode data transfer)
1. When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51D52 D53D54
0
0
0
DT
B0 B1 B2 B3 A0 A1 A2 A3
DD
CCB address
8 bit
Display data
52 bit
1 bit
Control data
3 bit
0
1
0
0
0
1
0
1
D55 D56
D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98
D100 D101 D102 D103 D104 D105 D106
0
0
0
1
D99
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
52 bit
DD
1 bit
Fixed data
3 bit
2. When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
1
0
1
D1 D2
D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54
0
DT
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
52 bit
DD
1 bit
Control data
3 bit
0
1
0
0
0
1
0
1
D55 D56
D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
52 bit
DD
1 bit
Fixed data
3 bit
Note: DD is the direction data.
• CCB address …………….... "A2H"
• D1 to D46, D49 to D106 …. Display data
• DT ……………………….... Static drive or 1/2 duty drive switching control data
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LC75832E, LC75832W
Serial Data Transfer Examples
(1) Static drive mode
The serial data shown in the figure below must be sent.
8 bit
72 bit
0
1
0
0
0
1
0
1
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54
0
0
0
0
0
0
0
P0 P1 P2 DT FC0 FC1 FC2 0C SC BU
0
B0 B1 B2 B3 A0 A1 A2 A3
(2) 1/2 duty drive mode
• When 55 or more segments are used
160 bits of serial data (including CCB address bits) must be sent.
8 bit
72 bit
0
1
0
0
0
1
0
1
D1 D
2
D47 D48 D49 D50 D51 D52 D53 D54
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
0
0 P0 P1 P2 DT FC0 FC1 FC2
0
C SC BU
0
1
B0 B1 B2 B3 A0 A1 A2 A3
0
1
0
0
0
1
0
1
D55 D56
0
0
0
0
0
0
0
0
0
0
0 0 0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 55 segments are used
The serial data shown below (the D1 to D54 display data and the control data) must always be sent.
8 bit
72 bit
0
1
0
0
0
1
0
1
D
1
D
2
D47 D48 D49 D50 D51 D52 D53 D54
0
0
0
0
0
0
0
P0 P1 P2 DT FC0 FC1 FC2
0
C SC BU
0
B0 B1 B2 B3 A0 A1 A2 A3
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LC75832E, LC75832W
Serial Data Transfer Example (When in 822 mode data transfer)
(1) Static drive mode
The serial data shown in the figure below must be sent.
8 bit
56 bit
0
1
0
0
0
1
0
1
D1 D2
D17 D18 D19 D20 D21 D22 D23 D25 D26 D27 D28 D29 D30 D31 D32
D50 D51 D52 D53 D54 DT 0 0
B0 B1 B2 B3 A0 A1 A2 A3
(2) 1/2 duty drive mode
• When 53 or more segments are used
128 bits of serial data (including CCB address bits) must be sent.
56 bit
8 bit
0
1
0
0
0
1
0
1
D
1
D
2
D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54
0
0
DT
0
0 0
B0 B1 B2 B3 A0 A1 A2 A3
0
1
0
0
0
1
0
1
D55 D56
D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106
0 1
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 53 segments are used
The serial data shown in the figure below (the D1 to D46 and D49 to D54 display data, and the control data) must
be sent.
8 bit
56 bit
0
1
0
0
0
1
0
1
D
1
D
2
D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54 0 DT 0 0
B0 B1 B2 B3 A0 A1 A2 A3
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14
LC75832E, LC75832W
Control Data Functions
1. P0 to P2: Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4
output pins.
However, segment output port is forcibly selected when in 822 mode data transfer.
Control data
Output pin state
P0
0
P1
0
P2
0
S1/P1
S1
S2/P2
S3/P3
S3
S4/P4
S4
S2
S2
P2
P2
P2
0
0
1
P1
S3
S4
0
1
0
P1
S3
S4
0
1
1
P1
P3
S4
1
0
0
P1
P3
P4
Note: Sn (n = 1 to 4): Segment output ports
Pn (n = 1 to 4): General-purpose output ports
Note that when the general-purpose output port function is selected, the correspondence between the output pins and
the display data will be that shown in the table.
Corresponding display data
Output pin
Static drive mode
1/2 duty drive mode
S1/P1
S2/P2
S3/P3
S4/P4
D1
D2
D3
D4
D1
D3
D5
D7
For example, if the general-purpose output port function is selected for the S4/P4 output pin in 1/2 duty drive mode,
it will output a high level (V ) when display data D7 is 1, and a low level (V ) when D7 is 0.
LCD
SS
2. DT: Static drive mode/1/2 duty drive mode switching control data
This control data bit selects either static drive mode or 1/2 duty drive mode.
DT
Duty drive mode
Static drive mode
1/2 duty drive mode
Output pin state (COM2)
0
V
level
SS
COM2
1
3. FC0 to FC2: Common/segment output waveform frame frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
However, fo=fosc/384 is forcibly selected when in 822 mode data transfer.
Control data
Frame frequency fo [Hz]
FC0
1
FC1
1
FC2
0
fosc/768, f /768
CK
1
1
1
fosc/576, f /576
CK
0
0
0
fosc/384, f /384
CK
0
0
1
fosc/288, f /288
CK
0
1
0
fosc/192, f /192
CK
4. OC: RC oscillator operating mode/external clock operating mode switching control data.
This control data bit switches the OSC pin function
(either RC oscillator operating mode or external clock operating mode).
However RC oscillator operating mode is forcibly selected when in 822 mode data transfer.
OC
OSC pin function
0
RC oscillator operating mode
External clock operating mode
1
Note: An external resistor, Rosc, and an external capacitor, Cosc, must be connected to the OSC pin if RC oscillator
operating mode is selected.
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15
LC75832E, LC75832W
5. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
However, the segment on state is forcibly selected when in 822 mode data transfer.
SC
Display state
0
On
Off
1
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
6. BU: Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
However, the normal mode is forcibly selected when in 822 mode data transfer.
BU
Mode
0
Normal mode
Power-saving mode.
In RC oscillator operating mode (OC = 0), the OSC pin oscillator is stopped, and in external clock operating mode
(OC = 1), acceptance of the external clock is stopped. In this mode the common and segment output pins go to the
1
V
levels. However, S1/P1 to S4/P4 output pins that are set to be general-purpose output ports by the control data
SS
P0 to P2 can be used as general-purpose output ports.
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16
LC75832E, LC75832W
Display Data and Output Pin Correspondence
(1) Static drive mode
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
Output pin
COM1
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
Output pin
COM1
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D1
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
D2
D3
D4
D5
S6
D6
S7
D7
S8
D8
S9
D9
S10
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
Note 1: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports.
Note 2: The S24 output pin outputs a low level (V level) when in 822 mode data transfer.
SS
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D21
0
1
The LCD segment corresponding to COM1 is off
The LCD segment corresponding to COM1 is on
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17
LC75832E, LC75832W
(2)1/2 duty drive mode
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
COM2
D2
Output pin
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
COM1
D41
D43
D45
D47
D49
D51
D53
D55
D57
D59
D61
D63
D65
D67
D69
D71
D73
D75
D77
D79
COM2
D42
D44
D46
D48
D50
D52
D54
D56
D58
D60
D62
D64
D66
D68
D70
D72
D74
D76
D78
D80
Output pin
S41
COM1
D81
COM2
D82
D1
D3
D4
S42
D83
D84
D5
D6
S43
D85
D86
D7
D8
S44
D87
D88
D9
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
D36
D38
D40
S45
D89
D90
S6
D11
D13
D15
D17
D19
D21
D23
D25
D27
D29
D31
D33
D35
D37
D39
S46
D91
D92
S7
S47
D93
D94
S8
S48
D95
D96
S9
S49
D97
D98
S10
S50
D99
D100
D102
D104
D106
D108
S11
S51
D101
D103
D105
D107
S12
S52
S13
S53
S14
S54
S15
S16
S17
S18
S19
S20
Note 1: Applies when the S1/P1 to S4/P4 output pins are to their segment output function.
Note 2: The S24 output pin outputs a low level (V level) when in 822 mode data transfer.
SS
Note 3: The S54 output pin outputs an all-segment-on waveform when in 822 mode data transfer.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D41
0
D42
0
The LCD segments corresponding to COM1 and COM2 are off
The LCD segment corresponding to COM2 is on
0
1
1
0
The LCD segment corresponding to COM1 is on
1
1
The LCD segments corresponding to COM1 and COM2 are on
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18
LC75832E, LC75832W
Output Waveforms (Static drive mode)
fo[Hz]
V
LCD
COM1
0V
V
LCD
LCD driver output when off
LCD driver output when on
0V
V
LCD
0V
Output Waveforms (1/2 duty, 1/2 bias drive mode)
fo[Hz]
V
LCD
COM1
COM2
1/2V
0V
LCD
V
LCD
1/2V
0V
LCD
V
LCD
LCD driver output when all LCD segments
corresponding to COM1 and COM2 are off.
0V
V
LCD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
V
LCD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
V
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
0V
Control data
Frame frequency fo [Hz]
FC0
1
FC1
1
FC2
0
fosc/768, f /768
CK
1
1
1
fosc/576, f /576
CK
0
0
0
fosc/384, f /384
CK
0
0
1
fosc/288, f /288
CK
0
1
0
fosc/192, f /192
CK
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19
LC75832E, LC75832W
INH
Display Control and the
Pin
Since the IC's internal data (the display data D1 to D54 and the control data when in static drive mode, and the display
data D1 to D108 and the control data when in 1/2 duty drive mode) is undefined when power is first applied,
applications should set the
pin low at the same time as power is applied to turn off the display (setting S1/P1 to
INH
S4/P4 and S5 to S54, COM1, and COM2 to the V level) and during this period send serial data from the controller.
SS
pin high after the data transfer has completed. This procedure prevents
The controller should then set the
INH
unnecessary display at power on (See Figures 4 to 7).
Notes on the Power On/Off Sequences
Applications should observe the following sequence when turning the LC75832E and LC75832W power on and off.
(See Figures 4 to 7):
• At power on: Logic block power supply (V ) on LCD driver block power supply (V
) on
DD LCD
• At power off: LCD driver block power supply (V ) off Logic block power supply (V ) off
LCD DD
However, if the logic and LCD driver block use a shared power supply, then power supplies can be turned on and off at
the same time.
t2
• Static drive mode
t1
t3
V
V
DD
LCD
INH
CE
VIL1
tc
VIL1
Display data and control data transferred
D1 to D54,P0 to P2,
Internal data DT, FC0 to FC2,
OC, SC, BU
Defined
Undefined
Undefined
Notes: t10
t2>0
Figure 4
t30 (t2>t3)
tc 10s min
• Static drive mode (when in 822 mode data transfer)
t2
t1
t3
V
V
DD
LCD
INH
CE
VIL1
tc
VIL1
Display data and control data transferred
D1 to D23,
Internal data D25 to D54,
DT
Undefined
Undefined
Defined
Notes: t10
t2>0
Figure 5
t30 (t2>t3)
tc 10s min
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20
LC75832E, LC75832W
• 1/2 duty drive mode
t2
t1
t3
V
V
DD
LCD
INH
CE
VIL1
tc
VIL1
Display data and control data transferred
D1 to D54, P0 to P2,
Internal data DT, FC0 to FC2,
OC, SC, BU
Undefined
Defined
Undefined
Undefined
Internal data (D55 to D108)
Undefined
Defined
Notes: t10
t2>0
t30 (t2>t3)
tc 10s min
Figure 6
1/2 duty drive mode (when in 822 mode data transfer)
t2
t1
t3
V
V
DD
LCD
INH
CE
VIL1
tc
VIL1
Display data and control data transferred
D1 to D46,
Internal data D49 to D54,
DT
Defined
Undefined
Undefined
Undefined
Internal data (D55 to D106)
Defined
Undefined
Notes: t10
t2>0
t30 (t2>t3)
tc 10s min
Figure 7
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21
LC75832E, LC75832W
Notes on Controller Transfer of Display Data
Since the LC75832E/W transfer the display data (D1 to D108) in two separate transfer operations in 1/2 duty drive
mode, we recommend that applications make a point of completing all of the display data transfer within a period of
less than 30 ms to prevent observable degradation of display quality.
OSC Pin Peripheral Circuit
(1) RC oscillator operating mode (control data OC = 0)
An external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and GND if
RC oscillator operating mode is selected.
OSC
Rosc
Cosc
(2) External clock operating mode (control data OC = 1)
When the external clock operating mode is selected, insert a current protection resistor Rg (4.7 to 47 k) between
the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to
the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
External clock output pin
External oscillator
OSC
Rg
V
DD
Rg
Note: Allowable current value at external clock output pin >
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22
LC75832E, LC75832W
Sample Application Circuit 1
Static drive mode
General-purpose
Output ports
(P1)
(P2)
(P3)
(P4)
Used for functions
such as backlight
control
*3
OSC
*2
+3.3V
+5V
V
V
DD
SS
COM1
P1/S1
P2/S2
P3/S3
P4/S4
S5
V
LCD
INH
CE
CL
DI
S53
S54
From the controller
OPEN
COM2
*2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected
between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor, Rg (4.7
to 47 k), must be inserted between the external clock output pin (on the external oscillator) and the OSC pin.
(See the “OSC Pin Peripheral Circuit” section.)
*3: When a capacitor except the recommended external capacitance (Cosc = 1000 pF) is connected to the OSC pin, it
should be in the range 220 to 2200 pF.
(P1)
(P2)
(P3)
(P4)
General-purpose
Output ports
Sample Application Circuit 2
1/2 duty drive mode
Used for functions
such as backlight
control
*3
OSC
*2
+3.3V
+5V
V
V
COM1
DD
SS
COM2
P1/S1
P2/S2
P3/S3
P4/S4
S5
V
LCD
INH
CE
CL
DI
S52
S53
S54
From the controller
*2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected
between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor, Rg (4.7
to 47 k), must be inserted between the external clock output pin (on the external oscillator) and the OSC pin.
(See the “OSC Pin Peripheral Circuit” section.)
*3: When a capacitor except the recommended external capacitance (Cosc = 1000 pF) is connected to the OSC pin, it
should be in the range 220 to 2200 pF.
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23
LC75832E, LC75832W
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
PQFP64 14x14 / QIP64E
(Pb-Free)
LC75832E-E
300 / Tray Foam
300 / Tray Foam
300 / Tray Foam
800 / Tray JEDEC
1000 / Tape & Reel
800 / Tray JEDEC
800 / Tray JEDEC
1000 / Tape & Reel
PQFP64 14x14 / QIP64E
(Pb-Free)
LC75832EH-E
PQFP64 14x14 / QIP64E
(Pb-Free)
LC75832ES-E
SPQFP64 10x10 / SQFP64
(Pb-Free)
LC75832W-E
SPQFP64 10x10 / SQFP64
(Pb-Free)
LC75832W-TBM-E
LC75832WH-E
LC75832WS-E
LC75832WS-TBM-E
SPQFP64 10x10 / SQFP64
(Pb-Free)
SPQFP64 10x10 / SQFP64
(Pb-Free)
SPQFP64 10x10 / SQFP64
(Pb-Free)
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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