LC823433TA [ONSEMI]
Audio Processing System LSI;
| 型号： | LC823433TA |
| 厂家： | 
ONSEMI |
| 描述： | Audio Processing System LSI |
| 文件： | 总20页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC823433TA
CMOS LSI
Audio Processing System LSI
for MP3 Record and Playback Devices
www.onsemi.com
Overview
LC823433TA is an audio processing system for MP3 record and playback
devices.
It integrates DSP for digital signal processing and analog blocks such as
audio ADC, audio DAC, and speaker and headphone amplifier in addition
to LCD segment driver.
Features
32bit LPDSP32
TQFP128 14x14 / TQFP128L
- SRAM (246KB)
PM 75KB (40KB + 35KB : ISOLATED)
DMA 170KB (16KB + 154KB:ISOLATED)
DMB 1KB (ISOLATED)
ISOLATED area : Power ON/OFF control is available by register.
- ROM (264.5KB)
PM 227.5KB (ISOLATED)
DMA 34KB (ISOLATED)
DMB 3KB (ISOLATED)
ISOLATED area : Power ON/OFF control is available by the register.
- SIO (Clock Serial IO 2ch)
SIO0 : Ch0 eSIO (Clock speed = Sysclk/1 (max))
program load and execute is possible using Serial Flash
(after internal ROM Boot)
SIO1 : Ch1 SIO (Clock speed = Sysclk/8 (max))
- UART (1ch)
- I2C (1ch Single Master, Full/Standard)
- Plain Timer (2ch)
Timer0 : w/ Watch Dog Timer
Timer1 : w/o Watch Dog Timer and XT1 operation
- Multiple Timer (2ch)
PWM output (1ch)
- RTC (Real Time Clock)
Operating voltage is independent of internal core operating voltage.
Only RTC power supply can be active during all others inactive (ISOLATED).
Continued on next page.
* I2C Bus is a trademark of Philips Corporation.
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
May 2015 - Rev. 1
1
Publication Order Number :
LC823433TA/D
LC823433TA
Continued from preceding page.
- SD card IF (2ch) (w/o CPRM)
eSD/eMMC can be connected.
SD ch0 : program load and execute using eSD/eMMC (after internal ROM Boot) is possible.
SD ch1 : SD card
- USB2.0 (480Mbps/12Mbps) Device IF. built-in PHY
- 10bit A/D converter (3ch)
- GPIO (31ch)
(GPIOs share the terminals with other functions. Refer to the terminal list in detail).
LCD controller, LCD Driver. 18SEG * 8COM, 1/8Duty, 1/4Bias
- Internal ROM Boot is possible.
- Firmware writing function.
The firmware reading from SD ch1 and writing to the following devices:
Serial Flash connected SIO0.
eMMC/eSD connected SD ch0.
- JTAG (for debugger)
Audio Functions
- Record and Playback
Compression method : MP31 (MPEG1/2/2.5 Layer3). Stereo/Mono compatible.
Sampling frequences : 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz
Bitrate : 8kbps (*1) to 320kbps (for Decoder-VBR)
(*1) Encoder supports only Mono (one channel) for 8Kbps.
- Adjusting the playback speed
Fast playback : 1.0 times to 2.0 times 10 steps.
Slow playback : 0.5 times to 1.0 times 10 steps.
- Multipurpose filter
- Audio data automatic transfer function
The audio buffer executes the data transfer between internal SRAM (DMA) and the audio block.
Wait cycle(s) is inserted to the LPDSP32 access to the SRAM while the audio buffer accesses to internal
SRAM(DMA).
- Digital volume, digital mute, BEEP, and level meter
The interrupt generation function at the operation completion
(e.g. interrupt at mute completion).
- Audio timer
LR clock count and the interrupt generation function.
- Flexible PCM audio interface (two interfaces)
Master/Slave Mode Selectable
Data Formats : I2S mode etc.
- Sample Rate Converters
0.5times to 64 times conversion range.
- Digital microphone IF (2ch)
Continued on next page.
1 MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license nor imply any right to distribute content created with this product in
revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming
applications (via Internet, intranets and/or networks), other content distribution systems (pay-audio or audio-on-demand
applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives,
memory cards and the like).
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer
Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An
independent license for such use is required. For details, please visit http://mp3licensing.com/.
www.onsemi.com
2
LC823433TA
Continued from preceding page.
Analog function
- Microphone amplifier 0/18/24/30dB (2ch)
- PGA with ALC -12dB to 35.25dB in 0.75dB steps (2ch)
- 16 bit ΔΣADC (2ch)
- Digital filter for 16 bits ΔΣDAC (2ch)
- AB class amplifier
The power supply only to AB class amplifier is possible (ISOLATED).
Thermal shutdown circuit built-in
Speaker amplifier (1ch BTL) 1dB to 4.5dB in 0.5dB steps
Maximum output 300mW @3.0V, Speaker = 8[], 1dB
Headphone amplifier (2ch) 0dB to 3dB in 1dB steps (Only same gain setting to 2ch is possible)
Maximum output 5mW @3.0V, HeadPhone = 16[], Rd (Series) = 33[], 1dB
Clock
- RCOSC : Internal RC oscillation. 1MHz (TYP.)
- XT1 : Main XTAL. 32.768kHz.
Used as an original oscillation of the system clock and the audio clock, and a RTC clock.
- XT2 : Optional XTAL. 12MHz (TYP) etc.
- PLL1 : For system clock generation (LPDSP32 is included).
- PLL2 : For audio clock generation
Specification
Supply voltage : 1.3V (core, etc), 3.15V (Audio, USB, etc)
Maximum operation frequency : 42MHz (DSP@1.3V)
Package : 128pin TQFP
Application
IC Recorder, Audio Player
Radio Recorder, Home Audio (Mini compo)
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LC823433TA
Specifications
Absolute Maximum Ratings at V = 0V
SS
Parameter
Supply voltage
Symbol
Domain of applicability
Ratings
Unit
V
V
V
1
DD
RTC
DD
0.3 to +1.8
AV PLL1
DD
AV PHY1
DD
V
V
2
DD
LCD
DD
AV PLL2
DD
AV ADC
DD
AV AADC
DD
0.3 to +3.96
V
AV ADAC
DD
AV SPAMP
DD
AV PHY2
DD
Input voltage
V
0.3 to *V *+0.3 (Max 3.96)
V
I
DD
Operating temperature
Storage temperature
Topr
Tstg
20 to +75
C
C
55 to +125
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions at Ta = 20C to +75C
Parameter
Supply voltage
Symbol
1
Test Conditions
min
1.15
typ
max
1.65
Unit
V
V
V
1.3
1.5
1.3
DD
RTC
0.9
1.15
2.7
2.7
2.7
2.7
2.7
2.7
1.8
1.35
3.0
0
1.65
1.65
3.3
V
DD
AV PLL1
DD
V
V
V
2
3.15
3.15
3.15
3.15
2.8
V
DD
LCD
3.3
V
DD
AV PLL2
DD
3.3
V
AV ADC
DD
3.3
V
AV AADC
DD
3.3
V
AV ADAC
DD
2.8
3.3
V
AV SPAMP
DD
3.15
1.5
3.8
V
AV PHY1
DD
1.65
3.6
V
AV PHY2
DD
3.15
V
Input voltage
V
*V
*
V
IN
DD
V
3
IN
(RTC)
_ADC
0
0
3.6
3.3
V
V
V
I_AN 300A
IN
(AN0-AN2).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC823433TA
DC Characteristics at Ta = 20C to +75C, V 1 = 1.15V to 1.65V, V 2 = 2.7V to 3.3V,
DD
DD
V
RTC = 0.9V to 1.65V
DD
Parameter
Symbol
Application
3ICUD
Test Conditions
min
typ
max
Unit
V
Input high voltage
V
0.7 V
2
2
IH
DD
3IS, 3ISUD
1IC
Schmitt
0.75 V
V
DD
0.7 V RTC
DD
V
1IS
Schmitt
Schmitt
Schmitt
0.7 V RTC
V
DD
Input low voltage
V
3ICUD
3IS, 3ISUD
1IC
0.3 V
2
2
V
IL
DD
0.25 V
V
DD
0.2 V RTC
DD
V
1IS
0.2 V RTC
V
DD
Input high leakage current
I
3ICUD, 3IS,
3ISUD
V
= V 2
DD
IH
IN
10
10
A
1IC, 1IS
V
V
V
= 3.3V
A
A
A
V
IN
Input low leakage current
Output high voltage
I
3IS, 3ISUD
1IC, 1IS
3T2
= V
SS
10
10
IL
IN
= V RTC
SS
IN
V
OH
I
I
I
= 2mA
= 4mA
= 4mA
V
V
20.4
OH
OH
OH
DD
3T4
20.4
V
DD
3T4(8)
V
20.4
20.4
V
V
DD
DD
(I
= 8mA)
= 6mA
OH
OH
3T6(12)
I
V
(I
I
= 12mA)
OH
Output low voltage
V
OL
3T2
= 2mA
0.4
0.4
V
V
OL
3T4
I
I
= 4mA
OL
OL
3T4(8)
= 4mA
0.4
V
(I
I
= 8mA)
= 6mA
OL
3T6(12)
OL
0.4
0.3
V
V
(I
= 12mA)
= 0.3mA
OL
OL
OD3
I
Output leakage current
I
3T2, 3T4,
3T4(8),
3T6(12)
3ICUD,
3ISUD
When it outputs Hi-Z
OZ
10
10
A
Pull-up resistor
Rup
Rdn
30
30
80
190
190
k
k
Pull-down resistor
3ICUD,
3ISUD
80
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC823433TA
Package Dimensions
unit : mm
TQFP128 14x14 / TQFP128L
CASE 932BA
ISSUE A
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G
= Pb-Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
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LC823433TA
Pin Assignment (Bonding Option)
Direction
Attribute
I
Input pin
3IS
3V Schmitt input
1IS
1IC
1V Schmitt input.
(3V tolerant correspondence)
1V CMOS input
O
B
P
Output pin
3ICUD
3ISUD
3V CMOS input pull-up/down
3V Schmitt input pull-up/down
(3V tolerant correspondence)
1V 0.3mA open drain output
(3V tolerant correspondence)
Bidirectional pin
Power supply pin
OD3
3T2
3T4
3V 2mA tristate output
3V 4mA tristate output
X
Oscillation amplifier
3V analog through
1V analog through
3T4(8)
3T6(12)
Tristate output with 3V 4mA/8mA switch function
3A
1A
Tristate output with 3V 6mA/12mA switch
function
TQFP128L
Pin No.
Name
Direction
Attribute
1
AV SPAMP
SS
P
P
O
I
2
3
AV SPAMP
DD
AVREFSP
HPINL/SPKINM
HPINR
3A
3A
3A
4
5
I
6
AV ADAC
SS
P
O
O
P
P
O
P
I
7
OUTMR
3A
3A
8
OUTML/OUTM
9
AV ADAC
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AV AADC
SS
AVREF
3A
AV AADC
DD
AINL
AINR
3A
3A
I
AV ADC
DD
P
I
AN0
AN1
AN2
3A
3A
3A
I
I
V
P
P
P
SS
V
2
1
DD
V
DD
TIOCA0/P10
B/B
I
3ISUD/3T2
3IS
BMODE0
BMODE1
I
3IS
BMODE2
I
3IS
NRES
I
3IS
SDCLK1/MCLK1/P00
SDCMD1/LRCK1/P02
SDAT10/BCK1/P03
SDAT11/DIN1/P04
SDAT12/DOUT1/P05
SDAT13/SDO1/P06
SDWP1/SDI1/P01
SDCD1/SCK1/P0A
SDCLK0/P14
O/B/B
B/O/B
B/B/B
B/I/B
B/O/B
B/O/B
I/I/B
I/B/B
O/B
P
3ISUD/3T6(12)
3ISUD/3T4(8)
3ISUD/3T4(8)
3ICUD/3T4(8)
3ICUD/3T4(8)
3ICUD/3T4(8)
3ISUD/3T2
3ISUD/3T2
3ICUD/3T6(12)
V
V
2
DD
P
SS
SDCMD0/P15
B/B
3ICUD/3T4(8)
Continued on next page.
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LC823433TA
Continued from preceding page.
TQFP128L
Name
Direction
B/B
Attribute
Pin No.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
SDAT03/P16
3ICUD/3T4(8)
3ICUD/3T4(8)
3ICUD/3T4(8)
3ICUD/3T4(8)
SDAT02/P17/SYSCLK
SDAT01/P18/AUD0CLK
SDAT00/P19/AUD1CLK
B/B/O
B/B/O
B/B/O
P
V
SS
XIN2
I
X
X
XOUT2
O
P
AV PHY1(+V 1)
DD
DD
AV PHY1
SS
P
AV PHY1
SS
P
RREF
B
3A
AV PHY2
SS
P
AV PHY2
DD
P
AV PHY2
DD
P
AV PHY2
SS
P
AV PHY2
SS
P
AV PHY2
SS
P
AV PHY2
DD
P
DP
B
3A
3A
DM
B
AV PHY2
SS
P
AV PHY2
DD
P
COM0
COM1
COM2
COM3
O
O
O
O
P
3A
3A
3A
3A
V
LCD
DD
VLCD1
VLCD2
VLCD3
O
O
O
P
3A
3A
3A
V
SS
V
1
P
DD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
COM4
COM5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
Continued on next page.
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LC823433TA
Continued from preceding page.
TQFP128L
Name
Direction
Attribute
Pin No.
91
92
93
94
95
96
97
98
99
COM6
O
O
3A
COM7
3A
HPDET/SDI1/SCL/P1A
HPMUTE/SDO1/SDA/P1B
JTDO/P1C
I/I/O/B
O/O/B/B
O/B
I/B
3ISUD/3T2
3ISUD/3T2
3ICUD/3T2
3ICUD/3T2
3ICUD/3T2
3ICUD/3T2
JTDI/P1D
JTMS/P1E
I/B
JTCK/P1F
I/B
V
V
1
2
P
DD
100
P
DD
SFMODE
I
3IS
(Internal Signal)
101
102
103
104
105
106
107
108
109
V
P
SS
TXD/SCL/P12
RXD/SDA/P13
SCK0/P07
O/O/B
I/B/B
B/B
3ISUD/3T2
3ISUD/3T2
3ISUD/3T4
3ISUD/3T4
3ISUD/3T2
3ISUD/3T2
3ISUD/3T2
3ISUD/3T2
SDO0/P08
O/B
SDI0/P09
I/B
MCLK0/DMCKO/SCK1/P0B
DIN0/DMDIN/P0F
DOUT0/P0E/NCS
B/O/B/B
I/I/B
O/B/O
110
111
KEYINT1
KEYINT0
I
I
1IS
1IS
112
113
114
115
116
117
RTCRSTB
PWRON
LINEFIXB
XOUT32K
XIN32K
I
1IC
OD3
1IS
X
O
I
O
I
X
V
RTC
P
DD
RTCMODE
I
1IS
(Internal Signal)
118
119
120
121
122
123
124
125
126
127
128
V
RTC
P
P
O
P
P
O
P
O
O
O
O
SS
AV PLL1
DD
VCNT1
1A
3A
V
SS
AV PLL2
DD
VCNT2
AV PLL2
SS
HPOUTR
HPOUTL
SPOUTP
SPOUTN
3A
3A
3A
3A
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LC823433TA
Block Diagram
JTAG
RCOSC
OSCCON
(System)
System Clock
XT1
XT2
ON Semiconductor
32bit DSP
Peripheral0 Clock
Peripheral1 Clock
Peripheral2 Clock
IRQ 15ch
PLL1
LPDSP32
DMA
DMB
DMIO
PRG
System Clock
System Clock
FUNCCLK0
FUNCCLK1
XT1
XT2
OSCCON
(FUNC)
32
DMB
32
40
SRAM
(1KB)
ROM
(3KB)
OSCCON
(Audio)
Audio Clock0
Audio Clock1
XT1
XT2
64
PM
ISOLATED
BCK0, BCK1
PLL2
XT2
SRAM
(35KB)
+
MCLK0, MCLK1
ISOLATED
DMA
ISOLATED
PCM0 IN
S/P
(40KB)
SRAM
(154KB)
ROM
(227.5KB)
PDM
Dig
MIC
Digital MIC IF
+
ISOLATED
(16KB)
PGA(ALC)
MIC AMP
ROM
(34KB)
16bit
A/D
MIC
MIC
0/18/24/30dB
MIC AMP
-12 to 35.25dB
ISOLATED
FUNCCLK1
PGA(ALC)
16bit
A/D
Plain
Timer0
64
0/18/24/30dB
-12 to 35.25dB
AV AADC
DD
Plain
Timer1
MUX
DF + ALC
Multiple
Timer
1
PWM
eSIO
(SIO0)
SIO
Ch0
S-Flash Boot
etc
PCM0 OUT
P/S
Audio Buffer
16bit D/A
(2ch/BTL)
SIO
Ch1
(Write To,
Read From
DMA)
PWM
eSIO
(SIO1)
“Lch” or “+”
“Rch”
LCD
LPF
LPF
AV ADAC
I2C
DD
ISOLATED
“+”
UART
Speaker
Boot monitor
etc
“-”
1 to 4.5dB
3
“Lch”
“Rch”
10bit
A/D
HeadPhone
GPIO
AV SPAMP
DD
0 to 3dB(Lch, Rch common)
P/S
18seg × 8com or
36seg × 4com(TBD)
LCD
CTL
PCM1 OUT
PCM1 IN
LCD
FUNCCLK1
eMMC/eSD Boot
S/P
Ch0
eSD
eMMC
SD I/F
Logic
Ch1
V
1
2
DD
V
I/O
Firmware DL
etc
DD
10bit A/D
LCDCTL
AV ADC
DD
V
LCD
DD
USB2.0
HS
Device
USB2.0
PHY
PLL1
PLL2
AV PLL1
DD
ISOLATED
AV PLL2
DD
XT2
or
XT2/2
AV PHY2
DD
RTC
V
RTC
AV PHY1
DD
DD
XT1
32.768kHz
Note
- Refer to the pin assignment for port share
- ISOLATED SRAMs and ROMs described in this figure can be power off by a register,
in addition to the tiny SRAMs (not described in this figure) in the SD I/F, USB2.0, SRC, 16bit D/A, DF.
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LC823433TA
Pin Functions
JTAG
Pin name
Pol.
Type
Description
Num.
1
JTDO/
P1C
-/
-
O/
B
JTAG test data output/
General purpose port
JTDI/
P1D
-/
-
I/
JTAG test data input/
B
General purpose port.
The input level of the terminal JTDI is taken by rising edge of the terminal
1
NRES.
The value can be read as a register, and can be used as the operation mode
setting.
JTMS/
P1E
-/
-
I/
JTAG test mode selection/
B
General purpose port
The input level of the terminal JTMS is taken by rising edge of the terminal
1
1
NRES.
The value can be read as a register, and can be used as the operation mode
setting.
JTCK/
P1F
Pos/
-
I/
JTAG test clock/
General purpose port
B
Total
4
RTC
Pin name
XIN32K
Pol.
Pos
-
Type
Description
Num.
I
32.768kHz oscillation amplifier input (XT1)
32.768kHz oscillation amplifier output (XT1)
RTC reset input
1
1
XOUT32K
RTCRSTB
O
I
Neg
1
1
1
(VDET)
Neg
-
I
There is an optional bonding as Power supply watch comparison input.
Main power supply ON/OFF control
PWRON
O
(RTCINT)
LINEFIXB
Neg
Neg
O
I
There is an optional bonding as RTC interrupt output.
RTC isolator cutting and the connection
(BACKUPB)
Neg
-
I
There is an optional bonding as RTC operation mode selection.
RTC block power supply.
V RTC
DD
P
1
1
V RTC
SS
-
P
RTC ground pin.
Total
7
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11
LC823433TA
SIO (synchronous serial) interface Ch0 (eSIO)/Timer PWM output/General purpose port
Pin name
Pol.
Type
Description
Num.
1
SCK0/
P07
Pos/
-
B/
B
Serial I/F Ch0 clock/
General purpose port
(It is possible to use it as an external interrupt input.)
Serial I/F Ch0 data output/
SDO0/
P08
-/
-
O/
B
General purpose port
(It is possible to use it as an external interrupt input).
1
(SDO0(SIO0))
-(-)
O(B)
There is an optional bonding as serial I/F Ch0 data output
(Data I/O 0 when at high speed operating).
Serial I/F Ch0 data input/
SDI0/
P09
-/
-
I/
B
General purpose port
(It is possible to use it as an external interrupt input).
1
1
(SDI0(SIO3))
-(-)
I(B)
There is an optional bonding as serial I/F Ch0 data input
(Data I/O 3 when at high speed operating).
MTM Ch0 A input capture and output capture/
General purpose port
TIOCA0/
P10
-/
-
B/
B
(V
)
-
P
There is an optional bonding as V .
SS
SS
Total
4
2
2
UART (asynchronization serial) interface/I2C interface/General purpose port
Pin name
Pol.
Type
Description
Num.
1
TXD/
SCL/
P12
-/
-/
-
O/
O/
B
UART transmitted serial data output/
I2C clock output (open drain output)/
General purpose port
(It is possible to use it as an external interrupt input).
UART received serial data input/
I2C data (open drain output)/
RXD/
SDA/
P13
-/
-/
-
I/
B/
B
1
General purpose port
(It is possible to use it as an external interrupt input).
Total
Headphone control/SIO (synchronous serial) interface Ch1 (SDI, SDO)/I2C interface/General purpose port
Pin name
Pol.
Type
Description
Num.
HPDET/
SDI1/
SCL/
Pos/
I/
Headphone insertion detection/
Serial I/F Ch1 data input/
I2C clock output (open drain output)/
General purpose port (It is possible to use it as an external interrupt input).
Headphone mute/
-/
I/
1
-/
O/
B
P1A
-
HPMUTE/
SDO1/
SDA/
Pos/
O/
O/
B/
B
-/
-/
-
Serial I/F Ch1 data output/
I2C data (open drain output)/
1
P1B
General purpose port
Total
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12
LC823433TA
PCM interface Ch0/Digital mic interface/
SIO (synchronous serial) interface Ch1 (SCK)/General purpose port/RTC (KeyInt RTC model)
Pin name
Pol.
Type
Description
Num.
1
MCLK0/
DMCKO/
SCK1/
P0B
Pos/
B/
O/
B/
B
PCM Ch0 master clock/
-/
-/
-
Digital mic clock output/
Serial I/F Ch1 clock/
General purpose port
(It is possible to use it as an external interrupt input).
KEY interrupt1
KEYINT1
-
-
I
(Notes: Operate in V RTC and the V RTC power supply).
DD
SS
(NHOLD(SIO1))
O(B)
There is an optional bonding as serial I/F Ch0 hold output
(Data I/O 1 when at high speed operating).
1
(BCK0/
P0C)
-/
-
B/
B
I
There is an optional bonding as PCM Ch0 bit clock/
General purpose port
KEYINT0
-
KEY interrupt0
(Notes: Operate in V RTC and the V RTC power supply).
DD
SS
(NWP(SIO2))
O(B)
There is an optional bonding as serial I/F Ch0 write protect output
(Data I/O 2 when high speed operating).
-
1
(LRCK0/
P0D)
B/
B
There is an optional bonding as PCM Ch0 LR clock/
General purpose port
-/
-
(It is possible to use it as an external interrupt input).
PCM Ch0 data input/
DIN0/
DMDIN/
P0F
-/
-/
-
I/
I/
B
Digital mic data input/
1
1
General purpose port
(It is possible to use it as an external interrupt input).
PCM Ch0 data output/
DOUT0/
P0E/
-/
-/
O/
B/
General purpose port
(It is possible to use it as an external interrupt input)/
CS for serial I/F Ch0 (When it boots from internal ROM and the program
from SerialFlash connected to serial I/F Ch0 is loaded, it is used as CS
control terminal of SerialFlash).
NCS
Neg
O
(NCS)
Total
Neg
O
There is an optional bonding as CS for serial I/F Ch0.
5
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13
LC823433TA
SD interface Ch0/General purpose port
Pin name
Pol.
Type
Description
Num.
1
SDCLK0/
P14
Pos/
O/
B
SD card I/F Ch0 clock output/
General purpose port
-
SDCMD0/
P15
-/
-
B/
B
SD card I/F Ch0 command line/
General purpose port
1
1
SDAT03/
P16
-/
-
B/
B
SD card I/F Ch0 data 3/
General purpose port
SDAT02/
P17/
-/
-/
-
B/
B/
O
SD card I/F Ch0 data 2/
General purpose port/
1
1
1
SYSCLK
SDAT01/
P18/
System Clock output (for evaluation)
SD card I/F Ch0 data 1/
-/
-/
-
B/
B/
O
General purpose port/
AUD0CLK
SDAT00/
P19/
Audio0 Clock output (for evaluation)
SD card I/F Ch0 data 0/
-/
-/
-
B/
B/
O
General purpose port/
AUD1CLK
Audio1 Clock output (for evaluation)
Total
6
SD interface Ch1/PCM interface Ch1/SIO (synchronous serial) interface Ch1/General purpose port
Pin name
Pol.
Type
Description
Num.
1
SDCLK1/
MCLK1/
P00
Pos/
O/
O/
B
SD card I/F Ch1 clock output/
PCM Ch1 master clock/
General purpose port
Pos/
-
SDCMD1/
LRCK1/
P02
-/
-/
-
B/
B/
B
SD card I/F Ch1 command line/
PCM Ch1 LR clock/
1
1
1
1
1
General purpose port
SDAT13/
SDO1/
P06
-/
-/
-
B/
O/
B
SD card I/F Ch1 data 3/
Serial I/F Ch1 data output/
General purpose port
SDAT12/
DOUT1/
P05
-/
-/
-
B/
O/
B
SD card I/F Ch1 data 2/
PCM Ch1 data output/
General purpose port
SDAT11/
DIN1/
-/
-/
-
B/
I/
SD card I/F Ch1 data 1/
PCM Ch1 data input/
P04
B
General purpose port
SDAT10/
BCK1/
P03
-/
-/
-
B/
B/
B
SD card I/F Ch1 data 0/
PCM Ch1 bit clock/
General purpose port
SDWP1/
SDI1/
-/
-/
-
I/
SD card I/F Ch1 write protect/
Serial I/F Ch1 data input/
General purpose port
I/
1
1
P01
B
(It is possible to use it as an external interrupt input).
SD card I/F Ch1 card detect/
Serial I/F Ch1 clock/
SDCD1/
SCK1/
P0A
-/
-/
-
I/
B/
B
General purpose port
(It is possible to use it as an external interrupt input).
Total
8
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14
LC823433TA
Oscillation amplifier and PLL
Pin name
Pol.
Type
I
Description
Num.
XIN2
Pos
Oscillation amplifier input for audio (XT2)
Oscillation amplifier output for audio (XT2)
VCO control for PLL1
1
1
1
1
1
1
1
1
XOUT2
VCNT1
-
-
-
-
-
-
-
O
O
P
AV PLL1
DD
Analog power supply for PLL1
Analog ground for PLL1
AV PLL1
SS
P
VCNT2
O
P
VCO control for PLL2
AV PLL2
DD
Analog power supply for PLL2
Analog ground for PLL2
AV PLL2
SS
P
Total
8
10bitA/D
Pin name
AN[2:0]
Pol.
Type
Description
Num.
-
-
-
I
ADC input
3
1
AV ADC
DD
P
P
Power supply for ADC
V
Ground for ADC. It connects V in LSI (terminal sharing).
SS
SS
1
(AV ADC)
SS
There is an optional bonding as dedicated ground AV ADC .
SS
Total
5
Audio CODEC
Pin name
Pol.
-
Type
I
Description
Num.
1
Analog voice input Lch (stereo)
Analog voice input (monaural).
Analog voice input Rch (stereo)
AINL
AINR
-
-
-
-
I
1
1
1
1
AVREF
O
P
P
Audio ADC reference output
Power supply for audio ADC
Ground for audio ADC
AV AADC
DD
AV AADC
SS
OUTML/
OUTM
-/
-
O/
O
Audio DAC PWM output (Lch for HP)/
Audio DAC PWM output (monaural for speaker)
Audio DAC PWM output (Rch for HP)
1
OUTMR
-
O
1
1
1
AV ADAC
DD
-
-
-
P
P
Power supply for audio DAC
Ground for audio DAC
AV ADAC
SS
HPINL/
SPKINM
HPINR
I/
I
Headphone amplifier input (Lch) /
Speaker amplifier input (monaural)
Headphone amplifier input (Rch)
1
-
-
-
-
-
-
-
-
I
1
1
1
1
1
1
1
1
SPOUTP
SPOUTN
HPOUTL
HPOUTR
AVREFSP
O
O
O
O
O
P
AB class speaker amplifier output (+)
AB class speaker amplifier output (-)
Headphone amplifier output (Lch)
Headphone amplifier output (Rch)
AB class amplifier reference output
Analog power supply for AB class amplifier
Analog ground for AB class amplifier
AV SPAMP
DD
AV SPAMP
SS
P
Total
18
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15
LC823433TA
LCD Driver (4COM/8COM bonding switch)
Pin name
SEG[17:0]
COM[7:4]
Pol.
Type
Description
Num.
18
-
-
O
Segment output for LCD
O
COM [7:4], Common driver output for LCD
(when 8COM is used).
4
(SEG[21:18])
COM[3:0]
VLCD1
-
-
-
O
O
O
There is an optional bonding as segment outputs, SEG[21:18],
for the LCD(when 4COM is used).
Common driver output for LCD.
4
1
•Both 8COM and 4COM ··· COM[3:0].
LCD drive voltage output 1
•When 1/3bias is used ··· 2 * V LCD /3.
DD
•When 1/4bias is used ··· 3 * V LCD /4.
DD
VLCD2
VLCD3
-
-
-
O
O
P
LCD drive voltage output 2
•When 1/3bias is used ··· 1 * V LCD /3.
DD
•When 1/4bias is used ··· 2 * V LCD /4.
DD
1
LCD drive voltage output 3
•When 1/3bias is used ··· 1 * V LCD /3.
DD
•When 1/4bias is used ··· 1 * V LCD /4.
DD
1
1
V
LCD
3V power supply for LCD driver
DD
Total
30
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16
LC823433TA
USB 2.0 HS Device/LCD Driver (bonding switch when 4COM is used)
Pin name
Pol.
Type
Description
Num.
1
DP
-
B
USB D+ (Device)
(SEG32)
DM
-
-
O
B
There is an optional bonding as segment output 32 for LCD.
USB D- (Device)
1
(SEG33)
RREF
-
-
O
B
There is an optional bonding as segment output 33 for LCD.
Reference resistance for USB PHY.
1
1
1
(SEG24)
-
-
O
P
There is an optional bonding as segment output 24 for LCD.
Analog 1.5V power supply for USB PHY.
AV PHY1
DD
It connects V 1 in LSI (terminal sharing).
DD
Analog ground for USB PHY.
AV PHY1
SS
-
P
(SEG22)
-
-
O
P
There is an optional bonding as segment output 22 for LCD.
Analog ground for USB PHY.
AV PHY1
SS
1
1
1
1
1
1
1
1
1
1
(SEG23)
-
-
O
P
There is an optional bonding as segment output 23 for LCD.
Analog 3.3V power supply for USB PHY.
AV PHY2
DD
(SEG26)
-
-
O
P
There is an optional bonding as segment output 26 for LCD.
Analog 3.3V power supply for USB PHY.
AV PHY2
DD
(SEG27)
-
-
O
P
There is an optional bonding as segment output 27 for LCD.
Analog 3.3V power supply for USB PHY.
AV PHY2
DD
(SEG31)
-
-
O
P
There is an optional bonding as segment output 31 for LCD.
Analog 3.3V power supply for USB PHY.
AV PHY2
DD
(SEG35)
-
-
O
P
There is an optional bonding as segment output 35 for LCD.
Analog ground for USB PHY.
AV PHY2
SS
(SEG25)
-
-
O
P
There is an optional bonding as segment output 25 for LCD.
Analog ground for USB PHY.
AV PHY2
SS
(SEG28)
-
-
O
P
There is an optional bonding as segment output 28 for LCD.
Analog ground for USB PHY.
AV PHY2
SS
(SEG29)
-
-
O
P
There is an optional bonding as segment output 29 for LCD.
Analog ground for USB PHY.
AV PHY2
SS
(SEG30)
-
-
O
P
There is an optional bonding as segment output 30 for LCD.
Analog ground for USB PHY.
AV PHY2
SS
(SEG34)
-
O
There is an optional bonding as segment output 34 for LCD.
Total
15
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17
LC823433TA
Power supply etc.
Pin name
Pol.
-
Type
Description
Num.
3
BMODE[2:0]
NRES
I
I
Operation mode selection
Neg
External reset and GPIO•LCD driver output force input
•When it is active (L input), the state of the GPIO•LCD driver is forced, and
LED lighting and the LCD display is controlled until reset depends on LSI.
When Low is input : GPIO = Hiz, LCD = Low Fixed (PIOFIXB).
•The state of JTDI and JTMS of JTAG is taken into the internal register by
rising edge of NRES
1
(for operation mode setting).
V
1
2
-
P
Digital internal power supply
DD
3
3
4
There is one V 1 which is also connected with AV PHY1.
DD
DD
V
V
-
-
P
P
Digital IO power supply
DD
Digital ground
SS
There is one V
SS
which is also connected with AV ADC.
SS
Total
Total
14
128
Notes : Do not open an unused digital input terminal or a digital bidirectional terminal of input state, and set
Pull-up/Pull-down register in ON (only terminals with this function) or connect to digital IO power supply or
digital ground.
Left open AINL, AINR, HPINL/SPKINM, and HPINR terminals if they are not used (do not fix to L or H).
Operational mode
Various boot modes etc. can be selected by switching BMODE[2:0] terminal.
BMODE2
BMODE1
BMODE0
Operational mode
0
0
0
0
0
0
1
1
0
1
0
1
Internal ROM boot (eMMC Physical Boot - SD interface Ch0)
Internal ROM boot (IPL Boot - SD interface Ch0)
Internal ROM boot (Partition Boot - SD interface Ch0)
Internal ROM boot
(External Serial Flash Boot - SIO (synchronous serial) interface Ch0)
Liberation of the terminal for SD interface Ch0 and SIO Ch0
(SDCLK0, SDCMD0, SDAT03, SDAT02, SDAT01, SDAT00, SCK0, SDO0, SDI0, and
DOUT0 (NCS) are output Hiz).
1
1
0
0
0
1
Internal ROM boot (Deletion Partition area and IPL user area –
SD interface Ch0 and SIO external Serial Flash Ch0)
LSI test mode (Do not set to this mode when working actually).
1
1
1
1
0
1
LSI test mode (Do not set to this mode when working actually).
www.onsemi.com
18
LC823433TA
Pin Type
EN
PAD
PAD
PAD
A
EN3
EN3
EN3
CTU
Y
3ICUD/
3T2
CTD
EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
EN
A
CTU
3ISUD/
3T2
Y
3ISUD/
3T4
CTD
EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
EN
A
CTI
CTU
3ICUD/
3T4(8)
Y
3ICUD/
3T6(12)
CTD
CTI current ability switch terminal 0: 4mA 1: 8mA/ 0: 6mA 1: 12mA
EN3 = 0:PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
EN
A
PAD
EN3
CTI
CTU
3ISUD/
3T4(8)
Y
3ISUD/
3T6(12)
CTD
CTI current ability switch terminal 0: 4mA 1: 8mA/ 0: 6mA 1: 12mA
EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
Continued on next page.
www.onsemi.com
19
LC823433TA
Continued from preceding page.
Y
Y
PAD
PAD
1IC
1IS
3IS
PAD
OD3
EN
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
450 / Tray JEDEC
TQFP128 14x14 / TQFP128L
(Pb-Free / Halogen Free)
LC823433TAK-2H
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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20
相关型号：
LC823455RAH-2H
Low Power & High-Resolution Audio Processing System SoC for Portable Sound Solution
ONSEMI
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