LC823455RB-2H_技术文档

Low Power &

High-Resolution Audio

Processing System SoC for

Portable Sound Solution

LC823455

Description

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LC823455 is an audio processing System−on−Chip (SoC) for

recording and playback, with High−Resolution 32−bit & 192 kHz

audio processing capability that provides the key functions required

for portable audio solutions.

It has a Dual CPU configuration and a DSP providing intensive

processing capability, 4316 KB of internal SRAM that supports the

implementation of large-scale programs for WLAN applications, and

multiple interfaces for increased extensibility. Its features an extensive

range of functions including SBC/AAC codec and Active Noise

Canceller by the DSP, UART and ASRC − applicable for wearable

audio applications. The highly integrated implementation of this rich

set of analog functions results in a miniature footprint with ultra− low

power consumption. This, along with its high performance, makes the

LC823455 suitable for portable audio markets such as Wireless

headsets.

WLCSP120, 4.086x4.086x0.62

CASE 567WG

LFBGA240, 11.0x11.0

CASE 566EY

This document describes features, basic functions, electrical

specifications, characteristics, application diagrams and package

dimension of this SoC.

Features

• Ultra Low Power Consumption

®

LFBGA136, 11.0x11.0

CASE 566GB

• Arm Cortex −M3 Dual Core

• Proprietary 32−bit DSP Core (LPDSP32)

• Internal Large−Scale Size SRAM : 4316 KB (4MB + 220 KB)

• High−Resolution 32−bit & 192 kHz Audio Processing Capability

• Several DSP Codes Available for Audio Functions

ORDERING INFORMATION

See detailed ordering and shipping information on page 107 of

this data sheet.

• Hard−Wired Audio Functions Built−In:

MP3 decoder, MP3 encoder,

6 band Equalizer

Synchronous SRC, Asynchronous SRC, etc.

• Analog Blocks Built−in:

System PLL, Audio PLL,

16−bit DAC, Class−D amp, etc.

• USB On−The−Go(OTG) that supports USB2.0 Device and Host

Functions with an Integrated PHY,

eMMC and SD Card I/F,

Serial Flash I/F(Quad) with Cache Memory,

SPI, UART, I2C, etc.

Typical Applications

• Wearable Earbuds

• Wearable Headphone

• Wireless Speaker

• IC Recorder

NOTE:

LC823455RAH−2H and LC823455RB−2H are

under planning.

LC823455RAH−2H : Package Code = RA

LC823455RB−2H : Package Code = RB

1

Publication Order Number:

March, 2021 − Rev. 2

LC823455/D

LC823455

Table of Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Terminal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Input/Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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2

LC823455

ABSTRACT

Features

®

♦ Real Time Clock

• Cortex−M3 Dual Core, AMBA (AHB/APB) system

♦ Internal SRAM (4 M-byte)

2 modes below are available

− General RTC mode : RTC w/o key input

− KeyInt RTC mode : RTC w/ key input which

enables power on function

♦ Internal ROM (256 k-byte). Boot code, Standard

Functions

♦ SDRAM Controller (1 * CS)

64M to 256Mbit SDRAM / Mobile SDRAM

♦ External Memory Controller (2 * CS) NOR FLASH,

SRAM, ROM supported, 8/16 bit I/F LCD controller

supported

Internal ROM boot and External memory device

boot available

♦ DMA Controller (8 ch)

♦ SWD (Serial Wire Debug) is supported as the debug

interface

SWV (Serial Wire Viewer) is supported as the trace

interfaceOnly one of Cortex−M3 Dual Core can be

traced

Availability of features explained here depends on

products.

♦ Interrupt Controller (External 90 ch, Internal 83 ch)

♦ SPI (2 ch)

♦ Pseudo SRAM I/F (1 ch)

• MP3 hard wired encoder/decoder

♦ MP3 MPEG1, MPEG2, MPEG2.5

− Sampling rate: 8 kHz,11.025 kHz,12 kHz,

16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz,

48 kHz

− Bit rate: 8 Kbps to 320 Kbps (Decoder−VBR

supported)

• LPDSP32 system

♦ Internal SRAM (220 kbyte)

♦ Audio codec

♦ Serial Flash I/F (1 ch)

♦ Quad SPI, cache memory (16 k-byte, 4way set

associative, 128 line) function available

♦ UART (3ch)

UART1, UART2: w/flow control (CTS, RTS)

UART0: w/o flow control

♦ I2C (2ch) Single Master, Full/Standard

♦ GPIO (90 ch)

♦ Pin multiplex function (I2C:2 ch, SPI:2 ch, UART:3

ch, MTM:2 ch, DMIC:2 ch x 2)

♦ Plain Timer w/ Watch Dog Timer (1 ch×3)

♦ Multiple Timer (2 ch×4)

♦ 12 bit ADC (8 ch)

♦ SD Card I/F (3 ch)

− MP3

− WMA

− AAC

− SBC

− FLAC, etc.

♦ Audio function

− Active Noise Canceller

− 1−mic/2−mic Noise Canceller for Recorder

− 2−mic Noise Canceller for Hands Free

− Echo Canceller

eSD/eMMC, UHS−I, w/o CPRM

− SD0: eSD/eMMC boot supported (Internal ROM

Boot function)

− SD1: 1.8 V/3.3 V dedicated power supply

− SD2 :

− Variable Speed Control playback etc.

♦ JTAG ICE

♦ USB2.0 Device (HS/FS) Controller,

Host (HS/FS/LS) Controller with OTG Controller,

Integrated PHY.

Xtal (XT1) is required for USB function, 12, 19.2,

24 MHz for device and host with OTG function.

Host and Device share an integrated PHY.

1

MPEG Layer−3 audio coding technology licensed from Fraunhofer IIS and Thomson. Supply of this product does not convey license nor

imply any right to distribute content created with this product in revenue−generating broadcast systems (terrestrial, satellite, cable and/or

other distribution channels), streaming applications (via Internet, intranets and/or networks), other content distribution systems (pay−au-

dio or audio−on−demand applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips,

hard drives, memory cards and the like). For details, please visit http://mp3licensing.com/

Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor

imply any right to use this product in any finished end user or ready−to−use final product. An independent license for such use is required.

For details, please visit http://mp3licensing.com/

This product contain technology of Microsoft company ownership, and you cannot distribute or use without getting license from Microsoft

Licensing Company.

2

www.onsemi.com

3

LC823455

• Bluetooth Protocol Stack available

• Audio clock generation

♦ Dedicated PLL for audio

• Audio

♦ Selectable PLL reference clock

XT1 (12, 19.2, 24 MHz Main xtal)

XTRTC (32.768 kHz RTC xtal)

PCM I/F MCLK0 (/MCLK1), BCK0, BCK1

♦ MP3 hard wired encoder/decoder, MP3 MPEG1,

MPEG2, MPEG2.5

− Sampling rate: 8 kHz,11.025 kHz,12 kHz,16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48kHz

− Bit rate :8 Kbps to 320 Kbps

(Decoder−VBR supported)

• Power supply

♦ Typical voltage

♦ Other audio functions available

− 6 band Equalizer (EQ3)

− LOGIC(Vdd1),XT1(VddXT1),

PLL1(AVddPLL1), PLL2(AVddPLL2) = 1.0 V

− RTC(VddRTC) = 1.0 V

− Hardware Mixer

− Volume, Mute

− Level Meter

− Audio Timer w/ interrupt generation

− 16/24/32 bit 192 kHz PCM I/F (2ch×2).

Master/slave, I2S

− I/O(Vdd2) = 1.8 V or 3.3 V

− SD1(VddSD1) = 1.8 V or 3.3 V

− ADC(AVddADC) = 1.8V

− USB PHY(DVddUSBPHY1) = 1.0 V,

(AVddUSBPHY2) = 3.3 V,

− SSRC (Synchronous Sampling Rate Converter)

0.25 to 64 conversion capable

− ASRC (Asynchronous Sampling Rate Converter)

Jitter reducing function supporting USB audio

class and Bluetooth streaming

− Beep generator

(AVddUSBPHY18) = 1.8 V

− Class−D Amplifier

(AVddDAMPL,AVddDAMPR) = 1.5 V

− Digital Microphone I/F (2ch x2), Sampling rate :

up to 48 kHz, Support up to 4 PDM Digital

Microphones

− 16 bit Audio DAC (2 ch)

w/ Class−D Amplifier for Head Phone (2 ch).

Requires external LC LPF

3

The product name for which Bluetooth Protocol Stack is available is determined. Please contact our representative for license fee for the

Stack.

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4

LC823455

Package Codes and Functional Differences

The products with Package Code = “RA” and “RB” are under planning.

Table 1. FUNCTIONAL DIFFERENCES

Package Code

XA

RA

RB

Function

Package

WLP120

BGA240

Available

BGA136

SDRAM Controller

−

External Memory

Controller

SD0

Shared pins with S−Flash

function

Dedicated

Available

Dedicated

P−SRAM

USB2.0

−

HS/FS Device

HS/FS Device and

HS/FS Device

HS/FS/LS Host with OTG

12 bit ADC

3ch

8ch

PLL1

PLL2

Only Internal Loop Filter

Internal / External Loop Filter

Only Internal Loop Filter

XTALINFO[1:0] input

RTCMODE input

BACKUPB input

“00”

Available

“00”

(24 MHz)

“0”

Available

(KEYINT RTC mode)

Connected with VDET

internally

KEYINT input

External Interrupt

GPIO

2ch

3ch

2ch

52 ch

90 ch

53 ch

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5

LC823455

Block Diagram

12MHz,

19.2MHz,

24MHz

32.768kHz

XTRTC

SWD/SWV

ICE

JTAG

ICE

XT 1

DMAC

(8ch)

ARM Cortex-M3 ARM Cortex-M3

LPDSP32

PSRAM I/F

(1ch)

Multilayer Bus

EXT4

S-Flash I/F

(1ch)

APB

Bridge

PD -G

SRAM S8

(32Kbyte)

SRAM S9

(220Kbyte)

SRAM S7A

(256Kbyte)

SDRAM

CTRL

Cache

(16 Kbyte)

PD -10

BASIC

PD -E

Reset

Controller

SRAM S5B

(384Kbyte)

SRAM S7B

(224Kbyte)

SRAM S6

(1536Kbyte)

External

Memory

Controller

BUF

(16 Kbyte)

PD -8

PD -7

PD -9

PD -J

USB2.0

Device/Host

(OTG)

USB

PHY

SRAM S2

(256Kbyte)

SRAM S5A

(384Kbyte)

SRAM S4

(256Kbyte)

SRAM S3

(256Kbyte)

XT1

PD -4

PD -6

PD -5

Plain

Timer

(1ch×3)

Multiple

Timer

(2ch×4)

Main

Module

Manager

SRAM S1

(256Kbyte)

ROM

(256Kbyte)

SRAM S0B

(128Kbyte)

SRAM S0A

(128Kbyte)

PD -3

PD -2

PD -1

EXT1

PD -H

12 bit ADC

(8ch )

I2C

(2ch )

UART

(3ch )

SPI

(2ch )

BUF

(512 byte×3)

OSC

System

PLL

SD I/F

(3ch)

PORT0～4

(80 I/O)

PORT5

(10 I/O)

XT1 XTRTC RC

EXT3

RTC

OSC

XTRTC

ATM

BEEP

VOLUME

EQ3

Audio Buffer

(256 Kbyte)

Audio PLL

PD -RTC

MP3

Decoder

PCM

I/F

PCM

I/F

MP3

XT1

AHB CLK

(HCLK)

BCK0/1

MCLK0/1

(PCM I/F)

METER

Encoder

MUTE

SSRC

ASRC

A

N

C

*

16bit Audio

DAC

Digital

Mic

Digital

Mic

MIXER

PD -A

Class-D

AMP

Figure 1. Top−Level Block Diagram

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6

LC823455

Bus Matrix

DMAC

(8ch)

USB2.0

ARM Cortex−M3

LPDSP32

ARM Cortex−M3

System

ROM

SRAM

(Seg 0)

SRAM

(Seg 8)

SRAM

(Seg 9)

BASIC

Peripheral

EXT1

Peripheral

EXT3

Peripheral

EXT4

Peripheral

APB

Peripheral

Figure 2. Bus Matrix

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7

LC823455

Audio

256KB SRAM divided into

A~ N Audio Buffers

by register settings

Internal

Bus

A buffer

8

MP3

Encoder

RAM

B buffer

D_redirect

E_redirect

G_redirect

J_redirect

BIT1-0、

MONO

16

RAM

L_redirect

N_redirect

24

8

0

1

D

E

C

S

E

L

C buffer

E_redirect

G_redirect

J_redirect

L_redirect

N_redirect

BIT1-0、MONO

24

16

MP3

Decoder

RAM

METER

(DEC)

MUTE

(DEC)

D buffer

E buffer

32

32 Bit conv

24

32

VOLUME

(DEC)

DMCKO0A

DMDIN0A

RAM

Bit conv

SSRC

S

E

L

24

32

Digtal

Mic0

BIT1-0、MONO

1

0

P

C

M

S

E

L

DMCKO0B

DMDIN0B

32

0

1

S

I

N

S

E

L

32

PCM input

VOLUME

(SP0)

PCM

SP0

DIN0

(PCM input)

Bit conv

BIT1-0、MONO

EQ3

METER

(SP0)

SINGEN

VOLUME

(AMB)

F buffer

D_redirect

E_redirect

G_redirect

J_redirect

L_redirect

N_redirect

BIT1-0、MONO

32

24

PCM output

PCM

PS0

DOUT0

(PCM output)

32

DWNMIX

(PS0)

VOLUME

(PS0)

MUTE

(PS0)

EQ3

MIXER

BTL

BEEP

16 bit

Audio

DAC

LOUT

ROUT

Class−D

AMP

RAM

MCLK0/

BCK0/

LRCK0

METER

(PS0)

METER

(SP1)

G buffer

LRCK0

AudioTimer0

32

VOLUME

(SP1)

24

32

RAM

Bit conv

BIT1-0、

Digtal

Mic1

DMCKO1

DMDIN1

P

C

M

1

S

E

L

1

0

MONO

BIT1-0、MONO

H buffer

D_redirect

E_redirect

G_redirect

J_redirect

L_redirect

N_redirect

PCM input

PCM

SP1

DIN1

(PCM input)

DWNMIX

(PS1)

VOLUME

(PS1)

32

PCM output

RAM

PCM

PS1

DOUT1

(PCM output)

METER

MCLK1/

BCK1/

(PS1)

LRCK1

I buffer

D_redirect

E_redirect

G_redirect

L_redirect

N_redirect

BIT1-0、MONO

LRCK1

AudioTimer1

24

ASRC

RAM

J buffer

32 Bit conv

RAM

Bit conv

BIT1-0、MONO

K buffer

D_redirect

E_redirect

G_redirect

J_redirect

N_redirect

BIT1-0、MONO

RAM

L buffer

CBIT1-0、

CMONO

RAM

Bit conv

32 Bit conv

BIT1-0、MONO

32

M buffer

D_redirect

E_redirect

G_redirect

J_redirect

L_redirect

BIT1-0、MONO

RAM

N buffer

RAM

CBIT1-0、

CMONO

Bit conv

32 Bit conv

BIT1-0、MONO

Figure 3. Audio

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8

LC823455

Clock Hierarchy

12MHz

19.2MHz

24MHz

FCLKCNT

XT1

PHI1 pin

32.768kHz

Oscillation System

1/1、1/2、1/4、

1/8、1/16

PLL1

1/4

1/2

XT1

(XIN1/XOUT 1 pin)

XTRTC

(XIN32K/XOUT 32K pin )

SYSTEM PLL

(PLL1)

1/4

XT1

1/4

1/2、1/4

PHI0 pin

XTRTC

RC

1/1、1/{(1～63)×2}

BASIC CLK

APB

ADC

1/2、1/4、1/8、

1/16、1/32、1/64

1/｛(1～8)

+

(0～63)/64｝

MCLKCNTAPB

BASIC

ADCCLK

(Internal)

M3Core0

M3Core1

LPDSP32

SRAM/ROM

INTC

CORECNT

[Note]

M3Core 0, M3Core

switch enabled by the execution of

SPI0

1/｛(2～256 )×4｝

-

1

and LPDSP 32 has additional clock gating

SCK0

a

dedicated operat.ion

SPI1

1/｛(2～256 )×4｝

SCK1

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

RTC

MCLKCNTBASIC

DMAC

Cache

S-Flash I/F

SFCK

1/1、1/2、

1/4、1/8

External Memory

Controller(XMC)

XTRTC

I2C0

1/｛(2～65535)×8｝

XT1

SCL0

SCL1

USB PHY

USB2.0 Device/Host

(OTG)

I2C1

1/｛(2～65535)×8｝

MCLKCNTAPB

UART0

1/｛(8～16)×

(1～65536)｝

APB CLK (PCLK )

1/(1～64)

UART1

1/｛(8～16)×

(1～65536)｝

AHB CLK(HCLK)

MCLKCNTEXT 1

AHB EXT1

Plain Timer 0

Plain Timer 1

Plain Timer 2

Multiple Timer 0

Multiple Timer 1

Multiple Timer 2

Multiple Timer 3

Audio PLL

UART2

1/｛(8～16)×

(1～65536)｝

AUDIO Block

CLOCKEN

FS384

FS192

1/2

MP3DEC

MP3ENC

DECCLK 1/2、1/4、

1/8

1/1、1/2、

1/4

ENCCLK 1/4、1/8、

1/16

AUDCLK

FS256

1/1、1/2、

1/3

1/4

AUDIO Control

MIXER

BCK0

BCK1

XT1

AUDIO

PLL

1/2

FS768

FS384

EQ3

XTRTC

(PLL2)

System PLL

1/4

BEEP

MCLK 0/MCLK 1

(input)

OSC System

1/1、1/2、

1/4、1/8

SDCLK0

SSRC

SSRCFCLK

AHB CLK

)

ASRC

1/1、1/2、

1/4、1/8

1/1、1/2、1/4、1/8、

1/16、1/32、1/64、

1/128 、1/256 、1/512

(HCLK

MCLKCNTEXT 1

ASRCFCLK

VOLUME DEC

VOLUME SP 0

VOLUME PS0

VOLUME SP 1

VOLUME PS1

VOLUME AMB

METER DEC

METER SP0

METER PS0

METER SP1

METER PS1

MUTE DEC

MUTE PS0

PCMPS0

SD0(Main Function)

SD0(Card Detect)

SDCLK1

[Note]

-

Regarding the initial value of switches described in this fig,ure

refer to the appropriate documen.ts

1/1、1/2、1/4、1/8、

1/16、1/32、1/64、

1/128 、1/256 、1/512

MCLKCNTEXT 1

Regarding the frequency of SSRCFCLK and ASRCFCLK,

refer to the SSRC and ASRC Programm’esr Model documents.

SD1(Main Function)

SD1(Card Detect)

ENCCLK frequency should be192 * FS

while FS is Sampling Frequency of MPE1Gmode of MP3.

ex.) ENCCLK should be8.4672MHz to make all of MP

44.1/22.05/11.025 KHz (MPEG1/MPEG2/MPEG2.5).

3 data

SDCLK2

-

DECCLK frequency should be384 * FS

while FS is Sampling Frequency of MPE1Gmode of MP3.

1/1、1/2、1/4、1/8、

1/16、1/32、1/64、

1/128 、1/256 、1/512

ex.) DECCLK should be16.9344MHz to make all of MP

44.1/22.05/11.025 KHz (MPEG1/MPEG2/MPEG2.5).

3 data

MCLKCNTEXT 1

SD2(Main Function)

SD2(Card Detect)

PCMSP0

MCLKCNTEXT 3

AHB EXT3

PCMPS1

AUDIO BUFFER

PCMSP1

AudioTimer 0

AudioTimer 1

SINGEN

AHB EXT4

PSRAM I/F

1/(1～64)

PLL1

MCLKCNTEXT 4

XT1

DigitalMIC0

DigitalMIC1

PCKGEN

[Note]

-

PSM_SCK

Class-D AMP has additional clock source and gating switch

for being used as GPO.

1/1, 1/2,

FS384

1/4

SDRAM CTRL

Damp CTL

Class -D AMP

SDRCLK

FCEDAC

AHB CLK

(EXT4 only)

1/1, 1/2, 1/4, 1/8,

1/16, 1/32

16bit Audio

DAC(Noise Shaping )

MCLK0/MCLK1

)

(output

1/1, 1/2, 1/4

1/8, 1/16

DAC(Main)

1/1, 1/21/4, 1/8,

1/16, 1/32

Figure 4. Clock Hierarchy

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9

LC823455

Memory Map

All Areas (Cortex−M3)

Figure 5. All Areas (Cortex−M3)

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10

LC823455

Code Area (Cortex−M3)

Table 2. CODE AREA (CORTEX−M3) − UNREMAPPED (AFTER RESET)

Cortex−M3−0

Cortex−M3−1

I−Bus

System−

Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0x1C00

0000

Reserved

0x1A00

0000

External memory 1

External memory 0

Reserved

d

0x1800

0000

0x0600

0000

0x0500

0000

S−Flash I/F

d

(Memory, Cache)

0x0254

0000

Reserved

256 KB Internal ROM

Reserved

0x0250

0000

d

0x0243

7000

0x0240

0000

220 KB Internal SRAM

(seg 9)

d

0x023F

8000

32 KB Internal SRAM

(seg 8)

480 KB

Internal

SRAM

0x023C

0000

224 KB

(seg 7−B)

0x0238

0000

256KB

(seg 7)

(seg 7−A)

0x0220

0000

1536 KB Internal SRAM

(seg 6)

768 KB

Internal

SRAM

0x021A

0000

384 KB

(seg 5−B)

0x0214

0000

384 KB

(seg 5)

(seg 5−A)

0x0210

0000

256 KB Internal SRAM

(seg 4)

0x020C

0000

256 KB Internal SRAM

(seg 3)

0x0208

0000

256 KB Internal SRAM

(seg 2)

0x0204

0000

256 KB Internal SRAM

(seg 1)

256 KB

Internal

SRAM

0x0202

0000

128 KB

(seg 0−B)

0x0200

0000

128 KB

(seg 0)

(seg 0−A)

0x0004

0000

Reserved

0x0000

0000

256 KB Internal ROM

Shadow Area

d

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11

LC823455

Table 3. CODE AREA (CORTEX−M3) − REMAPPED (REMAP[1:0]=2’B01)

Cortex−M3−0

Cortex−M3−1

I−Bus

System−

Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0x1C00

0000

Reserved

0x1A00

0000

External memory 1

External memory 0

Reserved

d

0x1800

0000

0x0600

0000

S−Flash I/F

0x0500

0000

d

(Memory, Cache)

0x0254

0000

Reserved

256 KB Internal ROM

Reserved

0x0250

0000

d

0x0243

7000

220 KB Internal SRAM

(seg 9)

0x0240

0000

d

32 KB Internal SRAM

(seg 8)

0x023F

8000

224 KB

480 KB

0x023C

0000

(seg 7−B)

Internal

SRAM

256 KB

0x0238

0000

(seg 7)

(seg 7−A)

1536 KB Internal SRAM

(seg 6)

0x0220

0000

384 KB

768 KB

0x021A

0000

(seg 5−B)

Internal

SRAM

384 KB

0x0214

0000

(seg 5)

(seg 5−A)

256 KB Internal SRAM

(seg 4)

0x0210

0000

256 KB Internal SRAM

(seg 3)

0x020C

0000

256 KB Internal SRAM

(seg 2)

0x0208

0000

256 KB Internal SRAM

(seg 1)

0x0204

0000

128 KB

256 KB

0x0202

0000

(seg 0−B)

Internal

SRAM

128 KB

0x0200

0000

(seg 0)

(seg 0−A)

0x0004

0000

Reserved

256 KB

Internal

SRAM

0x0002

0000

128 KB

d

(seg 0−B)

(seg 0)

128 KB

0x0000

0000

Shadow

Area

(seg 0−A)

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12

LC823455

Table 4. CODE AREA (CORTEX−M3) − REMAPPED (REMAP[1:0]=2’B11)

Cortex−M3−0

Cortex−M3−1

I−Bus

System−

Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0x1C00

0000

Reserved

0x1A00

0000

External memory 1

External memory 0

Reserved

d

0x1800

0000

0x0600

0000

S−Flash I/F

0x0500

0000

d

(Memory, Cache)

0x0254

0000

Reserved

256 KB Internal ROM

Reserved

0x0250

0000

d

0x0243

7000

220 KB Internal SRAM

(seg 9)

0x0240

0000

d

32 KB Internal SRAM

(seg 8)

0x023F

8000

224 KB

480 KB

0x023C

0000

(seg 7−B)

Internal

SRAM

256 KB

0x0238

0000

(seg 7)

(seg 7−A)

1536KB Internal SRAM

(seg 6)

0x0220

0000

384 KB

768 KB

0x021A

0000

(seg 5−B)

Internal

SRAM

384 KB

0x0214

0000

(seg 5)

(seg 5−A)

256KB Internal SRAM

(seg 4)

0x0210

0000

256KB Internal SRAM

(seg 3)

0x020C

0000

256KB Internal SRAM

(seg 2)

0x0208

0000

256KB Internal SRAM

(seg 1)

0x0204

0000

128 KB

256 KB

0x0202

0000

(seg 0−B)

Internal

SRAM

128 KB

0x0200

0000

(seg 0)

(seg 0−A)

External memory 0

Shadow Area

0x0000

0000

d

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13

LC823455

SRAM Area (Cortex−M3)

Table 5. SRAM AREA (CORTEX−M3)

Cortex−M3−0

Cortex−M3−1

I−Bus D−Bus

System−

Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0x2600

0000

Reserved

0x2500

0000

S−Flash I/F

d

(Memory, Cache)

0x2400

0000

S−Flash I/F

(Memory, No Cache)

0x2043

7000

Reserved

0x2040

0000

220 KB Internal SRAM

(seg 9) Shadow area

d

0x203F

8000

32 KB Internal SRAM

(seg 8) Shadow area

0x203C

0000

480 KB

224 KB

Internal

d

(seg 7−B)

SRAM

(seg 7)

256 KB

Shadow

0x2038

0000

d

(seg 7−A)

area

0x2020

0000

1536 KB Internal SRAM

(seg 6) Shadow area

0x201A

0000

768 KB

384 KB

Internal

(seg 5−B)

SRAM

(seg 5)

384 KB

Shadow

0x2014

0000

d

(seg 5−A)

area

0x2010

0000

256 KB Internal SRAM

(seg 4) Shadow area

d

0x200C

0000

256 KB Internal SRAM

(seg 3) Shadow area

0x2008

0000

256 KB Internal SRAM

(seg 2) Shadow area

0x2004

0000

256 KB Internal SRAM

(seg 1) Shadow area

256 KB

128 KB

0x2002

0000

Internal

d

(seg 0−B)

SRAM

(seg 0)

128 KB

Shadow

0x2000

0000

(seg 0−A)

area

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14

LC823455

Other Areas (Cortex−M3)

Table 6. OTHER AREAs (CORTEX−M3)

Cortex−M3−0

Cortex−M3−1

I−Bus D−Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0xE010

0000

Reserved

0xE00F

F000

ROM table

d

(Note 1)

0xE00F

E000

CORE REG

d

(Note 1)

0xE004

1000

Reserved

TPIU

0xE004

0000

d

(Note 1)

0xE000

F000

Reserved

NVIC

0xE000

E000

d

(Note 1)

0xE000

3000

Reserved

FPB

0xE000

2000

d

(Note 1)

0xE000

1000

DWT

ITM

d

(Note 1)

0xE000

0000

d

(Note 1)

0x6400

2000

Reserved

PSRAM I/F

SDRAM CTRL

Reserved

SDRAM Memory area

Reserved

RTC

0x6400

1000

d

0x6400

0000

0x6200

0000

0x6000

0000

d

0x4008

F000

0x4008

E000

d

0x4008

D000

UART2

d

0x4008

C000

UART1

0x4008

B000

UART0

0x4008

A000

I2C1

0x4008

9000

I2C0

0x4008

8800

SPI1

d

0x4008

8000

SPI0

0x4008

7000

ADC

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15

LC823455

Table 6. OTHER AREAs (CORTEX−M3) (continued)

Cortex−M3−0

Cortex−M3−1

I−Bus D−Bus

System−

Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0x4008

6000

PORT5

d

0x4008

5000

PORT4

PORT3

0x4008

4000

0x4008

3000

PORT2

0x4008

2000

PORT1

0x4008

1000

PORT0

0x4008

0000

System Controller

Reserved

0x4006

5000

0x4006

4000

Audio Controls

MP3 Encoder

MP3 Decoder

Audio Functions

Audio Buffer

Reserved

d

0x4006

3000

0x4006

2000

0x4006

1000

0x4006

0000

d

0x4004

D000

0x4004

C000

SD2

d

0x4004

B000

SD1

0x4004

A000

SD0

0x4004

9000

Plain Timer2

Plain Timer1

Plain Timer0

Multiple Timer3

Multiple Timer2

Multiple Timer1

Multiple Timer0

Audio PLL

0x4004

8000

0x4004

7000

0x4004

6000

0x4004

5000

0x4004

4000

0x4004

3000

0x4004

2000

0x4004

1000

System PLL

OSC System

0x4004

0000

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16

LC823455

Table 6. OTHER AREAs (CORTEX−M3) (continued)

Cortex−M3−0

Cortex−M3−1

I−Bus D−Bus

System−

Bus

System−

Bus

I−Bus

D−Bus

Address

Master / Slave

DMAC

USB20

0x4002

0000

Reserved

0x4001

0000

USB2.0 FIFO

Reserved

d

0x4000

7000

0x4000

6000

DSP CMDIF

MUTEX REG

DMAC

d

0x4000

5000

0x4000

4000

0x4000

3000

INTC

0x4000

2000

USB2.0 CTL

S−Flash I/F

External MEM CTL

0x4000

1000

0x4000

0000

1. Access from internal peripheral bus(AHB/APB)

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17

LC823455

LPDSP32

Table 7. LPDSP32 − DMA

LPDSP32

DMA

Address

0x40 0000

0x3F 8000

0x3C 0000

0x38 0000

0x20 0000

0x1A 0000

0x14 0000

0x10 0000

0x0C 0000

0x08 0000

0x04 0000

0x02 0000

0x00 0000

Master / Slave

Reserved

32 KB Internal SRAM (seg 8)

d

480 KB Internal SRAM (seg 7)

224 KB (seg 7−B)

256 KB (seg 7−A)

1536 KB Internal SRAM (seg 6)

768 KB Internal SRAM (seg 5)

384 KB (seg 5−B)

384 KB (seg 5−A)

256 KB Internal SRAM (seg 4)

256 KB Internal SRAM (seg 3)

256 KB Internal SRAM (seg 2)

256 KB Internal SRAM (seg 1)

256 KB Internal SRAM (seg 0)

128 KB (seg 0−B)

128 KB (seg 0−A)

Table 8. LPDSP32 – DMB

LPDSP32

DMB

Address

0xC0 0000

0xBF 8000

0xBC 0000

0xB8 0000

0xA0 0000

0x9A 0000

0x94 0000

0x90 0000

0x8C 0000

0x88 0000

0x84 0000

0x82 0000

0x80 0000

Master / Slave

Reserved

32 KB Internal SRAM (seg 8)

480 KB Internal SRAM (seg 7)

224 KB (seg 7−B)

d

256 KB (seg 7−A)

1536 KB Internal SRAM (seg 6)

768 KB Internal SRAM (seg 5)

384 KB (seg 5−B)

384 KB (seg 5−A)

256 KB Internal SRAM (seg 4)

256 KB Internal SRAM (seg 3)

256 KB Internal SRAM (seg 2)

256 KB Internal SRAM (seg 1)

256 KB Internal SRAM (seg 0)

128 KB (seg 0−B)

128 KB (seg 0−A)

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18

LC823455

Table 9. LPDSP32 − DMIO

LPDSP32

DMIO

Address

0xF0 2000

0xF0 1000

0xF0 0000

0xD0 0000

0xC6 5000

0xC6 4000

0xC6 3000

0xC6 2000

0xC6 1000

0xC6 0000

0xC4 A000

0xC4 9000

0xC4 8000

0xC4 7000

0xC4 6000

0xC4 5000

0xC4 4000

0xC4 3000

0xC4 2000

0xC4 1000

0xC4 0000

0xC0 7000

0xC0 6000

0xC0 5000

0xC0 4000

0xC0 3000

0xC0 0000

Master / Slave

Reserved

PSRAM I/F

d

SDRAM CTRL

SDRAM Memory Area

Reserved

Audio Controls

MP3 Encoder

MP3 Decoder

Audio Functions

Audio Buffer

Reserved

d

Plain Timer2

Plain Timer1

Plain Timer0

Multiple Timer3

Multiple Timer2

Multiple Timer1

Multiple Timer0

Audio PLL

d

System PLL

OSC System

Reserved

DSP CMDIF

MUTEX REG

DMAC

d

INTC

Reserved

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19

LC823455

Table 10. LPDSP32 − PM

LPDSP32

PM

Address

0x50 3332

0x50 0000

0x4B 0000

0x48 0000

Master / Slave

Reserved

32 KB Internal SRAM (seg 8)

Reserved

d

480 KB Internal SRAM (seg 7)

224 KB (seg 7−B)

256 KB (seg 7−A)

0x41 9998

0x38 0000

0x34 CCCC

0x30 0000

Reserved

1536 KB Internal SRAM (seg 6)

Reserved

768 KB Internal SRAM (seg 5)

384 KB (seg 5−B)

384 KB (seg 5−A)

0x29 9998

0x28 0000

0x21 9998

0x20 0000

0x19 9998

0x18 0000

0x11 9998

0x10 0000

0x09 9998

0x08 0000

Reserved

256 KB Internal SRAM (seg 4)

Reserved

d

256 KB Internal SRAM (seg 3)

Reserved

256 KB Internal SRAM (seg 2)

Reserved

256 KB Internal SRAM (seg 1)

Reserved

256 KB Internal SRAM (seg 0)

128 KB (seg 0−B)

128 KB (seg 0−A)

d

0x01 6000

0x00 0000

Reserved

220 KB Internal SRAM (seg 9)

d

2. PM of LPDSP32 cannot access internal SRAM seg5, 6, and 7.

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20

LC823455

TERMINAL FUNCTIONS

XA: Package Code = “XA”, RA: Package Code = “RA”, RB: Package Code = “RB”, (RA and RB are under planning).

Table 11. TERMINAL FUNCTIONS

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

JTAG/SWD

TDO

VddSD1

−

Pos

−

O

I

JTAG test data output

SD I/F Ch1 write protect

GPIO

d

6

d

6

d

6

SDWP1

GPIO21

EXTINT21

TDI

B

I

−

External Interrupt 2−bit1

JTAG test data input

SD I/F Ch1 detect

serial wire view data

GPIO

VddSD1

−

I

SDCD1

SWO

Neg

−

I

O

B

I

GPIO20

EXTINT20

TMS

−

External Interrupt 2−bit0

JTAG test data select

SD I/F Ch2 write protect

GPIO

Vdd2

−

I

SDWP2

GPIO28

EXTINT28

TCK

Pos

−

I

B

I

−

External Interrupt 2−bit8

JTAG test clock

Pos

Neg

−

I

SDCD2

GPIO29

EXTINT29

SWDCLK

DMCKO0B

GPIO58

EXTINT58

SWDIO

DMDIN0B

GPIO59

EXTINT59

I

SD I/F Ch2 detect

GPIO

B

I

−

External Interrupt 2−bit9

Serial wire clock

Digital Mic Ch0 Clock B Output

GPIO

Pos

−

I

O

B

I

−

External Interrupt 5−bit8

Serial wire Data

−

B

I

−

Digital Mic Ch0 Data B Input

GPIO

−

B

I

−

External Interrupt 5−bit9

Sum

RTC

XIN32K

Pos

−

I

32.768KHz XTAL Input

(XTRTC)

VddRTC

d

XOUT32K

O

32.768KHzXTAL Output

(XTRTC)

VDET

Neg

I

RTC power detect Input

VddRTC

d

RTCINT

O

RTC Interrupt Output (Normal:

Hiz, Interrupt enabled:Low Out-

put)

BACKUPB

Neg

I

RTC backup mode input

VddRTC

d

Bonded with VDET internally

for “XA”

KEYINT[2]

−

I

RTC KEY input can be used

when KeyInt RTC mode

VddRTC

d

KEYINT[1:0]

RTC KEY input can be used

when KeyInt RTC mode

d

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21

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

RTC

RTCMODE

−

I

RTC mode input (Note 3)

VddRTC

d

Set General or KeyInt RTC

mode

RTCMODE =

“0” : KeyInt RTC mode

“1” : General RTC mode

Bonded to “0” internally for “XA”

VddRTC

VssRTC

−

P

RTC power supply

RTC ground

Sum

d

8

d

11

10

EXTERNAL INTERRUPT/GPIO

Vdd2

SDRADDR12

GPIO2A

−

O

B

I

SDRAM address

GPIO

d

EXTINT2A

SCL1

External Interrupt 2−bit10

O

I2C ch1 Clock (open drain out-

put )

d

GPIO2B

EXTINT2B

SDA1

−

B

I

GPIO

d

External Interrupt 2−bit11

Vdd2

B

I2C ch1 Data (open drain out-

put )

GPIO2C

EXTINT2C

SDRADDR11

DMCKO0A

GPIO2D

−

B

I

GPIO

d

External Interrupt 2−bit12

SDRAM address

Digital Mic Ch0 Clock A Output

GPIO

O

B

I

EXTINT2D

EXTINT2E

GPIO2E

External Interrupt 2−bit13

External Interrupt 2−bit14

GPIO

Vdd2

I

B

I

EXTINT2F

GPIO2F

External Interrupt 2−bit15

GPIO

B

* During Internal ROM boot,

this terminal is used as the boot

monitor signal.

Sum

5

6

5

SPI (SERIAL I/F CH0)

SCK0

Vdd2

Neg

−

B

I

Serial I/F Ch0 Clock

GPIO

d

3

d

3

d

3

GPIO1D

EXTINT1D

SDI0

−

External Interrupt 1−bit13

Serial I/F Ch0 Data Input

GPIO

−

I

GPIO1E

−

B

I

EXTINT1E

SDO0

−

External Interrupt 1−bit14

Serial I/F Ch0 Data Output

GPIO

−

O

B

I

GPIO1F

−

EXTINT1F

−

External Interrupt 1−bit15

Sum

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22

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

S−FLASH I/F / SD I/F CH0 (Note 4)

Vdd2

SFCK

Neg

O

Serial Flash I/F Clock

d

(QSPI Clock)

GPIO0D

EXTINT0D

SDCLK0

−

B

I

GPIO

d

External Interrupt 0−bit13

SD I/F Ch0 Clock Output

O

Vdd2

SFDI(QIO0)

I(B)

Serial Flash I/F Data input

(QSPI Data 0)

GPIO0E

EXTINT0E

SDAT00

−

B

I

GPIO

d

External Interrupt 0−bit14

SD I/F Ch0 Data0

B

SFDO(QIO1)

O(B)

Serial Flash I/F Data output

(QSPI Data 1)

GPIO0F

EXTINT0F

SDAT01

−

B

I

GPIO

d

External Interrupt 0−bit15

SD I/F Ch0 Data1

−

B

SFWP(QIO2)

Neg

O(B)

Serial Flash I/F write protect

(QSPI Data 2)

GPIO11

EXTINT11

−

B

I

GPIO

d

External Interrupt 1−bit1

SD I/F Ch0 Data2

SDAT02

−

B

SFHOLD(QIO3)

Neg

O(B)

Serial Flash I/F hold

(QSPI Data 3)

GPIO12

EXTINT12

SDAT03

−

B

I

GPIO

d

5

d

5

d

5

External Interrupt 1−bit2

SD I/F Ch0 Data3

Sum

B

I2C

Vdd2

SCL0

−

O

I2C ch0 Clock (open drain out-

put )

d

GPIO07

EXTINT07

SDA0

−

B

I

GPIO

d

External Interrupt 0−bit7

B

I2C ch0 Data (open drain out-

put )

GPIO08

−

B

I

GPIO

d

2

d

2

d

2

EXTINT08

External Interrupt 0−bit8

Sum

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23

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

UART

Vdd2

TXD1

SDAT20

GPIO04

EXTINT04

RXD1

−

O

B

I

UART Ch1 transmit Data

SD I/F Ch2 Data 0

GPIO

d

−

External Interrupt 0−bit4

UART Ch1 receive Data

SD I/F Ch2 Data 1

GPIO

Vdd2

−

I

SDAT21

GPIO05

EXTINT05

CTS1

−

B

I

−

External Interrupt 0−bit5

UART Ch1 clear to send

SD I/F Ch2 Data 2

UART Ch0 receive Data

GPIO

Neg

−

I

SDAT22

RXD0

B

I

−

GPIO56

EXTINT56

RTS1

−

B

I

−

External Interrupt 5−bit6

UART Ch1 request to send

SD I/F Ch2 Data 3

UART Ch0 transmit Data

GPIO

Vdd2

Neg

−

O

B

O

B

I

SDAT23

TXD0

−

GPIO57

EXTINT57

TXD2

−

External Interrupt 5−bit7

UART Ch2 transmit Data

MTM1 Ch0A

−

O

B

TIOCA10

−

− target signal of pulse−length−

reader function

− output of sentinel−inform−

function

− output of PWM output

GPIO0B

EXTINT0B

RXD2

−

B

I

GPIO

d

External Interrupt 0−bit11

UART Ch2 receive Data

Vdd2

I

TIOCA11

B

MTM1 Ch1A

− target signal of pulse−length−

reader

function

− output of sentinel−inform−

function

− output of PWM output

GPIO0C

−

B

I

GPIO

d

6

d

6

d

6

EXTINT0C

External Interrupt 0−bit12

Sum

TIMER

Vdd2

TIOCA00

−

B

MTM0 Ch0A

d

− target signal of pulse−length−

reader

function

− output of sentinel−inform−

function

− output of PWM output

SD I/F Ch2 Clock Output

System Clock Output 0

SDCLK2

PHI0

−

O

d

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24

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

TIMER

GPIO09

EXTINT09

TIOCA01

−

B

I

GPIO

d

External Interrupt 0−bit9

Vdd2

B

MTM0 Ch1A

− target signal of pulse−length−

reader

function

− output of sentinel−inform−

function

− output of PWM output

SD I/F Ch2 command line

System Clock Output 1

GPIO

SDCMD2

PHI1

−

B

O

B

I

d

GPIO0A

EXTINT0A

TIOCB00

External Interrupt 0−bit10

Vdd2

B

MTM0 Ch0B

− target signal of pulse−length−

reader

function

− output of sentinel−inform−

function

DIN1

−

I

PCM1 Data Input

Digital Mic Ch0 Data A Input

GPIO

d

DMDIN0A

GPIO02

B

I

EXTINT02

TIOCB01

External Interrupt 0−bit2

Vdd2

B

MTM0 Ch1B

− target signal of pulse−length−

reader

function

− output of sentinel−inform−

function

SFQSCS

Neg

O

Serial Flash I/F QSPI chip se-

lect

d

During Serial Flash Boot, this is

used as chip select of Serial

Flash

GPIO03

EXTINT03

SDCMD0

TCLKA0

BCK1

−

B

I

GPIO

d

6

d

6

d

6

External Interrupt 0−bit3

SD I/F Ch0 command line

MTM0 external Clock A

PCM1 bit Clock

GPIO

B

I

Vdd2

B

I

GPIO00

EXTINT00

TCLKB0

LRCK1

External Interrupt 0−bit0

MTM0 external Clock B

PCM1 LR Clock

GPIO

I

B

I

GPIO01

EXTINT01

External Interrupt 0−bit1

Sum

PCM I/F

MCLK0

MCLK1

GPIO18

Vdd2

Pos

−

B

PCM0 maser Clock

PCM1 master Clock

GPIO

d

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25

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

PCM I/F

EXTINT18

BCK0

−

I

B

O

B

I

External Interrupt 1−bit8

PCM0 bit Clock

d

8

d

8

d

8

Vdd2

DMCKO0B

GPIO19

EXTINT19

LRCK0

Digital Mic Ch0 Clock B Output

GPIO

External Interrupt 1−bit9

PCM0 LR Clock

Vdd2

B

I

DMDIN0B

GPIO1A

EXTINT1A

DIN0

Digital Mic Ch0 Data B Input

GPIO

B

I

External Interrupt 1−bit10

PCM0 Data Input

Digital Mic Ch0 Data A Input

GPIO

I

DMDIN0A

GPIO1B

EXTINT1B

DOUT0

I

B

I

External Interrupt 1−bit11

PCM0 Data Output

Digital Mic Ch0 Clock A Output

GPIO

O

B

I

DMCKO0A

GPIO1C

EXTINT1C

BCK1

External Interrupt 1−bit12

PCM1 bit Clock

Vdd2

B

I

GPIO13

EXTINT13

LRCK1

GPIO

External Interrupt 1−bit3

PCM1 LR Clock

B

I

GPIO14

EXTINT14

DOUT1

GPIO

External Interrupt 1−bit4

PCM1 Data Output

GPIO

O

B

I

GPIO15

EXTINT15

External Interrupt 1−bit5

Sum

SD IF

SDCLK0

−

O

B

O

B

I

SD I/F Ch0 Clock Output

SD I/F Ch0 command line

SD I/F Ch0 Data

SD I/F Ch1 Clock Output

GPIO

Vdd2

d

12

d

12

SDCMD0

SDAT0[3:0]

SDCLK1

Vdd2

VddSD1

d

6

GPIO22

EXTINT22

SDCMD1

GPIO23

External Interrupt 2−bit2

SD I/F Ch1 command line

GPIO

VddSD1

B

I

EXTINT23

SDAT1[3:0]

GPIO2[7:4]

EXTINT2[7:4]

External Interrupt 2−bit3

SD I/F Ch1 Data

GPIO

B

I

External Interrupt 2−bit7 to bit4

Sum

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26

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

PSEUDO SRAM

PSM_SCK

−

Neg

−

O

P−SRAM I/F Clock Output

Vdd2

d

PSM_CS

P−SRAM I/F chip select Output

PSM_SDI(DAT0)

I(B)

P−SRAM I/F Data input(QPI

Data0)

PSM_SDO(DAT1)

−

O(B)

P−SRAM I/F Data output(QPI

Data1)

Vdd2

d

PSM_DAT2

PSM_DAT3

−

B

P−SRAM I/F QPI Data 2

P−SRAM I/F QPI Data 3

Sum

Vdd2

d

6

0

SDRAM I/F

SDRCLK

SDRCKE

SDRCS

Neg

Pos

Neg

Pos

O

SDRAM Clock Output

Vdd2

d

SDRAM Clock enable Output

SDRAM chip select Output

SDRAM write enable Output

SDRAM CAS Output

SDRWE

SDRCAS

SDRRAS

SDRDQM[1:0]

SDRAM RAS Output

SDRAM Data mask byte lane

select

SDRADDR[10:0]

SDRBA[1:0]

−

O

B

SDRAM address (Note 5)

SDRAM bank select

SDRAM Data

Vdd2

d

SDRDATA[15:0]

d

Sum

0

37

0

EXTERNAL MEMORY I/F

Vdd2

NCS0

GPIO06

EXTINT06

NCS1

Neg

O

B

I

chip select0

d

−

−−

Neg

−

GPIO

External Interrupt 0−bit6

chip select1

O

I

(Note 6)

RXD0

UART Ch0 receive Data

GPIO

d

GPIO10

EXTINT10

NRD

−

B

I

d

−

External Interrupt 1−bit0

read enable

d

Vdd2

Neg

−

O

B

I

(Note 6)

GPIO17

EXTINT17

NWRENWRL

DIN0

GPIO

d

−

External Interrupt 1−bit7

write enable, write enable low

PCM0 Data Input

GPIO

d

Neg

−

O

I

(Note 6)

d

GPIO30

EXTINT30

NHBNWRH

−

B

I

d

−

External Interrupt 3−bit0

Vdd2

Neg

O

high byte select, write enable

high

(Note 6)

TXD0

DOUT0

−

O

B

I

UART Ch0 transmit Data

PCM0 Data Output

GPIO

d

GPIO31

EXTINT31

External Interrupt 3−bit1

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27

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

EXTERNAL MEMORY I/F

NLBEXA0

Vdd2

−

O

B

I

low byte select, address0

(Note 6)

d

(Note 6)

GPIO16

GPIO

d

EXTINT16

External Interrupt 1−bit6

Vdd2

EXA[20:15]

O

B

I

address

GPIO4[5:0]

GPIO

EXTINT4[5:0]

EXA[14:9]

External Interrupt 4−bit5 to bit0

O

B

I

address

GPIO

GPIO3[F:A]

EXTINT3[F:A]

External Interrupt 3−bit15 to

bit10

Vdd2

EXA[8:5]

GPIO3[9:6]

EXTINT3[9:6]

EXA4

−

O

B

I

address

d

GPIO

External Interrupt 3−bit9 to bit6

O

B

I

address

DOUT1

PCM1 Data Output

GPIO35

GPIO

EXTINT35

EXA3

External Interrupt 3−bit5

Vdd2

O

I

address

(Note 6)

DIN1

PCM1 Data Input

d

GPIO34

B

I

GPIO

EXTINT34

EXA[2:1]

External Interrupt 3−bit4

Vdd2

O

B

I

address

GPIO3[3:2]

EXTINT3[3:2]

EXD[7:0]

GPIO4[D:6]

EXTINT4[D:6]

GPIO

External Interrupt 3−bit3 to bit2

B

I

Data

GPIO

External Interrupt 4−bit13 to

bit6

Vdd2

EXD[15:10]

GPIO5[5:0]

EXTINT5[5:0]

EXD[9:8]

−

B

I

Data

d

GPIO

External Interrupt 5−bit5 to bit0

B

I

Data

GPIO4[F:E]

EXTINT4[F:E]

GPIO

External Interrupt 4−bit15 to

bit14

Sum

5

42

6

XTAL, PLL

XIN1

−

I

XTAL input (XT1)

VddXT1

d

XOUT1

VddXT1

VssXT1

O

P

XTAL output (XT1)

XTAL power supply (XT1)

XTAL ground (XT1)

VddXT1

−

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28

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

XTAL, PLL

XTALINFO[1: 0]

−

B

XTALINFO[1: 0] =

Vdd2

d

“00” : 24MHz

“01” : 12MHz

“10” : 19.2MHz

“11” : reserved

Used for determining clock fre-

quency setting during internal

ROM boot.

Bonding “00” internally for XA.

VCNT1

AVddPLL1

AVssPLL1

VCNT2

−

O

P

O

P

PLL1 VCO control

AVddPLL1

d

PLL1 analog power supply

PLL1 analog power ground

PLL2 VCO control

−

d

−

d

AVddPLL2

d

AVddPLL2

AVssPLL2

PLL2 analog power supply

PLL2 analog power ground

Sum

−

d

8

d

8

d

12

USB−PHY

USBDP

−

B

I

USB D+

AVddUSBPHY2

AVddUSBPHY18

−

d

USBDM

USB D−

USBEXT02

USBVBUS

USBID

USB reference resistor

USB 5V VBUS detection

USB identifier

B

P

AVddUSBPHY18

−

DVddUSBPHY1

USB−PHY 1.0V digital power

supply

AVddUSBPHY2

AVddUSBPHY18

AVssUSBPHY

−

P

USB−PHY 3.3V analog power

supply

−

d

USB−PHY 1.8V analog power

supply

USB−PHY ground

d

2

Sum

10

12 BIT ADC

SIN[7: 3]

−

I

ADC input ch7−3

ADC input ch2−0

ADC analog power supply

ADC analog power ground

Sum

AVddADC

d

SIN[2: 0]

I

AVddADC

d

5

AVddADC

AVssADC

P

−

d

10

CLASS−D AMP

LOUT

AVddDAMPL

AVddDAMPR

−

O

P

Lch Class D AMP Output

d

GPLOUT

ROUT

General purpose Output (GPO)

Rch Class D AMP Output

GPROUT

AVddDAMPL

General purpose Output (GPO)

Lch Class D AMP analog power

supply

−

AVddDAMPR

−

P

Rch Class D AMP analog

power supply

d

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29

LC823455

Table 11. TERMINAL FUNCTIONS (continued)

Terminal Name

Polarity

Direction

Function

Available(d)

Multiplexed

Function

XA

RA

RB

IO POWER

CLASS−D AMP

AVssDAMPL

−

P

Lch Class D AMP analog power

ground

−

d

6

d

6

d

6

AVssDAMPR

Rch Class D AMP analog

power ground

Sum

OTHER, POWER

BMODE[1: 0]

TEST

−

B

I

Boot mode select

Vdd2

d

Pos

test mode

VddRTC

Connect to ground.

NRES

IO18V

Neg

−

I

SoC reset input

Vdd2

Vdd1

d

1.8 V IO range select for I/O of

Vdd2

“0” : 3.3 V IO operation

“1” : 1.8 V IO operation

When setting “1”, don’t supply

any voltage over the 1.8 V volt-

age range to Vdd2.

Vdd1

Vdd2

−

P

Digital core power supply

−

d

6

7

6

Digital IO power supply

d

6

15

7

VddSD1

Vss1

Digital IO power supply(SDI/F

ch1)

d

1

Digital core power ground

d

6

9

6

Vss2

Digital IO power ground

d

7

15

8

Sum

31

52

33

All Sum

120

240

136

3. Set according to the General RTC mode or KeyInt RTC mode.

4. S−Flash I/F / SD I/F Ch0 includes SFQSCS / SDCMD0 in Timer.

5. SDRAM address bit is 13 bit including SDRADDR [12:11].

6. This function is not available.

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LC823455

Signals Handled by Pin Multiplex Function

The pin multiplex function can be used to assign

low−speed signals to any of GPIOs. The table below shows

the signal functions that can be multiplexed and the GPIOs

that can be assigned.

Table 12. PIN MULTIPLEX FUNCTIONS

Number

Module name

Signal name

Function

Assigned GPIO

GPIO00 to 0F

0

I2C0

SCL0

SDA0

SCL1

SDA1

SCK0

SDI0

I2C ch0 Clock

I2C ch0 Data

I2C ch1 Clock

I2C ch1 Data

GPIO10 to 1F

GPIO20 to 2F

GPIO30 to 3F

GPIO40 to 4F

GPIO50 to 59

1

2

I2C1

SPI0

3

4

Serial I/F Ch0 Clock

Serial I/F Ch0 Data Input

Serial I/F Ch0 Data Output

Serial I/F Ch1 Clock

Serial I/F Ch1 Data Input

Serial I/F Ch1 Data Output

MTM0 external Clock A

MTM0 external Clock B

MTM0 Ch0A

5

6

SDO0

SCK1

SDI1

7

SPI1

8

9

SDO1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

MTM0

TCLKA0

TCLKB0

TIOCA00

TIOCA01

TIOCB00

TIOCB01

TCLKA1

TCLKB1

TIOCA10

TIOCA11

TIOCB10

TIOCB11

RXD0

MTM0 Ch1A

MTM0 Ch0B

MTM0 Ch1B

MTM1

MTM1 external Clock A

MTM1 external Clock B

MTM1 Ch0A

MTM1 Ch1A

MTM1 Ch0B

MTM1 Ch1B

UART0

UART1

UART Ch0 receive Data

UART Ch0 transmit Data

UART Ch1 receive Data

UART Ch1 transmit Data

UART Ch1 clear to send

UART Ch1 request to send

UART Ch2 receive Data

UART Ch2 transmit Data

UART Ch2 clear to send

UART Ch2 request to send

Digital Mic Ch0 Clock Output

Digital Mic Ch0 Data Input

Digital Mic Ch1 Clock Output

Digital Mic Ch1 Data Input

Power control for WIC Sleep

Reserved

TXD0

RXD1

TXD1

CTS1

RTS1

UART2

RXD2

TXD2

CTS2

RTS2

DMIC0

DMIC1

DMCKO0

DMDIN0

DMCKO1

DMDIN1

WICPOWERDOWN

Reserved

OSC

Reserved

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31

LC823455

Boot Mode

The available boot modes are determined by the values on

the BMODE[1:0] terminal.

Table 13. BOOT MODE

IPL mode

BMODE1

BMODE0

Explanation

Physical

Boot

PD

Internal ROM boot (EMMC Physical Boot with USB download)

(SD card I/F Ch0 + USB Device + EXTINT2F)

470 kꢀ

USB

IPL2 is transferred to boot partition1 area of eMMC via USB from PC.

Using Boot operation mode of eMMC, IPL2(program) is copied to internal SRAM

from boot partition1 area of eMMC connected to SDCH0 and is executed.

XT1 must be connected in this mode to boot the ROM.

The connection of XTRTC is arbitrary.

Physical

Boot

PD

PU

Internal ROM boot (EMMC Physical Boot with SD Ch1 download)

(SD card I/F Ch0 + SD card I/F Ch1 + EXTINT2F)

470 kꢀ

SD

IPL2 is transferred to boot partition1 area of eMMC from SDCH1.

Using Boot operation mode of eMMC, IPL2(program) is copied to internal SRAM

from boot partition1 area of eMMC connected to SDCH0 and is executed.

Either XT1 or XTRTC is required to boot the ROM.

User Area

Boot

PD

PU or PD

Internal ROM boot (User Area Boot with USB download)

(SD card I/F Ch0 + USB Device + EXTINT2F)

1 kꢀ

470 kꢀ

USB

IPL2 is transferred to user area of eMMC via USB from PC.

IPL2(program) is copied to internal SRAM from user area of eMMC connected to

SDCH0 and is executed.

XT1 must be connected in this mode to boot the ROM.

The connection of XTRTC is arbitrary.

User Area

Boot

PU

PD

Internal ROM boot (User Area Boot with SD Ch1 download)

(SD card I/F Ch0 + SD card I/F Ch1 + EXTINT2F)

470 kꢀ

1 kꢀ

SD

IPL2 is transferred to user area of eMMC from SDCH1.

IPL2(program) is copied to internal SRAM from user area of eMMC connected to

SDCH0 and is executed.

Either XT1 or XTRTC is required to boot the ROM.

SPI Boot

USB

PU

Internal ROM boot (External Serial Flash SPI Boot with USB download)

(S−FLASH I/F + USB Device + EXTINT2F )

470 kꢀ

IPL2 is transferred to user area of S−FLASH via USB from PC.

IPL2(program) is copied to internal SRAM from user area of S−FLASH and is

executed.

XT1 must be connected in this mode to boot the ROM.

The connection of XTRTC is arbitrary.

SPI Boot

SD

PD

PU

Internal ROM boot (External Serial Flash SPI Boot with SD Ch1 download)

(S−FLASH I/F + SDcard I/F Ch1 + EXTINT2F)

470 kꢀ

1 kꢀ

IPL2 is transferred to user area of S−FLASH from SDCH1.

IPL2(program) is copied to internal SRAM from user area of S−FLASH and is

executed.

Either XT1 or XTRTC is required to boot the ROM.

QSPI Boot

USB

PU

Internal ROM boot

1 kꢀ

470 kꢀ

(External Serial Flash QSPI Boot with USB download)

(S−Flash I/F(QSPI) + USB Device + EXTINT2F)

The IPL supports the direct write of the program using the DD command from USB.

In this mode, the CPU fetches Serial Flash connected to S/Flash IF directly.

XT1 must be connected in this mode to boot the ROM.

The connection of XTRTC is arbitrary.

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LC823455

Table 13. BOOT MODE (continued)

IPL mode

BMODE1

BMODE0

Explanation

QSPI Boot

SD

PU

PD

Internal ROM boot

1 kꢀ

470 kꢀ

(External Serial Flash QSPI Boot with SD Ch1 download)

(S−Flash I/F(QSPI) + SD card I/F Ch1 + EXTINT2F)

IPL2 is transferred to S−FLASH from SDCH1.

In this mode, the CPU fetches from Serial Flash connected to S/Flash IF directly.

Either XT1 or XTRTC is required to boot the ROM.

User Area

Delete

PD

PU

Internal ROM boot (User Area IPL2 deletion)

( SD card I/F Ch0 + EXTINT2F)

1 kꢀ

It comes to be able to write IPL2 again at User Area Boot.

Either XT1 or XTRTC is necessary to boot the ROM.

Partition

Delete

PD

Internal ROM boot (Partition Area IPL2 deletion)

(SD card I/F Ch0 + EXTINT2F)

470 kꢀ

1 kꢀ

It comes to be able to write IPL2 again at eMMC Physical Boot.

Either XT1 or XTRTC is necessary to boot the ROM.

SPI All

Erase

PU

Internal ROM boot (All external Serial Flash SPI area deletion)

( S−Flash I/F, + EXTINT2F )

470 kꢀ

1 kꢀ

All of Serial Flash is deleted.

Please select it when you use Serial Flash with SPI.

Either XT1 or XTRTC is required to boot the ROM.

SDCH0 All

Erase

PD

Internal ROM boot (All area deletion )

(SD card I/F Ch0 + EXTINT2F)

1 kꢀ

All of eMMC is deleted. The partition area is also erased, which takes time. When

eMMC corresponds to Trim, Trim is done.

Either XT1 or XTRTC is required to boot the ROM.

QSPI All

Erase

PU

PD

Internal ROM boot (All external Serial Flash QSPI area deletion)

(S−Flash I/F(QSPI) + EXTINT2F)

1 kꢀ

All of Serial Flash is deleted.

Please use it when you use Serial Flash in the fetch mode of QSPI.

Either XT1 or XTRTC is required to boot the ROM.

External

PU

PD

External memory boot (External−0)

ROM Boot

470 kꢀ

In this mode, the CPU fetches external memory connected by the external memory

controller of External0 directly.

Either XT1 or XTRTC is required to boot the ROM.

Hi−z

PU

External memory I/F terminal are Hiz

EXA[20:1], EXD[15:0], NCS[1:0], NRD, NWRENWRL, NHBNWRH, NLBEXA0

SD card I/F Ch0 terminal are Hiz

1 kꢀ

SDCLK0, SDCMD0, SDAT0[3:0]

S−Flash(QSPI) terminal are Hiz

SFQSCS, SFCK, SFDI(QIO0), SFDO(QIO1), SFWP(QIO2), SFHOLD(QIO3)

Either XT1 or XTRTC is required to boot the ROM.

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LC823455

Boot Port

The ports used while booting are described below.

• SPI Boot / SPI All Erase uses only SFCK, SFDO, SFDI

and SFQSCS switched from TIOCB01. SFHOLD and

SFWP (The function is different according to the

device) are not used

• There is no dedicated SDCH0 pin in the WLP package.

Therefore, when booting from eMMC, the terminals

SFCK, SFQSCS, SFDO, SFDI, SFWP, and SFHOLD

must be switched to SDCLK0, SDCMD0, SDAT00,

SDAT01, SDAT02, and SDAT03. The target is Physical

Boot USB · Physical Boot SD · User Area Boot USB ·

User Area Boot SD · User Area Delete, Partition

Delete, SDCH 0 All Erase

• QSPI Boot / QSPI All Erase uses SFCK, SFDO, SFDI,

SFHOLD, SFWP and SFQSCS switched from

TIOCB01

• External ROM boot uses NCS0 and other terminals

required by the external memory controller. It is

available to packages in which the terminals of external

memory controller are assigned.

• SD Card SDCH1 uses only CMD, DATA, and CLK.

The terminals CD and WP are not used. These three

terminals are controlled only when writing IPL2 from

SDCH1

Table 14. GPIOs USED DURING IPL

(RA and RB are under planning.)

SDCH0

Shared (for XA)

P2F(error notification)

Dedicated (for RA)

Dedicated (for RB)

IPL mode

Physical Boot USB

P2F(error notification)

P0D(SDCLK0), P0E(SDAT00), P0F(SDAT01),

P11(SDAT02), P12(SDAT03), P03(SCMD0)

Physical Boot SD

P2F(error notification),

P22(SDCLK1), P23(SDCMD1), P24(SDDATA10),

P25(SDDATA11), P26(SDDATA12),

P27(SDDATA13), P0D(SDCLK0), P0E(SDAT00),

P0F(SDAT01), P11(SDAT02), P12(SDAT03)

P03(SCMD0)

P22(SDCLK1), P23(SDCMD1),

P24(SDDATA10), P25(SDDATA11),

P26(SDDATA12), P27(SDDATA13)

User Area Boot USB

User Area Boot SD

P2F(error notification),

P2F(error notification)

P0D(SDCLK0), P0E(SDAT00), P0F(SDAT01),

P11(SDAT02), P12(SDAT03), P03(SCMD0)

P2F(error notification)

P2F(error notification),

P0D(SDCLK0), P0E(SDAT00), P0F(SDAT01),

P11(SDAT02), P12(SDAT03), P03(SCMD0),

P22(SDCLK1), P23(SDCMD1), P24(SDDATA10),

P25(SDDATA11),

P22(SDCLK1), P23(SDCMD1),

P24(SDDATA10), P25(SDDATA11),

P26(SDDATA12), P27(SDDATA13)

SPI Boot USB

SPI Boot SD

P2F(error notification)

P2F(error notification),

P0D(SFCK), P03(SFQSCS), P0F(SFDO),

P0E(SFDI)

P0D(SFCK), P03(SFQSCS), P0F(SFDO), P0E(SFDI)

P2F(error notification),

P0D(SFCK), P03(SFQSCS) P0F(SFDO),

P0E(SFDI), P22(SDCLK1), P23(SDCMD1),

P24(SDDATA10), P25(SDDATA11),

P26(SDDATA12), P27(SDDATA13)

P0D(SFCK), P03(SFQSCS) P0F(SFDO), P0E(SFDI),

P22(SDCLK1), P23(SDCMD1), P24(SDDATA10),

P25(SDDATA11),

P26(SDDATA12), P27(SDDATA13)

QSPI Boot USB

QSPI Boot SD

P2F(error notification),

P0D(SFCK), P03(SFQSCS), P0F(SFDO),

P0E(SFDI), P11(SFWP), P12(SFHOLD)

P0D(SFCK), P03(SFQSCS), P0F(SFDO), P0E(SFDI),

P11(SFWP), P12(SFHOLD)

P2F(error notification)

P0D(SFCK), P03(SFQSCS), P0F(SFDO),

P0E(SFDI), P011(SFWP), P12(SFHOLD),

P22(SDCLK1), P23(SDCMD1), P24(SDDATA10),

P25(SDDATA11), P26(SDDATA12),

P27(SDDATA13)

P0D(SFCK), P03(SFQSCS), P0F(SFDO), P0E(SFDI),

P011(SFWP), P12(SFHOLD), P22(SDCLK1), P23(SD-

CMD1),

P24(SDDATA10), P25(SDDATA11),

P26(SDDATA12), P27(SDDATA13)

UserArea Delete

P2F(error notification),

P2F(error notification)

P0D(SDCLK0), P0E(SDAT00), P0F(SDAT01),

P11(SDAT02), P12(SDAT03), P03(SCMD0)

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LC823455

Table 14. GPIOs USED DURING IPL (continued)

(RA and RB are under planning.)

SDCH0

Dedicated (for RA)

Shared (for XA)

P2F(error notification),

Dedicated (for RB)

IPL mode

Partition Delete

P2F(error notification)

P0D(SDCLK0), P0E(SDAT00), P0F(SDAT01),

P11(SDAT02), P12(SDAT03), P03(SCMD0)

SPI Erase

P2F(error notification),

P0D(SFCK), P03(SFQSCS), P0F(SPIOUT),

P0E(SFDI)

P0D(SFCK), P03(SFQSCS), P0F(SPIOUT), P0E(SFDI)

P2F(error notification)

SDCH0 All Erase

QSPI All Erase

External ROM Boot

P2F(error notification),

P0D(SDCLK0), P0E(SDAT00), P0F(SDAT01),

P11(SDAT02), P12(SDAT03), P03(SCMD0)

P2F(error notification),

P0D(SFCK), P03(SFQSCS), P0F(SFDO),

P0E(SFDI), P11(SFWP), P12(SFHOLD)

P0D(SFCK), P03(SFQSCS), P0F(SFDO), P0E(SFDI),

P11(SFWP), P12(SFHOLD)

N/A

P06(NCS0), P17(NRD),

P30(NWRENWRL)

N/A

P31(NHBNWRH),

P16(NLBEXA0),

P32(EXA01), P33(EXA02),

P34(EXA03), P35(EXA06),

P36(EXA05), P37(EXA06),

P38(EXA07), P39(EXA08),

P3A(EXA09), P3B(EXA10),

P3C(EXA11), P3D(EXA12),

P3E(EXA13), P3F(EXA14),

P40(EXA15), P41(EXA16),

P42(EXA17), P43(EXA18),

P44(EXA19), P45(EXA20),

P46(EXD00), P47(EXD01),

P48(EXD02), P49(EXD03),

P4A(EXD04), P4B(EXD05),

P4C(EXD06), P4D(EXD07),

P4E(EXD08), P4F(EXD09),

P50(EXD10), P51(EXD11),

P52(EXD12), P53(EXD13),

P54(EXD14), P55(EXD15)

HI−z

SDCLK0 is set to the Hi−z input.

7. In this table, “Pxx” means “GPIOxx”. For example “P2F” means “GPIO2F”.

SDIF PullUp

If using the SDIF port during boot mode, internal PullUp

resistors are used (SDCMD0, SDAT0[3:0] / SDCMD1,

SDAT1[3:0]). Therefore, external PullUp resistors are not

required on the board.

termination of USB connection, as well as error notification

with High/Low of the terminal.

When errors occur during boot sequences, for example

writing of IPL2, GPIO2F reports the sort of error. Moreover,

GPIO2F can indicate the status of USB connection and the

completion of USB file transfer. Additionally, Delete Mode,

completion of Erase, and status of Erase can also be reported

through a sequence of Low/High.

For more detail about the behavior of this port used during

boot, refer to the “IPL detail” chapter in the “LC823455

Sample Software Reference”.

SFQSCS PullUp

If using SFQSCS during boot mode, the initial condition

for terminal P03 relative to SFQSCS is Pull−Up. After

terminal P03 is switched to SFQSCS, the Pull−Up is

released.

GPIO2F

During boot mode, GPIO2F provides notification of the

beginning of USB connection, notification of the

www.onsemi.com

35

LC823455

PIN ASSIGNMENT

Table 15. PIN ASSIGNMENT

I/O

I

Input

Output

O

B

P

G

Bidirectional

Power

Ground

XA: Package Code = “XA”, RA: Package Code = “RA”, RB: Package Code = “RB”, (RA and RB are under planning).

Table 16.

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

M13

N14

M12

No.

Ball

−

No.

Ball

−

Circuit Type

PIN NAME

Vdd2

I/O

P

Drive

PU/PD

1

2

3

−

Vss2

G

−

EXD0/

GPIO46/

EXTINT46

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

4

5

6

7

8

M14

L13

L14

K11

K13

−

EXA1/

GPIO32/

EXTINT32

O/

B/

I

3ISD/3T2

(4)(8)

EXA11/

GPIO3C/

EXTINT3C

O/

B/

I

3ISD/3T2

(4)(8)

EXA12/

GPIO3D/

EXTINT3D

O/

B/

I

3ISD/3T2

(4)(8)

EXA13/

GPIO3E/

EXTINT3E

O/

B/

I

3ISD/3T2

(4)(8)

EXA14/

GPIO3F/

EXTINT3F

O/

B/

I

3ISD/3T2

(4)(8)

9

R15

R16

1

2

R15

R16

1

2

L10

H8

Vdd1

P

10

NRD/

GPIO17/

EXTINT17

O/

B/

I

Schmitt

3−State

2/4/8 mA

2 mA

PD

PU

Vdd2

3ISD/3T2

(4)(8)

11

P15

3

P15

3

K9

SWDIO/

DMDIN0B/

GPIO59/

B/

I/

B/

I

3ISU/3T2

EXTINT59

12

13

14

P16

K14

J10

4

−

P16

−

4

−

G7

−

NLBEXA0/

GPIO16/

EXTINT16

O/

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

EXD2/

GPIO48/

EXTINT48

B/

I

3ISD/3T2

(4)(8)

−

EXA2/

GPIO33/

EXTINT33

O/

B/

I

3ISD/3T2

(4)(8)

15

16

N15

J11

5

−

N15

−

5

−

L9

−

Vss2

G

EXA6/

GPIO37/

EXTINT37

O/

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

17

18

J13

J14

−

EXA7/

GPIO38/

EXTINT38

O/

B/

I

3ISD/3T2

(4)(8)

SDRADDR12/

GPIO2A/

EXTINT2A

O/

B/

I

PU/PD

3ISUD/3T2

(4)(8)

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36

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

No.

Ball

No.

Ball

Circuit Type

PIN NAME

I/O

Drive

PU/PD

19

20

N16

6

7

N16

6

J8

TDI/

SDCD1/

SWO/

GPIO20/

EXTINT20

I/

O/

B/

I

Schmitt

3−State

2 mA

PU/PD

VddSD1

3ISUD/3T2

M15

7

K8

TDO/

O/

I/

B/

I

Schmitt

3−State

2 mA

PU/PD

VddSD1

3ISUD/3T2

SDWP1/

GPIO21/

EXTINT21

21

22

M16

L15

8

9

M16

L15

8

9

L8

VddSD1

P

H7

SDCMD1/

GPIO23/

EXTINT23

B/

I

CMOS

3−State

2/4/8/10

mA

PU/PD

VddSD1

3ICUD/3T2

(4)(8)(10)

23

24

L16

K12

10

11

L16

K12

10

11

J7

SDAT10/

GPIO24/

EXTINT24

B/

I

2/4/8/10mA

3ICUD/3T2

(4)(8)(10)

K7

SDAT11/

GPIO25/

EXTINT25

B/

I

3ICUD/3T2

(4)(8)(10)

25

26

J15

12

13

J15

12

13

L7

F5

Vss2

G

K16

SDAT12/

GPIO26/

EXTINT26

B/

I

CMOS

3−State

2/4/8/10mA

PU/PD

VddSD1

3ICUD/3T2

(4)(8)(10)

27

28

J12

14

15

J12

14

15

G6

H6

SDAT13/

GPIO27/

EXTINT27

B/

I

3ICUD/3T2

(4)(8)(10)

K15

SDCLK1/

GPIO22/

EXTINT22

O/

B/

I

3ICUD/3T2

(4)(8)(10)

29

30

31

32

33

34

35

36

37

38

J16

H12

H15

H16

G15

G16

H13

F15

F16

E16

16

17

18

19

20

21

−

J16

H12

H15

H16

G15

G16

−

16

−

L6

−

Vss1

RTCMODE

VddRTC

XIN32K

G

I

CMOS

X

−

VddRTC

1IC

X

17

18

19

20

−

K6

J5

K5

L5

−

P

I

VssRTC

XOUT32K

Keyint2

G

O

I

−

X

−

PD

−

VddRTC

X

CMOS

−

1ICD

1IC

22

23

24

F15

F16

E16

−

BACKUPB

VDET

I

−

21

22

J6

H5

I

−

1IC

RTCINT (Note

8)

O

OD

0.3 mA−OD

−

OD3

39

40

41

42

43

44

45

46

47

48

49

50

51

G12

E15

F12

D15

D14

D16

C15

C14

C16

E13

E14

D13

H10

25

26

27

28

−

G12

E15

F12

D15

−

23

24

25

26

−

G5

H4

L4

K4

−

Keyint0

TEST

I

CMOS

−

PD

−

VddRTC

1ICD

1IC

I

Keyint1

AVddPLL1

VCNT1

AVssPLL1

AVddPLL2

VCNT2

AVssPLL2

Vss1

I

PD

1ICD

P

O

G

P

O

G

P

G

−

1A

−

AVddPLL1

AVddPLL2

1A

29

30

−

D16

C15

−

27

28

−

J4

K3

−

31

−

C16

−

29

−

L3

−

Vdd2

−

Vss2

−

EXD4/

GPIO4A/

EXTINT4A

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

52

H11

−

EXD5/

GPIO4B/

EXTINT4B

B/

I

3ISD/3T2

(4)(8)

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37

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

B15

H14

No.

Ball

B15

−

No.

Ball

L2

−

Circuit Type

PIN NAME

I/O

Drive

PU/PD

PD

53

54

32

−

30

−

Vdd1

P

EXD6/

GPIO4C/

EXTINT4C

B/

I

Schmitt

3−State

2/4/8 mA

Vdd2

3ISD/3T2

(4)(8)

55

56

57

58

G10

G11

G13

G14

−

EXA19/

GPIO44/

EXTINT44

O/

B/

I

PD

3ISD/3T2

(4)(8)

EXA20/

GPIO45/

EXTINT45

O/

B/

I

PD

3ISD/3T2

(4)(8)

EXD7/

GPIO4D/

EXTINT4D

B/

I

PD

3ISD/3T2

(4)(8)

EXD8/

GPIO4E/

EXTINT4E

B/

I

PD

3ISD/3T2

(4)(8)

59

60

B14

F14

33

−

B14

−

31

−

L1

−

Vss1

G

EXD11/

GPIO51/

EXTINT51

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

61

62

63

F13

D12

F11

−

EXD12/

GPIO52/

EXTINT52

B/

I

3ISD/3T2

(4)(8)

EXD13/

GPIO53/

EXTINT53

B/

I

3ISD/3T2

(4)(8)

EXD14/

GPIO54/

EXTINT54

B/

I

3ISD/3T2

(4)(8)

64

65

C13

A16

−

Vss2

G

34

A16

32

K2

DOUT1/

GPIO15/

EXTINT15

O/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

PD

Vdd2

3ISUD/3T2

(4)(8)

66

67

D11

F10

−

EXD9/

GPIO4F/

EXTINT4F

B/

I

3ISD/3T2

(4)(8)

EXD10/

GPIO50/

EXTINT50

B/

I

PD

3ISD/3T2

(4)(8)

68

69

B16

D10

35

−

B16

−

33

−

K1

−

Vdd2

P

EXD15/

GPIO55/

EXTINT55

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

70

71

A15

A14

36

37

A15

A14

34

35

J3

BCK1/

GPIO13/

EXTINT13

B/

I

PU/PD

3ISUD/3T2

(4)(8)

G4

MCLK0/

MCLK1/

GPIO18/

EXTINT18

B/

I

3ISUD/3T2

(4)(8)

72

A13

38

A13

36

J2

LRCK1/

GPIO14/

EXTINT14

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

73

74

75

B13

C11

B12

39

−

B13

−

37

−

J1

−

Vss2

Vdd2

G

P

40

B12

38

H3

BCK0/

DMCKO0B/

GPIO19/

B/

O/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

EXTINT19

76

77

A12

B11

41

42

A12

B11

39

40

G3

H2

LRCK0/

DMDIN0B/

GPIO1A/

B/

I/

B/

I

3ISUD/3T2

(4)(8)

EXTINT1A

DIN0/

I/

B/

I

3ISUD/3T2

(4)(8)

DMDIN0A/

GPIO1B/

EXTINT1B

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38

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

C12

G9

No.

Ball

−

No.

Ball

−

Circuit Type

PIN NAME

Vss2

I/O

G

Drive

PU/PD

78

79

−

XTALINFO1

B

Schmitt

3−State

2/4/8 mA

PU

Vdd2

3ISU/3T2

(4)(8)

80

81

C10

A11

−

Vdd2

P

43

A11

41

H1

DOUT0/

DMCKO0A

GPIO1C/

O/

B/

I

3−State

2/4/8 mA

PU/PD

3ISUD/3T2

(4)(8)

EXTINT1C

82

83

84

85

A10

B10

F9

44

45

−

A10

B10

−

42

43

−

F4

F3

−

BMODE0

BMODE1

B

O

Schmitt

−

3−State

2 mA

PU/PD

−

Vdd2

3ISUD/3T2

3T2(4)(8)

SDRADDR1

2/4/8 mA

D9

−

EXA4/

DOUT1/

GPIO35/

EXTINT35

O/

B/

I

Schmitt

PD

3ISD/3T2

(4)(8)

86

87

88

89

C9

B9

A9

A8

−

SDRADDR0

NRES

O

I

−

3−State

−

2/4/8 mA

−

Vdd2

3T2(4)(8)

3IS

46

47

48

B9

A9

A8

44

45

46

G1

G2

F1

Schmitt

AVssDAMPR

G

ROUT/

GPROUT

O/

O

−

1A

−

AVddDAMPR

AVddDAMPL

1A

90

91

92

A7

A6

A5

49

50

51

A7

A6

A5

47

48

49

F2

E2

E1

AVddDAMPR

AVddDAMPL

P

LOUT/

GPLOUT

O/

O

93

94

95

96

97

A4

B8

52

53

−

A4

B8

−

50

51

−

D2

D1

−

AVssDAMPL

Vss1

G

O

G8

D8

SDRADDR2

SDRADDR3

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

−

E12

54

E12

52

E3

SCL1/

GPIO2B/

EXTINT2B

O/

B/

I

Schmitt

PU/PD

3ISUD/3T2

(4)(8)

98

99

E11

E10

55

56

E11

E10

53

54

E4

D3

SDA1/

GPIO2C/

EXTINT2C

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

SDRADDR11/

DMCKO0A/

GPIO2D/

O/

B/

I

3ISUD/3T2

(4)(8)

EXTINT2D

100

C8

−

SDRDATA0

B

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

101

102

B7

C7

57

−

B7

−

55

−

C1

−

Vdd1

P

B

SDRDATA1

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

103

104

105

E9

E8

E7

58

59

60

E9

E8

E7

56

57

58

C2

D4

C3

TCLKA0/

BCK1/

GPIO00/

EXTINT00

I/

B/

I

Schmitt

PU/PD

3ISUD/3T2

(4)(8)

TCLKB0/

LRCK1/

GPIO01/

EXTINT01

I/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

PD

Vdd2

3ISUD/3T2

(4)(8)

NHBNWRH/

TXD0/

DOUT0/

GPIO31/

EXTINT31

O/

B/

I

3ISD/3T2

(4)(8)

106

107

108

C6

B5

D7

−

61

−

B5

−

59

−

B1

−

Vdd2

Vss2

P

G

B

PSM_DAT2

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

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39

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

No.

Ball

No.

Ball

Circuit Type

PIN NAME

I/O

Drive

PU/PD

109

D6

−

PSM_SDO

(DAT1)

O(B)

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

110

D5

−

PSM_DAT3

B

CMOS

3−State

2/4/8/10 mA

PU/PD

3ICUD/3T2

(4)(8)(10)

111

112

C5

C4

−

SDRADDR4

SDRDATA4

O

B

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

CMOS

PD

3ICD/3T2

(4)(8)

113

C3

−

SDRDATA14

B

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

114

115

116

B6

D4

D3

62

−

B6

−

60

−

A1

−

Vdd2

P

B

−

SDRDATA2

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

117

118

119

120

121

E4

E3

F7

F6

F8

−

SDRDATA3

B

3ICD/3T2

(4)(8)

SDRDATA15

2/4/8 mA

PD

3ICD/3T2

(4)(8)

PSM_SDI

(DAT0)

I(B)

O

2/4/8/10 mA

2/4/8/10mA

2/4/8/10 mA

PU/PD

3ICUD/3T2

(4)(8)(10)

PSM_CS

3ICUD/3T2

(4)(8)(10)

PSM_SCK

O

3ICUD/3T2

(4)(8)(10)

122

123

F4

F3

−

SDRADDR7

SDRDATA5

O

B

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

CMOS

PD

3ICD/3T2

(4)(8)

124

G7

−

SDRDATA13

Vss2

B

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

125

126

B4

A2

63

64

B4

A2

61

62

A2

B2

G

EXTINT2E/GP

IO2E

I/B

Schmitt

3−State

2/4/8 mA

PU/PD

PU

Vdd2

3ISUD/3T2

(4)(8)

127

A1

65

A1

63

B3

NCS1/

RXD0/

GPIO10/

EXTINT10

O/

I/

B/

I

3ISU/3T2

(4)(8)

128

129

130

G6

G4

G3

−

SDRDATA12

SDRDATA6

SDRDATA7

B

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

3ICD/3T2

(4)(8)

3ICD/3T2

(4)(8)

131

132

B3

H7

66

−

B3

−

64

−

A3

−

Vss1

G

B

SDRDATA8

CMOS

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

133

134

B2

B1

67

68

B2

B1

65

66

C4

B4

EXTINT2F/

GPIO2F

I/

B

PU/PD

3ISUD/3T2

(4)(8)

TCK/

I/

B/

I

3ISUD/3T2

(4)(8)

SDCD2/

GPIO29/

EXTINT29

135

H6

−

SDRDATA9

B

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

136

137

A3

H4

69

−

A3

−

67

−

A4

−

Vdd2

P

B

SDRDATA11

3ICD/3T2

(4)(8)

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40

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

No.

Ball

No.

Ball

Circuit Type

PIN NAME

I/O

Drive

PU/PD

138

H3

−

SDRDATA10

B

CMOS

3−State

2/4/8 mA

PD

Vdd2

3ICD/3T2

(4)(8)

139

C2

70

C2

68

D5

TIOCA01/

SDCMD2/

PHI1/

GPIO0A/

EXTINT0A

B/

O/

B/

I

CMOS

3−State

2/4/8/10 mA

PU/PD

3ICUD/3T2

(4)(8)(10)

140

141

C1

D2

71

72

C1

D2

69

70

C5

B5

TXD1/

SDAT20/

GPIO04/

EXTINT04

O/

B/

I

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

RXD1/

SDAT21/

GPIO05/

EXTINT05

I/

B/

I

3ICUD/3T2

(4)(8)(10)

142

143

144

J7

D1

E6

−

Vss2

Vdd1

G

P

73

74

D1

E6

71

72

A5

E5

CTS1/

SDAT22/

RXD0/

GPIO56/

EXTINT56

I/

B/

I/

B/

I

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

145

146

E5

E2

75

76

E5

E2

73

74

C6

B6

RTS1/

SDAT23/

TXD0/

GPIO57/

EXTINT57

O/

B/

O/

B/

I

3ICUD/3T2

(4)(8)(10)

TIOCA00/

SDCLK2/

PHI0/

GPIO09/

EXTINT09

B/

O/

B/

I

3ICUD/3T2

(4)(8)(10)

147

148

149

150

151

J6

J4

J3

H9

E1

−

SDRADDR5

SDRADDR6

SDRADDR9

Vdd2

O

P

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

−

77

78

H9

E1

75

76

A6

D6

TMS/

I/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

SDWP2/

GPIO28/

EXTINT28

152

153

F5

F2

79

80

F5

F2

77

78

E6

D7

TXD2/

O/

B/

I

3ISUD/3T2

(4)(8)

TIOCA10/

GPIO0B/

EXTINT0B

RXD2/

I/

B/

I

3ISUD/3T2

(4)(8)

TIOCA11/

GPIO0C/

EXTINT0C

154

155

156

157

158

K6

K4

F1

K3

G5

−

SDRBA1

SDRBA0

Vss2

O

G

O

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

81

−

F1

−

79

−

A7

−

SDRADDR10

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

82

G5

80

B7

SFCK/

GPIO0D/

EXTINT0D/

SDCLK0

O/

B/

I/

CMOS

2/4/8/10 mA

PU/PD

3ICUD/3T2

(4)(8)(10)

O

159

160

G2

G1

83

84

G2

G1

81

82

C7

E7

TIOCB01/

SFQSCS/

GPIO03/

EXTINT03/

SDCMD0

B/

O/

B/

I/

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

B

SFDO(QIO1)/

GPIO0F/

EXTINT0F/

SDAT01

O(B)/

B/

I/

CMOS

3−State

2/4/8/10 mA

2/4/8 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

B

161

162

L4

−

SDRRAS

Vdd2

O

P

−

3T2(4)(8)

H8

85

H8

83

A8

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41

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

No.

Ball

No.

Ball

Circuit Type

PIN NAME

I/O

Drive

PU/PD

163

164

165

H5

86

87

88

H5

84

85

86

B8

SFDI(QIO0)/

GPIO0E/

EXTINT0E/

SDAT00

I(B)/

B/

I/

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

B

H2

H1

H2

H1

C8

D8

SFWP(QIO2)/

GPIO11/

EXTINT11/

SDAT02

O(B)/

B/

I/

3−State

2/4/8/10 mA

PU/PD

3ICUD/3T2

(4)(8)(10)

B

SFHOLD(QIO

3)/

GPIO12/

EXTINT12/

SDAT03

O(B)/

B/

I/

3ICUD/3T2

(4)(8)(10)

B

166

167

168

169

L2

L3

M5

J5

89

−

L2

−

87

−

A9

−

Vss1

G

O

SDRWE

SDRCKE

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

−

90

J5

88

B9

TIOCB00/

DIN1/

DMDIN0A/

GPIO02/

EXTINT02

B/

I/

B/

I

Schmitt

PU/PD

3ISUD/3T2

(4)(8)

170

171

172

173

174

M4

M3

M2

N3

J2

−

SDRCLK

SDRCS

IO18V

O

I

−

3−State

−

2/4/8/10 mA

2/4/8 mA

−

Vdd2

Vdd1

3T2(4)(8)(10)

3T2(4)(8)

1A

91

−

M2

−

89

−

A10

−

1A

Vss1

G

B

92

J2

−

SDAT02

CMOS

3−State

2/4/8/10 mA

PU/PD

Vdd2

3ICUD/3T2

(4)(8)(10)

175

176

J1

93

94

J1

−

SDAT03

SDAT01

B

3ICUD/3T2

(4)(8)(10)

K5

3ICUD/3T2

(4)(8)(10)

177

178

179

180

181

K2

L1

95

96

97

−

K2

L1

M1

−

Vdd2

Vss2

P

G

P

O

B

M1

M6

K1

90

−

A11

−

Vdd1

SDRDQM1

SDAT00

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

98

K1

−

CMOS

2/4/8/10 mA

PU/PD

3ICUD/3T2

(4)(8)(10)

182

183

L6

L5

99

L6

L5

−

SDCLK0

SDCMD0

O

B

−

3−State

2/4/8/10 mA

−

Vdd2

3T2(4)(8)(10)

100

CMOS

PU/PD

3ICUD/3T2

(4)(8)(10)

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

K7

M7

N5

N4

N1

P1

R1

N2

P2

R2

P3

R3

P4

R4

P5

−

SDRADDR8

SDRCAS

Vdd2

O

P

G

I

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

−

Vss2

101

102

103

104

105

106

107

108

109

110

111

N1

P1

R1

N2

P2

R2

P3

R3

P4

R4

P5

91

92

93

94

−

B11

B10

C9

C11

−

SIN0

3A

−

AvddADC

3A

SIN1

I

SIN2

I

AVddADC

SIN3

P

I

3A

−

AvddADC

3A

−

SIN4

I

−

SIN5

I

−

SIN6

I

−

SIN7

I

95

96

C10

E8

AVssADC

AVssUSBPHY

G

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42

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

No.

Ball

No.

Ball

Circuit Type

PIN NAME

I/O

Drive

PU/PD

199

R5

112

R5

97

D11

B

3A

−

AVddUSBPHY

18

3A

USBEXT0

2

200

201

P6

R6

113

114

P6

R6

98

99

D9

AVddUSBPHY

2

P

B

D10

USBDM

3A

−

AVddUSBPHY

2

3A

202

203

P7

R7

115

116

P7

R7

100

101

E9

AVssUSBPHY

USBDP

G

B

E10

AVddUSBPHY

2

204

P8

117

P8

102

F8

DVddUSBPHY

1

P

205

206

R8

P9

118

119

R8

P9

103

104

F9

I

−

USBVBUS

F10

AVddUSBPHY

18

P

207

R9

120

R9

105

F11

B

3A

AVddUSBPHY

18

3A

USBID

208

209

210

211

212

213

214

215

R10

R11

P10

P11

N10

N9

121

122

123

124

−

R10

R11

P10

P11

−

106

107

108

109

−

G8

G9

G10

G11

−

VddXT1

XIN1

P

I

X

−

VddXT1

X

VssXT1

XOUT1

Vss1

G

O

G

P

B

X

−

Vdd1

N12

N6

−

Vdd2

−

XTALINFO0

Schmitt

3−State

2/4/8 mA

PU

Vdd2

3ISU/3T2

(4)(8)

216

217

N11

L7

−

Vss2

G

125

L7

110

F7

SDO0/

GPIO1F/

EXTINT1F

O/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

218

L8

126

L8

111

F6

SCK0/

GPIO1D/

EXTINT1D

B/

I

3ISUD/3T2

(4)(8)

219

220

N7

J8

−

SDRDQM0

O

−

3−State

2/4/8 mA

−

Vdd2

3T2(4)(8)

EXA15/

GPIO40/

EXTINT40

O/

B/

I

Schmitt

PD

3ISD/3T2

(4)(8)

221

222

R12

K8

127

−

R12

−

112

−

H11

−

Vdd1

P

EXA10/

GPIO3B/

EXTINT3B

O/

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

223

L12

128

L12

−

EXA3/

DIN1/

GPIO34/

EXTINT34

O/

I/

B/

I

3ISD/3T2

(4)(8)

224

225

226

227

M8

N8

J9

−

EXA17/

GPIO42/

EXTINT42

O/

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

EXD3/

GPIO49/

EXTINT49

B/

I

3ISD/3T2

(4)(8)

EXA16/

GPIO41/

EXTINT41

O/

B/

I

3ISD/3T2

(4)(8)

K9

EXA18/

GPIO43/

EXTINT43

O/

B/

I

3ISD/3T2

(4)(8)

228

229

P12

L9

129

130

P12

L9

113

114

J11

Vss2

G

H10

SCL0/

GPIO07/

EXTINT07

O/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

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43

LC823455

Table 16. (continued)

RA

RB

XA

BGA240

BGA136

WLP120

Input

Type

Output

Type

IO

Pwr Grp

IO

No.

Ball

No.

Ball

No.

Ball

Circuit Type

PIN NAME

I/O

Drive

PU/PD

230

231

232

233

L10

131

132

−

L10

115

116

−

J10

SDI0/

GPIO1E/

EXTINT1E

I/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

L11

M9

L11

−

H9

−

SDA0/

GPIO08/

EXTINT08

B/

I

3−State

2/4/8 mA

PU/PD

PD

3ISUD/3T2

(4)(8)

EXA9/

GPIO3A/

EXTINT3A

O/

B/

I

3ISD/3T2

(4)(8)

K10

−

NCS0/

GPIO06/

EXTINT06

O/

B/

I

PU

3ISU/3T2

(4)(8)

234

235

R13

M10

133

−

R13

−

117

−

K11

−

Vdd2

P

EXD1/

GPIO47/

EXTINT47

B/

I

Schmitt

3−State

2/4/8 mA

PD

Vdd2

3ISD/3T2

(4)(8)

236

237

238

M11

N13

P14

−

EXA5/

GPIO36/

EXTINT36

O/

B/

I

3ISD/3T2

(4)(8)

EXA8/

GPIO39/

EXTINT39

O/

B/

I

3ISD/3T2

(4)(8)

134

P14

118

J9

NWRENWRL/

DIN0/

GPIO30/

O/

I/

B/

I

3ISD/3T2

(4)(8)

EXTINT30

239

240

R14

P13

135

136

R14

P13

119

120

K10

L11

SWDCLK/

DMCKO0B

GPIO58/

I/

O/

B/

I

Schmitt

3−State

2/4/8 mA

PU/PD

Vdd2

3ISUD/3T2

(4)(8)

EXTINT58

Vss1

G

8. RTCINT (open drain Output) 3.6 V tolerant.

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44

LC823455

INPUT/OUTPUT CIRCUIT

Attribute : 3IS

VddIO (Note 9)

PAD

Vss

Attribute : 1IC

Attribute : 1ICD

VddIO (Note 9)

PAD

Vss

Attribute : 3T2(4)(8)

2/4/8mA

Attribute : OD3

VddIO (Note 9)

PAD

Out/Hiz

Vss

Attribute : 3ICUD/3T2(4)(8)(10)

Attribute : 3ICD/3T2(4)(8)

VddIO (Note 9)

ON/OFF

DRVcnt

Out/Hiz

( Note 10)

(Note 10)

PAD

Out/Hiz

ON/OFF

Vss

Attribute : 3ISUD /3T2(4)(8)

VddIO (Note 9)

Attribute : 3ISUD /3T2

ON/OFF

VddIO (Note 9)

ON/OFF

DRVcnt

(Note 10)

PAD

Out/Hiz

ON/OFF

Vss

Level Shifter

Figure 6. Input/Output Circuit

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45

LC823455

Attribute : 3ISD/3T2(4)(8)

Attribute : 3ISU/3T2

VddIO (Note 9)

ON/OFF

DRVcnt

Out/Hiz

(Note 10)

PAD

Out/Hiz

ON/OFF

Vss

Attribute : 3ISU/3T2(4)(8)

VddIO (Note 9)

Attribute : 3A,1A

AVdd *

ON/OFF

DRVcnt

(Note 10)

PAD(Output)

PAD(Input)

PAD

Out/Hiz

AVss*

Vss

Attribute : X

Attribute : 3AA

VddXT 1/VddRTC

PAD(Input)

PAD(Output)

PAD(Input)

PAD(Output)

Vss

Level Shifter

9. Vdd2, VddSD1 (IO Pwr Grp of Pin Assignment).

AVss*

10.DRVcnt: 2/4/8 mA, 2/4/8/10 mA, etc. Drivability switch control signal.

Figure 6. Input/Output Circuit (continued)

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46

LC823455

XA: Package Code = “XA”, RA: Package Code = “RA”, RB: Package Code = “RB”, (RA and RB are under planning).

Table 17. TERMINAL STATE TABLE

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

(Note 12)

TCLKA0/

BCK1/

GPIO00/

EXTINT00

GPIO00

GPIO01

GPIO02

Hiz

D

TCLKB0/

LRCK1/

GPIO01/

EXTINT01

Hiz

TIOCB00/

DIN1/

D

DMDIN0A/

GPIO02/

EXTINT02/

TIOCB01/

SFQSCS/

GPIO03/

GPIO03

PU

PU (Note 13)

D

EXTINT03/

SDCMD0

TXD1/

SDAT20/

GPIO04/

EXTINT04

GPIO04

GPIO05

Hiz

D

RXD1/

SDAT21/

GPIO05/

EXTINT05

NCS0/

GPIO06/

EXTINT06

GPIO06

GPIO07

GPIO08

GPIO09

Hiz

D

SCL0/

GPIO07/

EXTINT07

D

SDA0/

GPIO08/

EXTINT08

TIOCA00/

SDCLK2/

PHI0/

D

GPIO09/

EXTINT09

TIOCA01/

SDCMD2/

PHI1/

GPIO0A

Hiz

D

GPIO0A/

EXTINT0A

TXD2/

GPIO0B

GPIO0C

GPIO0D

Hiz

TIOCA10/

GPIO0B/

EXTINT0B

D

RXD2/

TIOCA11/

GPIO0C/

EXTINT0C

SFCK/

GPIO0D/

EXTINT0D/

D

SDCLK0

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47

LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

(Note 12)

SFDI(QIO0)/

GPIO0E/

EXTINT0E/

SDAT00

GPIO0E

GPIO0F

GPIO10

GPIO11

GPIO12

Hiz

D

SFDO(QIO1)/

GPIO0F/

EXTINT0F/

SDAT01

Hiz

NCS1/

RXD0/

GPIO10/

EXTINT10

SFWP(QIO2)/

GPIO11/

EXTINT11

SDAT02

SFHOLD(QIO3)/

GPIO12/

EXTINT12

SDAT03

BCK1/

GPIO13/

EXTINT13

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

Hiz

D

LRCK1/

GPIO14/

EXTINT14

DOUT1/

GPIO15/

EXTINT15

NLBEXA0/

GPIO16/

EXTINT16

NRD/

GPIO17/

EXTINT17

MCLK0/

MCLK1/

D

GPIO18/

EXTINT18

BCK0/

DMCKO0B/

GPIO19/

GPIO19

GPIO1A

GPIO1B

GPIO1C

GPIO1D

Hiz

EXTINT19

LRCK0/

DMDIN0B/

GPIO1A/

EXTINT1A

DIN0/

DMDIN0A/

GPIO1B/

EXTINT1B

DOUT0/

DMCKO0A

GPIO1C/

D

EXTINT1C

SCK0/

GPIO1D/

EXTINT1D

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48

LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

(Note 12)

SDI0/

GPIO1E/

EXTINT1E

GPIO1E

GPIO1F

GPIO20

Hiz

D

SDO0/

GPIO1F/

EXTINT1F

Hiz

TDI/

SDCD1/

SWO/

GPIO20/

D

EXTINT20

TDO/

GPIO21

Hiz

SDWP1/

GPIO21/

EXTINT21

SDCLK1/

GPIO22/

EXTINT22

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

Hiz

D

SDCMD1/

GPIO23/

EXTINT23

SDAT10/

GPIO24/

EXTINT24

SDAT11/

GPIO25/

EXTINT25

SDAT12/

GPIO26/

EXTINT26

SDAT13/

GPIO27/

EXTINT27

TMS/

SDWP2/

GPIO28/

EXTINT28

D

TCK/

GPIO29

GPIO2A

Hiz

SDCD2/

GPIO29/

EXTINT29

SDRADDR12/

D

GPIO2A/

EXTINT2A

SCL1/

GPIO2B/

EXTINT2B

GPIO2B

GPIO2C

GPIO2D

Hiz

D

SDA1/

GPIO2C/

EXTINT2C

SDRADDR11/

DMCKO0A/

D

GPIO2D/

EXTINT2D

GPIO2E/

EXTINT2E

GPIO2E

Hiz

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LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

(Note 12)

GPIO2F/

EXTINT2F

GPIO2F

Hiz

Hiz (Note 14)

D

NWRENWRL/

DIN0/

GPIO30/

GPIO30

Hiz

EXTINT30

NHBNWRH/

TXD0/

GPIO31

Hiz

D

DOUT0/

GPIO31/

EXTINT31

EXA1/

GPIO32/

EXTINT32

GPIO32

GPIO33

GPIO34

Hiz

D

EXA2/

GPIO33/

EXTINT33

EXA3/

DIN1/

GPIO34/

EXTINT34

D

EXA4/

DOUT1/

GPIO35/

EXTINT35

GPIO35

Hiz

EXA5/

GPIO36/

EXTINT36

GPIO36

GPIO37

GPIO38

GPIO39

GPIO3A

GPIO3B

GPIO3C

GPIO3D

GPIO3E

GPIO3F

Hiz

D

EXA6/

GPIO37/

EXTINT37

EXA7/

GPIO38/

EXTINT38

EXA8/

GPIO39/

EXTINT39

EXA9/

GPIO3A/

EXTINT3A

EXA10/

GPIO3B/

EXTINT3B

EXA11/

GPIO3C/

EXTINT3C

EXA12/

GPIO3D/

EXTINT3D

EXA13/

GPIO3E/

EXTINT3E

EXA14/

GPIO3F/

EXTINT3F

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LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

(Note 12)

EXA15/

GPIO40/

EXTINT40

GPIO40

GPIO41

GPIO42

GPIO43

GPIO44

GPIO45

GPIO46

GPIO47

GPIO48

GPIO49

GPIO4A

GPIO4B

GPIO4C

GPIO4D

GPIO4E

GPIO4F

GPIO50

GPIO51

Hiz

D

EXA16/

GPIO41/

EXTINT41

Hiz

EXA17/

GPIO42/

EXTINT42

EXA18/

GPIO43/

EXTINT43

EXA19/

GPIO44/

EXTINT44

EXA20/

GPIO45/

EXTINT45

EXD0/

GPIO46/

EXTINT46

EXD1/

GPIO47/

EXTINT47

EXD2/

GPIO48/

EXTINT48

EXD3/

GPIO49/

EXTINT49

EXD4/

GPIO4A/

EXTINT4A

EXD5/

GPIO4B/

EXTINT4B

EXD6/

GPIO4C/

EXTINT4C

EXD7/

GPIO4D/

EXTINT4D

EXD8/

GPIO4E/

EXTINT4E

EXD9/

GPIO4F/

EXTINT4F

EXD10/

GPIO50/

EXTINT50

EXD11/

GPIO51/

EXTINT51

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LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

(Note 12)

EXD12/

GPIO52/

EXTINT52

GPIO52

GPIO53

GPIO54

GPIO55

GPIO56

Hiz

D

EXD13/

GPIO53/

EXTINT53

Hiz

EXD14/

GPIO54/

EXTINT54

EXD15/

GPIO55/

EXTINT55

CTS1/

SDAT22/

RXD0/

D

GPIO56/

EXTINT56

RTS1/

SDAT23/

TXD0/

GPIO57

Hiz

D

GPIO57/

EXTINT57

D

PSM_CS

PSM_SDI(DAT0)

PSM_SDO(DAT1)

PSM_DAT2

PSM_DAT3

PSM_SCK

SDAT00

PSM_CS

PSM_SDI(DAT0)

PSM_SDO(DAT1)

PSM_DAT2

PSM_DAT3

PSM_SCK

SDAT00

PD

D

Hiz

SDAT01

Hiz

SDAT02

Hiz

SDAT03

Hiz

SDCLK0

Low

Hiz

Low

Hiz

SDCMD0

SDRADDR0

SDRADDR1

SDRADDR10

SDRADDR2

SDRADDR3

SDRADDR4

SDRADDR5

SDRADDR6

SDRADDR7

SDRADDR8

SDRADDR9

SDRBA0

SDRADDR0

SDRADDR1

SDRADDR10

SDRADDR2

SDRADDR3

SDRADDR4

SDRADDR5

SDRADDR6

SDRADDR7

SDRADDR8

SDRADDR9

SDRBA0

Low

SDRBA1

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LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

SDRCAS

(Note 12)

High

Low

High

Hiz

D

SDRCAS

SDRCKE

High

Low

High

Hiz

SDRCKE

SDRCLK

SDRCS

SDRDATA0

SDRDATA1

SDRDATA10

SDRDATA11

SDRDATA12

SDRDATA13

SDRDATA14

SDRDATA15

SDRDATA2

SDRDATA3

SDRDATA4

SDRDATA5

SDRDATA6

SDRDATA7

SDRDATA8

SDRDATA9

SDRDQM0

SDRDQM1

SDRRAS

SDRDATA0

SDRDATA1

SDRDATA10

SDRDATA11

SDRDATA12

SDRDATA13

SDRDATA14

SDRDATA15

SDRDATA2

SDRDATA3

SDRDATA4

SDRDATA5

SDRDATA6

SDRDATA7

SDRDATA8

SDRDATA9

SDRDQM0

SDRDQM1

SDRRAS

Hiz

High

Hiz

High

Hiz

SDRWE

SWDCLK/

DMCKO0B/

GPIO58/

SWDCLK

D

EXTINT58

SWDIO/

DMDIN0B/

GPIO59/

SWDIO

Hiz

EXTINT59

D

NRES

TEST

NRES

TEST

Hiz

PD

Low

PD

Hiz

PD

Low

PD

XTALINFO0

XTALINFO1

BMODE0

BMODE1

IO18V

XTALINFO0

XTALINFO1

BMODE0

BMODE1

IO18V

D

RTCMODE

KEYINT0

USBDM

RTCMODE

KEYINT0

USBDM

D

KEYINT1

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LC823455

Table 17. TERMINAL STATE TABLE (continued)

Terminal status

NRES = High(ii)

Default Function

(NRES = Low)

(Note 11)

Terminal status

NRES = Low(i)

(Note 12)

RA

BGA240

RB

BGA136

XA

WLP120

PIN NAME

KEYINT2

BACKUPB

RTCINT

(Note 12)

D

KEYINT2

BACKUPB

RTCINT

VDET

PD

D

Hiz

D

−(Not Determined)

VDET

Hiz

LOUT/

GPLOUT

LOUT

D

ROUT/

GPROUT

ROUT

Hiz

D

USBDP

USBID

USBEXT02

USBVBUS

VCNT1

VCNT2

SIN0

USBDP

USBID

USBEXT02

USBVBUS

VCNT1

VCNT2

SIN0

Low

Hiz

−(Not Applicable)

Hiz

−(Not Applicable)

Hiz

−(Not Applicable)

D

SIN1

SIN2

SIN3

SIN4

SIN5

SIN6

SIN7

D

XIN1

XIN32K

XOUT1

XOUT32K

XIN32K

XOUT1

XOUT32K

*“D” Means a port is available for each package. “PD” means pull down.

11. Default function is port function set by NRES = Low.

12.NRES = High(ii) occurs just after NRES = Low(i).

13.This terminal is configured as an output terminal with PU disabled, and used as QSCS for the SPI I/F chip select during serial flash boot mode.

14.This terminal is configured as an output terminal and used as the boot monitor port during Internal ROM boot.

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LC823455

ELECTRICAL SPECIFICATION

Product parametric performance is indicated in the

Electrical Characteristics for the listed test conditions,

unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under

different conditions.

Table 18. MAXIMUM RATINGS (*VSS* = 0V)

Item

Symbol

Condition

Ratings

Unit

Maximum power supply voltage

Vdd1

−0.3 to 1.2

V

VddXT1

AVddPLL1

AVddPLL2

VddRTC

DVddUSBPHY1

−0.3 to 1.2

−0.3 to 2.0

V

AVddADC

AVddUSBPHY18

AVddDAMPL

AVddDAMPR

Vdd2

VddSD1

−0.3 to 3.65

V

AVddUSBPHY2

Input voltage

VI

−0.3 to

V

*Vdd*+0.3

VIUSB1

VIUSB2

USBDP,USBDM

terminal

−0.3 to 6.0

USBVBUS

terminal

−0.3 to 6.0

Operating ambient temperature

Topr

Tstg

−20 to +65

°C

Ambient temperature of preservation

−55 to +125

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

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LC823455

Table 19. RECOMMENDATION OPERATING CONDITIONS (T_A= −205C to +655C)

Low voltage operation

(Note 15)

High voltage operation

(Note 15)

Min

Typ

Max

Min

1.05

Typ

Max

1.155

Item

Symbol

Condition

Unit

Power supply

voltage

Vdd1

0.95

1.0

1.155

1.1

V

VddXT1

AVddPLL1

AVddPLL2

VddRTC

0.95

0.765

0.90

2.7

1.0

1.155

0.90

1.155

3.6

same as left

V

(Note 16)

1.0

3.3

1.8

3.3

1.8

1.0

3.3

1.8

1.5

Vdd2

(Note 17)

(Note 18)

1.7

1.95

3.6

VddSD1

2.7

1.7

1.95

1.1

AVddADC

1.7

DVddUSBPHY1

(Note 19)

(Note 20)

(Note 19)

(Note 20)

(Note 19)

(Note 20)

0.93

3.07

2.7

1.155

3.6

AVddUSBPHY2

AVddUSBPHY18

AVddDAMPL

AVddDAMPR

VIN

3.6

1.7

1.95

1.65

1.95

1.65

1.95

*Vdd*

1.7

0.95

0

(Note 21)

Input range

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

15.Follow the operating frequency specifications because the operating frequency ranges are specified according to the operating voltage

ranges.

16.APB clock needs 57.5 MHz or less.

17.IO terminals operating at Vdd2 need to be specified for the IO voltage range of either 3.3 V or 1.8 V according to the Vdd2 voltage by using

the IO18 V terminal. When setting 1.8 V IO interface, even for extremely short period, don’t supply not only the 3.3 V voltage range but also

any voltage over the 1.8 V voltage range to Vdd2.

18.IO terminals operating at VddSD1 need to be specified for the IO voltage range of either 3.3V or 1.8V according to the VddSD1 voltage by

setting a register “System Controller” described in the “System Functions User’s Manual”. When setting 1.8 V IO interface, even for extremely

short period, don’t supply not only the 3.3 V voltage range but also any voltage over the 1.8 V voltage range to VddSD1.

19.While USB is used (including USB suspend mode).

20.While USB is not used.

21.While used as GPO (general purpose output) the output of which can be controlled by registers.

The power domains of Vdd1, DVddUSBPHY1, AVddPLL1, AVddPLL2, VddXT1 are divided, and different voltages can be supplied.

The power domains of Vdd2, VddSD1, AVddADC, AVddUSBPHY2, AVdd USBPHY18, AvddDAMPL = AVddDAMPR are divided, and difference

voltages can be supplied.

If power is supplied to one of the power supply pins above, all the other power supply pins should also be supplied.

However, DVddUSBPHY1, AVddUSBPHY18 and AVddUSBPHY2 can all be turned off to reduce leakage current while USB is not used. In

addition, VddRTC can be supplied if BACKUPB is set to low, while other power supply pins are not supplied.

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LC823455

Table 20. RECOMMENDED OPERATING CONDITIONS

Low voltage operation

High voltage operation

Min

Typ

Max

Min

Typ

Max

Item

Symbol

Function

Unit

Xtal Input

frequency

Fxin1

System,

Audio clock

(XT1 oscillator)

12 MHz or 19.2 MHz or 24 MHz

Tolerance: 50 ppm or less

same as left

−

FxinRTC

RTC clock

(XTRTC

32.768 kHz

Tolerance : 50ppm or less

same as left

−

oscillator)

Frc

RC

0.4

(Note 25)

1

2

same as left

MHz

ms

(RC oscillator)

(Note 25)

Time for

Xtal stable

Txin1

3

(Note 26)

TxinRTC

1000

ms

(Note 26)

Internal clock

frequency

Farm

Fahb

Fapb

Fdsp

Cortex−M3

AHB

0

115

0

170

MHz

APB

115

DSP

115

Faud

AUDCLK(768fs)

33.8688

16.9344

147.456

same as left

(Note 22)

Fdec

DECCLK

(Note 23)

0

73.728

36.864

MHz

(MP3 Decoder)

Fenc

ENCCLK

(Note 24)

8.4672

same as left

(MP3 Encoder)

22.Audio blocks run on a clock of 256 * Fs(sampling frequency).

However, Class−D AMP, etc. run at 384 * Fs(sampling frequency).

These clocks are generated from 768 * Fs(Base Clock) divided by 3 and 2 respectively.

23.MP3 Decoder runs on a clock of 384 * Fs(sampling frequency of MPEG1 mode).

It runs on the clock of the same frequency as MPEG1 mode during MPEG2 / 2.5 mode. For example, even when operating in MPEG2 / 2.5

mode(Fs = 22.05 / 11.025 KHz as an example), please supply 16.9344MHz(= 384 * 44.1 KHz) clock which is the same clock frequency as

MPEG1 mode.

24.MP3 Encoder runs on a clock of 192 * Fs(sampling frequency of MPEG1 mode).

It runs on the clock of the same frequency as MPEG1 mode during MPEG2 / 2.5 mode. For example, even when operating in MPEG2 / 2.5

mode(Fs = 22.05 / 11.025 KHz as an example), please supply 8.4672Mhz (= 192 * 44.1 KHz) clock which is the same clock frequency as

MPEG1 mode.

25.Vdd1 = 0.95 V to 1.155 V, Ta = −25_C to +65_C.

26.It is a reference level in Ta = 25_C. Adjustment is necessary by the situation of the set.

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Table 21. DC CHARACTERISTICS

(Vdd2 = 2.7 V to 3.6 V, VddSD1 = 2.7 V to 3.6 V, VddRTC = 0.765 V to 1.155 V, Ta = −20°C to +65°C)

Item

Symbol

(1)(2)(4)

(3)

Condition

Min

Typ

Max

Unit

V

Input H voltage

V

IH

CMOS

0.7 x Vdd2

0.7 x VddSD1

0.75 x Vdd2

0.75 x VddSD1

0.7 x VddRTC

V

Schmitt

(6)(8)

(7)

V

(5)(9)

(1)(2)(4)

(3)

CMOS

V

Input L voltage

V

IL

0.25 x Vdd2

0.25 x VddSD1

0.2 x Vdd2

V

Schmitt

(6)(8)

(7)

V

0.2 x VddSD1

0.2 x VddRTC

V

(5)(9)

CMOS

V

Output H voltage

V

OH

I

= −2 mA

(10)(11)(12)

(14)(15)(17)

Vdd2 − 0.4

V

OH

(13)(16)

VddSD1 − 0.4

Vdd2 − 0.4

V

= −4 mA

(10)

OH

(14)(15)(17)

(16)

VddSD1 − 0.4

Vdd2 − 0.4

V

= −8 mA

(10)

OH

(14)(15)(17)

(16)

(14)(15)(17)

(16)

VddSD1 − 0.4

Vdd2 − 0.4

V

I

= −10 mA

OH

VddSD1 − 0.4

Output L voltage

V

OL

I

= 2 mA

= 4 mA

= 8 mA

(10)(11)(12)

(14)(15)(17)

0.4

OL

(13)(16)

0.4

V

I

(10)

OL

(14)(15)(17)

(16)

0.4

V

I

(10)

OL

(14)(15)(17)

(16)

(14)(15)(17)

(16)

0.4

0.3

150

80

V

I

= 10 mA

= 0.3 mA

OL

V

(18)

I

OL

V

Pull−up resistor

Rup

Rdn

(20)(21)

(22)

30

25

kꢀ

(23)

18

50

Pull−down resistor

(26)

VddRTC =

180

720

0.765 to 0.90 V

VddRTC =

93

280

kꢀ

0.90 to 1.155 V

(19)(21)

(22)

30

25

150

80

kꢀ

ꢁ A

(23)

18

50

Input leak current

I

IL

(1)(2)(3)

(4)(5)(6)

(7)(8)(9)

VI = Vdd*

or

VI = Vss

−10

10

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LC823455

Table 21. DC CHARACTERISTICS (continued)

(Vdd2 = 2.7 V to 3.6 V, VddSD1 = 2.7 V to 3.6 V, VddRTC = 0.765 V to 1.155 V, Ta = −20°C to +65°C)

Item

Symbol

Condition

Min

Typ

Max

Unit

Output leak current

I

(11)(12)

(13)(14)(15)

(16)(18)(27)

HiZ output

−10

10

ꢁ A

OZ

Table 22. DC CHARACTERISTICS

(Vdd2 = 1.7 V to 1.95 V, VddSD1 = 1.7 V to 1.95 V, AVddDAMPL = 0.95 V to 1.95 V, AVddDAMPR = 0.95 V to 1.95 V,

Ta = −20°C to +65°C)

Item

Symbol

Condition

Min

Typ

Max

Unit

Input H voltage

V

(1)(2)(4)

(3)

CMOS

0.7 x Vdd2

0.7 x VddSD1

0.75 x Vdd2

V

IH

(6)(8)

(7)

Schmitt

CMOS

Schmitt

0.75 x VddSD1

Input L voltage

V

(1)(2)(4)

(3)

0.3 x Vdd2

0.3 x VddSD1

0.25 x Vdd2

IL

(6)(8)

(7)

0.25 x VddSD1

Output H voltage

V

OH

(10)(11)(12)

(14)(15)(17)

I

= −2 mA

Vdd2 − 0.4

OH

(13)(16)

VddSD1 − 0.4

Vdd2 − 0.4

V

(10)

= −4 mA

OH

(14)(15)(17)

(16)

(14)(15)(17)

(16)

VddSD1 − 0.4

Vdd2 − 0.4

V

= −8 mA

OH

VddSD1 − 0.4

Vdd2 − 0.4

(14)(15)(17)

(16)

I

= −10 mA

OH

VddSD1 − 0.4

AVddDAMPL – 0.4

(24)

I

= −8 mA

OH

(Note 27)

(25)

I

= −8 mA

AVddDAMPR – 0.4

V

OH

(Note 27)

Output L voltage

V

OL

(10)(11)(12)

(14)(15)(17)

I

OL

I

OL

I

OL

= 2 mA

= 4 mA

= 8 mA

= 10 mA

0.4

(13)(16)

0.4

V

(10)

(14)(15)(17)

(16)

0.4

V

(10)

(14)(15)(17)

(16)

(14)(15)(17)

(16)

0.4

200

80

V

I

OL

V

(24)

I

= 8 mA

V

OL

(25)

V

OL

Pull−up resistor

Rup

Rdn

(20)(21)

(22)

30

25

18

30

25

18

kꢀ

(23)

50

Pull−down resistor

(19)(21)

(22)

200

80

(23)

50

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LC823455

Table 22. DC CHARACTERISTICS (continued)

(Vdd2 = 1.7 V to 1.95 V, VddSD1 = 1.7 V to 1.95 V, AVddDAMPL = 0.95 V to 1.95 V, AVddDAMPR = 0.95 V to 1.95 V,

Ta = −20°C to +65°C)

Item

Symbol

Condition

Min

Typ

Max

Unit

Input leak current

I

IL

(1)(2)(3)

(4)(6)

VI = Vdd*

or

VI = Vss

−10

10

ꢁ A

(7)(8)

Output leak current

I

(11)(12)

(13)(14)(15)

(16)(27)

HiZ output

−10

10

ꢁ A

OZ

(24)(25)

−10

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

(1) SDRDATA15, SDRDATA14, SDRDATA13, SDRDATA12, SDRDATA11, SDRDATA10, SDRDATA9, SDRDATA8, SDRDATA7, SDRDATA6,

SDRDATA5, SDRDATA4, SDRDATA3, SDRDATA2, SDRDATA1, SDRDATA0

(2) SDCLK2(GPIO09), SDCMD2(GPIO0A), SDAT23(GPIO57), SDAT22(GPIO56), SDAT21(GPIO05), SDAT20(GPIO04), PSM_SCK,

PSM_CS, PSM_SDI, PSM_SDO, PSM_DAT2, PSM_DAT3

(3) SDCLK1(GPIO22), SDCMD1(GPIO23), SDAT13(GPIO27), SDAT12(GPIO26), SDAT11(GPIO25), SDAT10(GPIO24)

(4) SDCMD0, SDAT03, SDAT02, SDAT01, SDAT00, SFCK(GPIO0D), SFDI(GPIO0E), SFDO(GPIO0F), SFWP(GPIO11),

SFHOLD(GPIO12), TIOCB01(GPIO03)

(5) RTCMODE, VDET

(6) SDWP2(GPIO28), SDCD2(GPIO29), EXD0(GPIO46), EXD1(GPIO47), EXD2(GPIO48), EXD3(GPIO49), EXD4(GPIO4A),

EXD5(GPIO4B), EXD6(GPIO4C), EXD7(GPIO4D), EXD8(GPIO4E), EXD9(GPIO4F), EXD10(GPIO50), EXD11(GPIO51),

EXD12(GPIO52), EXD13(GPIO53), EXD14(GPIO54), EXD15(GPIO55), EXA1(GPIO32), EXA2(GPIO33), EXA3(GPIO34),

EXA4(GPIO35), EXA5(GPIO36), EXA6(GPIO37), EXA7(GPIO38), EXA8(GPIO39), EXA9(GPIO3A), EXA10(GPIO3B),

EXA11(GPIO3C), EXA12(GPIO3D), EXA13(GPIO3E), EXA14(GPIO3F), EXA15(GPIO40), EXA16(GPIO41), EXA17(GPIO42),

EXA18(GPIO43), EXA19(GPIO44), EXA20(GPIO45), NRD(GPIO17), NLBEXA0(GPIO16), NHBNWRH(GPIO31), NCS1(GPIO10),

NCS0(GPIO06), NWRENWRL(GPIO30), SWDIO(GPIO59), DOUT1(GPIO15), BCK1(GPIO13), MCLK0(GPIO18), LRCK1(GPIO14),

BCK0(GPIO19), LRCK0(GPIO1A), DIN0(GPIO1B), XTALINFO1, DOUT0(GPIO1C), NRES, SCL1(GPIO2B), SDA1(GPIO2C),

TCLKA0(GPIO00), TCLKB0(GPIO01), EXTINT2E(GPIO2E), EXTINT2F(GPIO2F), TXD2(GPIO0B), RXD2(GPIO0C),

TIOCB00(GPIO02), XTALINFO0, SDO0(GPIO1F), SCK0(GPIO1D), SCL0(GPIO07), SDI0(GPIO1E), SDA0(GPIO08),

SWDCLK(GPIO58), SDRADDR12(GPIO2A), SDRADDR11(GPIO2D)

(7) SDWP1(GPIO21), SDCD1(GPIO20)

(8) BMODE0, BMODE1

(9) Keyint2, Keyint0, Keyint1, BACKUPB, TEST

(10) EXD0(GPIO46), EXD1(GPIO47), EXD2(GPIO48), EXD3(GPIO49), EXD4(GPIO4A), EXD5(GPIO4B), EXD6(GPIO4C), EXD7(GPIO4D),

EXD8(GPIO4E), EXD9(GPIO4F), EXD10(GPIO50), EXD11(GPIO51), EXD12(GPIO52), EXD13(GPIO53), EXD14(GPIO54),

EXD15(GPIO55), EXA1(GPIO32), EXA2(GPIO33), EXA3(GPIO34), EXA4(GPIO35), EXA5(GPIO36), EXA6(GPIO37), EXA7(GPIO38),

EXA8(GPIO39), EXA9(GPIO3A), EXA10(GPIO3B), EXA11(GPIO3C), EXA12(GPIO3D), EXA13(GPIO3E), EXA14(GPIO3F),

EXA15(GPIO40), EXA16(GPIO41), EXA17(GPIO42), EXA18(GPIO43), EXA19(GPIO44), EXA20(GPIO45), NRD(GPIO17),

NLBEXA0(GPIO16), NHBNWRH(GPIO31), NCS1(GPIO10), NCS0(GPIO06), NWRENWRL(GPIO30), DOUT1(GPIO15),

BCK1(GPIO13), MCLK0(GPIO18), LRCK1(GPIO14), BCK0(GPIO19), LRCK0(GPIO1A), DIN0(GPIO1B), XTALINFO1,

DOUT0(GPIO1C), SCL1(GPIO2B), SDA1(GPIO2C), TCLKA0(GPIO00), TCLKB0(GPIO01), EXTINT2E(GPIO2E), EXTINT2F(GPIO2F),

TXD2(GPIO0B), RXD2(GPIO0C), TIOCB00(GPIO02), XTALINFO0, SDO0(GPIO1F), SCK0(GPIO1D), SCL0(GPIO07), SDI0(GPIO1E),

SDA0(GPIO08), SWDCLK(GPIO58), SDRADDR0, SDRADDR1, SDRADDR2, SDRADDR3, SDRADDR4, SDRADDR5, SDRADDR6,

SDRADDR7, SDRADDR8, SDRADDR9, SDRADDR10, SDRADDR11(GPIO2D), SDRADDR12(GPIO2A), SDRDATA0, SDRDATA1,

SDRDATA2, SDRDATA3, SDRDATA4, SDRDATA5, SDRDATA6, SDRDATA7, SDRDATA8, SDRDATA9, SDRDATA10, SDRDATA11,

SDRDATA12, SDRDATA13, SDRDATA14, SDRDATA15, SDRBA1, SDRBA0, SDRCKE, SDRCS, SDRWE, SDRCAS, SDRRAS,

SDRDQM1, SDRDQM0, SDWP2(GPIO28), SDCD2(GPIO29)

(11) SWDIO(GPIO59)

(12) BMODE0, BMODE1

(13) SDWP1(GPIO21), SDCD1(GPIO20)

(14) SDCLK0, SDCMD0, SDAT03, SDAT02, SDAT01, SDAT00, SFCK(GPIO0D), SFDI(GPIO0E), SFDO(GPIO0F), SFWP(GPIO11),

SFHOLD(GPIO12), TIOCB01(GPIO03)

(15) SDCLK2(GPIO09), SDCMD2(GPIO0A), SDAT23(GPIO57), SDAT22(GPIO56), SDAT21(GPIO05), SDAT20(GPIO04), PSM_SCK,

PSM_CS, PSM_SDI, PSM_SDO, PSM_DAT2, PSM_DAT3

(16) SDCLK1(GPIO22), SDCMD1(GPIO23), SDAT13(GPIO27), SDAT12(GPIO26), SDAT11(GPIO25), SDAT10(GPIO24),

(17) SDRCLK

(18) RTCINT

(19) EXD0(GPIO46), EXD1(GPIO47), EXD2(GPIO48), EXD3(GPIO49), EXD4(GPIO4A), EXD5(GPIO4B), EXD6(GPIO4C), EXD7(GPIO4D),

EXD8(GPIO4E), EXD9(GPIO4F), EXD10(GPIO50), EXD11(GPIO51), EXD12(GPIO52), EXD13(GPIO53), EXD14(GPIO54),

EXD15(GPIO55), EXA1(GPIO32), EXA2(GPIO33), EXA3(GPIO34), EXA4(GPIO35), EXA5(GPIO36), EXA6(GPIO37), EXA7(GPIO38),

EXA8(GPIO39), EXA9(GPIO3A), EXA10(GPIO3B), EXA11(GPIO3C), EXA12(GPIO3D), EXA13(GPIO3E), EXA14(GPIO3F),

EXA15(GPIO40), EXA16(GPIO41), EXA17(GPIO42), EXA18(GPIO43), EXA19(GPIO44), EXA20(GPIO45), NRD(GPIO17),

NLBEXA0(GPIO16), NHBNWRH(GPIO31), NWRENWRL(GPIO30), SDRDATA0, SDRDATA1, SDRDATA2, SDRDATA3, SDRDATA4,

SDRDATA5, SDRDATA6, SDRDATA7, SDRDATA8, SDRDATA9, SDRDATA10, SDRDATA11, SDRDATA12, SDRDATA13, SDRDATA14,

SDRDATA15

(20) NCS1(GPIO10), NCS0(GPIO06), XTALINFO1, XTALINFO0, SWDIO(GPIO59)

(21) DOUT1(GPIO15), BCK1(GPIO13), MCLK0(GPIO18), LRCK1(GPIO14), BCK0(GPIO19), LRCK0(GPIO1A), DIN0(GPIO1B),

DOUT0(GPIO1C), SCL1(GPIO2B), SDA1(GPIO2C), TCLKA0(GPIO00), TCLKB0(GPIO01), SDO0(GPIO1F), SCK0(GPIO1D),

SCL0(GPIO07), SDI0(GPIO1E), SDA0(GPIO08), EXTINT2E(GPIO2E), EXTINT2F(GPIO2F), TXD2(GPIO0B), RXD2(GPIO0C),

TIOCB00(GPIO02), SWDCLK(GPIO58), SDWP1(GPIO21), SDCD1(GPIO20), SDRADDR11(GPIO2D), SDRADDR12(GPIO2A),

SDWP2(GPIO28), SDCD2(GPIO29)

(22) SDCLK1(GPIO22), SDCMD1(GPIO23), SDAT13(GPIO27), SDAT12(GPIO26), SDAT11(GPIO25), SDAT10(GPIO24),

SDCLK2(GPIO09), SDCMD2(GPIO0A), SDAT23(GPIO57), SDAT22(GPIO56), SDAT21(GPIO05), SDAT20(GPIO04), PSM_SCK,

PSM_CS, PSM_SDI, PSM_SDO, PSM_DAT2, PSM_DAT3, BMODE0, BMODE1

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LC823455

(23) SDCMD0, SDAT03, SDAT02, SDAT01, SDAT00, SFCK(GPIO0D), SFDI(GPIO0E), SFDO(GPIO0F), SFWP(GPIO11),

SFHOLD(GPIO12), TIOCB01(GPIO03)

(24) LOUT(used as GPLOUT)

(25) ROUT(used as GPROUT)

(26) Keyint0, Keyint1, Keyint2

(27) EXD0(GPIO46), EXD1(GPIO47), EXD2(GPIO48), EXD3(GPIO49), EXD4(GPIO4A), EXD5(GPIO4B), EXD6(GPIO4C), EXD7(GPIO4D),