LC863820B(48QIP) [ONSEMI]
Microcontroller, 8-Bit, FLASH, 3MHz, CMOS, PQFP48;
| 型号： | LC863820B(48QIP) |
| 厂家： | 
ONSEMI |
| 描述： | Microcontroller, 8-Bit, FLASH, 3MHz, CMOS, PQFP48 控制器 微控制器 微控制器和处理器 |
| 文件： | 总20页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0119A
LC863864B, LC863856B
LC863848B, LC863840B
LC863832B, LC863828B
LC863824B, LC863820B
LC863816B
CMOS IC
64K/56K/48K/40K/32K/28K/24K/20K/16K-byte ROM,
CGROM16K-byte
on-chip 768-byte RAM and 352×9-bit OSD RAM
8-bit 1-chip Microcontroller
Overview
The LC863864B/56B/48B/40B/32B/28B/24B/20B/16B are 8-bit single chip microcontrollers with the following on-chip
functional blocks :
• CPU : Operable at a minimum bus cycle time of 0.424µs
• On-chip ROM capacity
Program ROM : 64K/56K/48K/40K/32K/28K/24K/20K/16K-bytes
CGROM
: 16K-bytes
• On-chip RAM capacity : 768-bytes
• OSD RAM : 352 × 9-bits
• Closed-Caption TV controller and the on-screen display controller
• Closed-Caption data slicer
• Four channels × 8-bit AD Converter
• Three channels × 7-bit PWM
• Two 16-bit timer/counter, 14-bit base timer
• 8-bit synchronous serial interface circuit
• IIC-bus compliant serial interface circuit (Multi-master type)
Continued on next page.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in
advance of our receiving your program ROM code order.
Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in
an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips.
Trademarks
IIC is a trademark of Philips Corporation.
Ver.1.00
52506HKIM No.A0119-1/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
• ROM correction function
• 16-source 10-vectored interrupt system
• Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the closed caption function
All of the above functions are fabricated on a single chip.
Features
Read-only memory (ROM)
: 65536 × 8-bits / 57344 × 8-bits / 49152 × 8-bits /
40960 × 8-bits / 32768 × 8-bits / 28672 × 8-bits /
24576 × 8-bits / 20480 × 8-bits / 16384 × 8-bits for program
16128 × 8-bits for CGROM
Random access memory (RAM) : 768 × 8-bits (including 128 bytes for ROM correction function)
352 × 9-bits (for CRT display)
OSD functions
• Screen display : 36 characters × 16 lines (by software)
• RAM
Display area : 36 words × 8 lines
Control area : 8 words × 8 lines
• Characters
: 352 words (9-bits per word)
Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts : a 16 × 17 dot and 8 × 9 dot character font
At least 111 characters need to be divide to display the caption fonts.
• Various character attributes
Character colors
: 16 colors
Character background colors : 16 colors
Fringe/shadow colors
Full screen colors
Rounding
: 16 colors
: 16 colors
Underline
Italic character (slanting)
• Attribute can be changed without spacing
• Vertical display start line number can be set for each row independently (Rows can be overlapped)
• Horizontal display start position can be set for each row independently
• Horizontal pitch (9 to 16 dots) *1 and vertical pitch (1 to 32 dots) can be set for each row independently
• Different display modes can be set for each row independently
Caption • Text mode/OSD mode 1/OSD mode 2 (Quarter size) /Simplified graphic mode
• Ten character sizes *1
Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)
(1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5)
• Shuttering and scrolling on each row
• Simplified graphic display
*1 Note : Range depends on display mode : refer to the manual for details.
Data Slicer (closed caption format)
• Closed caption data and XDS data extraction
• NTSC/PAL, and extracted line can be specified
Bus Cycle Time/Instruction-Cycle Time
Bus cycle time
Instruction cycle time
Clock divider
System clock oscillation
Internal VCO
(Ref : X'tal 32.768kHz)
Internal RC
Oscillation frequency
14.156MHz
Voltage
0.424µs
0.848µs
1/2
4.5V to 5.5V
7.5µs
15.0µs
183.1µs
366.2µs
1/2
1/1
1/2
800kHz
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
91.55µs
183.1µs
Crystal
32.768kHz
32.768kHz
Crystal
No.A0119-2/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Ports
• Input/Output Ports
Data direction programmable in nibble units
: 5 ports (28 terminals)
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually : 4 ports (20 terminals)
AD converter
• 4-channels × 8-bit AD converters
Serial interfaces
• IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
• Synchronous 8-bit serial interface
PWM output
• 3-channels × 7-bit PWM
Timer
• Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
• Timer 1 : 16-bit timer/ PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9 to 16 bits)
In mode0/1, the resolution of Timer1/PWM is 1 tCYC
In mode2/3, the resolution is selectable by program; tCYC or 1/2 tCYC
• Base timer
Generate every 500ms overflow for a clock application
(using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow
(using 32.768kHz crystal oscillation for the base timer clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
• Noise rejection function
• Polarity switching
Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
ROM correction function
Max 128-bytes/2 addresses
No.A0119-3/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Interrupts
• 16 sources 10 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8-bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8-bits)
6. Timer T1H, Timer T1L
7. SIO0
8. Data slicer
9. Vertical synchronous signal interrupt ( ), horizontal line ( ), AD
VS HS
10. IIC, Port 0
• Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.
Low or high priority can be assigned to the interrupts from 3 to 10 listed above.
For the external interrupt INT0 and INT1, low or highest priority can be set.
Sub-routine stack level
• A maximum of 128 levels (stack is built in the internal RAM)
Multiplication/division instruction
• 16-bits × 8-bits (7 instruction cycle times)
• 16-bits ÷ 8-bits (7 instruction cycle times)
3 oscillation circuits
• Built-in RC oscillation circuit used for the system clock
• Built-in VCO circuit used for the system clock and OSD
• X’tal oscillation circuit used for base timer, system clock and PLL reference
Standby function
• HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.
• HOLD mode
The HOLD mode is used to stop the oscillations ; RC (internal), VCO, and X’tal oscillations.
This mode can be released by the following conditions.
1. Pull the reset terminal (
RES
) to low level.
2. Feed the selected level to either P70/INT0 or P71/INT1.
3. Input the interrupt condition to Port 0.
Package
• DIP42S (Lead-free type)
• QIP48E (Lead-free type)
Development tools
• Flash EEPROM
• Evaluation chip
• Emulator
: LC86F3864A
: LC863096
: EVA86000 (main) + ECB863200A (evaluation chip board)
+ POD863200 (pod: DIP42S) or POD863201 (QIP48E)
[Shared with LC8632 Series]
No.A0119-4/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Package Dimensions
unit : mm
3025C
37.7
42
22
1
21
0.95
0.48
1.78
SANYO : DIP42S(600mil)
(1.05)
Package Dimensions
unit : mm
3156A
17.2
14.0
25
36
24
13
37
48
1
12
0.35
0.15
1.0
(1.5)
SANYO : QIP48E(14X14)
No.A0119-5/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Pin Assignment
P10/SO0
P11/SI0
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P07
2
P06
P12/SCK0
P13/PWM1
P14/PWM2
P15/PWM3
P16
3
P05
4
P04
5
P03
6
P02
7
P01
LC863864B
LC863856B
LC863848B
LC863840B
LC863832B
LC863828B
LC863824B
LC863820B
LC863816B
P17/PWM
8
P00
V
9
P73/INT3/T0IN
SS
XT1
XT2
10
11
12
13
14
15
16
17
18
19
20
21
P72/INT2/T0IN
P71/INT1
V
P70/INT0
DD
P84/AN4
P63/SCLK1
P85/AN5
P86/AN6
P87/AN7
RES
P62/SDA1
P61/SCLK0
DIP42S
P60/SDA0
I
FILT
BL
B
CVIN
VS
G
R
HS
Top view
P15/PWM3
P16
1
36
35
34
33
32
31
30
29
28
27
26
25
P02
2
P01
LC863864B
LC863856B
LC863848B
LC863840B
LC863832B
LC863828B
LC863824B
LC863820B
LC863816B
P17/PWM
3
P00
V
4
NC
SS
XT1
XT2
5
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
P63/SCLK1
P62/SDA1
P61/SCLK0
P60/SDA0
6
V
7
DD
NC
8
P84/AN4
P85/AN5
P86/AN6
P87/AN7
9
10
11
12
QIP48E
Top view
No.A0119-6/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
System Block Diagram
Interrupt Control
Standby Control
IR
PLA
ROM
X’tal
RC
VCO
PC
PLL
IIC
ROM Correct Control
ACC
B Register
C Register
SIO0
XRAM
Timer 0
Bus Interface
Timer 1
Port 1
Port 6
ALU
Base Timer
ADC
Port 7
Port 8
PSW
RAR
RAM
INT0-3
Noise Rejection Filter
PWM
CGROM
OSD
Control
Circuit
Data Slicer
Stack Pointer
Port 0
VRAM
Watch Dog Timer
No.A0119-7/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Pin Description
Terminal
I/O
Function Description
Negative power supply
Option
V
-
SS
XT1
XT2
I
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Positive power supply
O
-
V
DD
RES
FILT
CVIN
VS
HS
R
I
Reset terminal
O
I
Filter terminal for PLL
Video signal input terminal
I
Vertical synchronization signal input terminal
Horizontal synchronization signal input terminal
Red (R) output terminal of RGB image output
Green (G) output terminal of RGB image output
Blue (B) output terminal of RGB image output
Intensity ( I ) output terminal of RGB image output
I
O
O
O
O
O
G
B
I
BL
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
Port 0
I/O
• 8-bit input/output port,
Input/output can be specified in nibble unit
• Other functions
Pull-up resistor
provided/not provided
Output Format
P00 to P07
HOLD release input
CMOS/Nch-OD
Interrupt input
Port 1
I/O
• 8-bit input/output port
Input/output can be specified in a bit
• Other functions
Output Format
CMOS/Nch-OD
P10 to P17
P10
P11
P12
P13
P14
P15
P17
SIO0 data output
SIO0 data input/bus input/output
SIO0 clock input/output
PWM1 output
PWM2 output
PWM3 output
Timer1 (PWM) output
Port 6
I/O
• 4-bit input/output port
Input/output can be specified for each bit
• Other functions
P60 to P63
P60
P61
P62
P63
IIC0 data I/O
IIC0 clock output
IIC1 data I/O
IIC1 clock output
Continued on next page.
No.A0119-8/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
Terminal
Port 7
I/O
I/O
Function Description
Option
• 4-bit input/output port
Input or output can be specified for each bit
• Other function
P70
P71 to P73
P70
INT0 input/HOLD release input/
Nch-Tr. output for watchdog timer
INT1 input/HOLD release input
INT2 input/Timer 0 event input
INT3 input (noise rejection filter connected)/
Timer 0 event input
P71
P72
P73
Interrupt receiver format, vector addresses
rising/
rising
falling
H level
L level
vector
falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
03H
0BH
13H
1BH
Port 8
I/O
• 4-bit input/output port
Input or output can be specified for each bit
• Other function
P84 to P87
AD converter input port (4 lines)
Unused terminal
NC
-
Leave open
• Output form and existence of pull-up resistor for all ports can be specified for each bit.
• Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain
output in port 1.
• Port status in reset
Terminal
Port 0
I/O
Pull-up resistor status at selecting pull-up option
Pull-up resistor OFF, ON after reset release
Programmable pull-up resistor OFF
I
I
Port 1
No.A0119-9/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Absolute Maximum Ratings / Ta = 25°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
-0.3
typ
max
+6.5
unit
V
DD
Maximum supply
voltage
V
max
V
DD
DD
Input voltage
V (1)
,
,
, CVIN
RES HS VS
-0.3
-0.3
-0.3
V
V
V
+0.3
+0.3
+0.3
I
DD
DD
DD
Output voltage
V
V
(1)
R, G, B, I, BL, FILT
Ports 0, 1, 6, 7, 8
Ports 0, 1, 7, 8
O
Input/output voltage
IO
High
Peak
IOPH(1)
• CMOS output
• For each pin.
• CMOS output
• For each pin.
The total of all pins.
-4
-5
level
output
current
output
current
IOPH(2)
R, G, B, I, BL
Total
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
IOPL(1)
Ports 0, 1
-20
-10
-15
output
current
Ports 7, 8
The total of all pins.
The total of all pins.
For each pin.
R, G, B, I, BL
Ports 0, 1, 6, 8
Port 7
mA
Low
Peak
20
15
level
output
current
IOPL(2)
For each pin.
output
current
IOPL(3)
R, G, B, I, BL
Ports 0, 1
For each pin.
5
Total
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Pd max
The total of all pins.
The total of all pins.
The total of all pins.
Ta = -10 to +70°C
40
output
current
Ports 6, 7, 8
R, G, B, I, BL
DIP42S
40
15
Maximum power
dissipation
715
385
mW
°C
QIP48E
Operating
Topr
Tstg
-10
-55
+70
temperature range
Storage
+125
temperature range
Recommended Operating Range / Ta = -10°C to +70°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
5.5
unit
DD
Operating supply
voltage range
V
V
V
(1)
V
0.844µs ≤ tCYC ≤ 0.852µs
4µs ≤ tCYC ≤ 400µs
4.5
DD
DD
DD
(2)
4.5
5.5
DD
Hold voltage
V
RAMs and the registers
data are kept in HOLD
mode.
HD
2.0
5.5
High level input
voltage
V
(1)
IH
Port 0 (Schumitt)
Output disable
4.5 to 5.5
4.5 to 5.5
0.6V
V
V
DD
DD
V (2)
IH
• Ports 1, 6 (Schumitt)
• Port 7 (Schumitt)
port input/interrupt
Output disable
V
0.75V
DD
DD
•
,
,
HS VS RES
(Schumitt)
V
(3)
IH
Port 70
Output disable
Output disable
4.5 to 5.5
4.5 to 5.5
V
-0.5
DD
V
V
DD
Watchdog timer input
Port 8
V (4)
IH
0.7V
DD
DD
Watchdog timer input
Continued on next page.
No.A0119-10/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
Limits
Parameter
Symbol
Pins
Conditions
Output disable
V
[V]
min
V
typ
max
0.2V
unit
DD
Low level input
voltage
V
(1)
IL
Port 0 (Schumitt)
4.5 to 5.5
SS
DD
V
(2)
IL
• Ports 1, 6 (Schumitt)
• Port 7 (Schumitt)
port input/interrupt
Output disable
4.5 to 5.5
V
0.25V
0.6V
SS
DD
•
,
,
HS VS RES
V
(Schumitt)
V
(3)
IL
Port 70
Output disable
Output disable
4.5 to 5.5
4.5 to 5.5
V
V
SS
DD
Watchdog timer input
Port 8
V (4)
IL
0.3V
SS
DD
Watchdog timer input
CVIN
CVIN
VCVIN
1Vp-p
-3dB
1Vp-p
+3dB
5.0
1Vp-p
0.848
Vp-p*
Operation
cycle time
tCYC(1)
tCYC(2)
• All functions operating
4.5 to 5.5
0.844
0.852
• AD converter operating
• OSD and Data slicer are
not operating
4.5 to 5.5
0.844
30
µs
tCYC(3)
FmRC
• OSD, AD converter and
Data slicer are not
operating
4.5 to 5.5
4.5 to 5.5
0.844
0.4
400
3.0
Oscillation
Internal RC oscillation
0.8
MHz
frequency range
* Vp-p : Peak-to-peak voltage
Electrical Characteristics / Ta = -10°C to +70°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 6, 7, 8
• Output disable
• Pull-up MOS Tr. OFF
• V = V
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
1
1
IN
DD
(Including the off-leak current of
the output Tr.)
I
I
(2)
IH
•
•
• V = V
RES
IN
DD
,
HS VS
µA
Low level input
current
(1)
IL
Ports 0, 1, 6, 7, 8
• Output disable
• Pull-up MOS Tr. OFF
• V = V
-1
IN
SS
(Including the off- leak current of
the output Tr.)
I
(2)
IL
•
•
V
= V
SS
RES
IN
4.5 to 5.5
4.5 to 5.5
-1
-1
,
HS VS
High level
V
(1)
• CMOS output of
ports 0, 1, 71 to 73, 8
R, G, B, I, BL
I
= -1.0mA
OH
OH
V
DD
output voltage
V
V
V
V
(2)
I
I
I
I
= -0.1mA
= 10mA
= 1.6mA
= 3.0mA
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
V
-0.5
OH
OH
OL
OL
OL
DD
Low level
(1)
(2)
(3)
Ports 0, 1, 71 to 73, 8
Ports 0, 1, 71 to 73, 8
1.5
0.4
OL
OL
OL
output voltage
V
• R, G, B, I, BL
• Port 6
4.5 to 5.5
0.4
V
V
(4)
(5)
Port 6
I
I
= 6.0mA
= 1mA
= 0.9V
4.5 to 5.5
4.5 to 5.5
0.6
0.4
OL
OL
Port 70
OL
OL
Pull-up MOS
Tr. resistance
Bus terminal
short circuit
Rpu
• Ports 0, 1, 7, 8
V
OH
DD
4.5 to 5.5
13
38
80
kΩ
RBS
• P60 to P62
• P61 to P63
resistance
4.5 to 5.5
130
300
Ω
(SCL0 to SCL1,
SDA0 to SDA1)
Continued on next page.
No.A0119-11/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
Limits
Parameter
Symbol
VHIS
Pins
Conditions
Output disable
V
[V]
min
typ
max
unit
V
DD
Hysteresis
• Ports 0, 1, 6, 7
voltage
•
•
4.5 to 5.5
5.0
0.1V
RES
DD
,
HS VS
Input clump
voltage
VCLMP
CP
CVIN
2.3
2.5
10
2.7
Pin
All pins
• f = 1MHz
capacitance
• Every other terminals are
4.5 to 5.5
pF
connected to V
• Ta = 25°C
.
SS
Serial Input/Output Characteristics at Ta = -10°C to +70°C, V = 0V
SS
Ratings
Parameter
Symbol
Pins
Conditions
unit
V
[V]
min
typ
max
DD
Cycle
tCKCY(1)
tCKL(1)
•SCK0
Refer to figure 4.
2
1
•SCLK0
Low Level
4.5 to 5.5
4.5 to 5.5
pulse width
High Level
pulse width
Cycle
tCKH(1)
1
2
tCYC
tCKCY(2)
tCKL(2)
•SCK0
• Use pull-up
•SCLK0
resistor (1kΩ)
when Nch open-
drain output.
Low Level
pulse width
1/2tCKCY
1/2tCKCY
High Level
tCKH(2)
tICK
• Refer to figure 4.
pulse width
Data set up time
SI0
• Data set-up to
SCK0.
0.1
0.1
• Data hold from
SCK0.
4.5 to 5.5
Data hold time
tCKI
• Refer to figure 4.
µs
Output delay time
tCKO(1)
tCKO(2)
SO0
SO0
• Data hold from
SCK0.
7/12tCYC
+0.2
4.5 to 5.5
4.5 to 5.5
(Using external clock)
Output delay time
• Use pull-up
resistor (1kΩ)
when Nch open-
drain output.
• Refer to figure 4.
(Using internal clock)
1/3tCYC
+0.2
IIC Input/Output Conditions / Ta = -10°C to +70°C, V = 0V
SS
Standard
High speed
Parameter
Symbol
unit
min
0
max
min
max
SCL frequency
fSCL
tBUF
100
0
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
BUS free time between stop to start
HOLD time of start, restart condition
L time of SCL
4.7
4.0
4.7
4.0
4.7
0
-
1.3
-
tHD ; STA
tLOW
-
0.6
-
-
1.3
-
H time of SCL
tHIGH
-
0.6
0.6
-
-
Set-up time of restart condition
HOLD time of SDA
tSU ; STA
tHD ; DAT
tSU ; DAT
tR
-
-
-
0
0.9
-
Set-up time of SDA
250
-
100
Rising time of SDA, SCL
Falling time of SDA, SCL
Set-up time of stop condition
1000
300
-
20 + 0.1Cb
20 + 0.1Cb
0.6
300
300
-
tF
-
tSU ; STO
4.0
Refer to figure 10
Note: Cb: Total capacitance of all BUS (unit: pF)
No.A0119-12/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Pulse Input Conditions / Ta = -10°C to +70°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
High/low level pulse
width
tPIH(1)
•INT0, INT1
• Interrupt acceptable
• Timer 0-countable
• Interrupt acceptable
• Timer 0-countable
4.5 to 5.5
4.5 to 5.5
1
2
tPIL(1)
tPIH(2)
tPIL(2)
•INT2/T0IN
INT3/T0IN
(1 tCYC is selected for
noise rejection clock.)
INT3/T0IN
tCYC
tPIH(3)
tPIL(3)
• Interrupt acceptable
• Timer 0-countable
(16 tCYC is selected for
noise rejection clock.)
INT3/T0IN
4.5 to 5.5
32
tPIH(4)
tPIL(4)
• Interrupt acceptable
• Timer 0-countable
(64 tCYC is selected for
noise rejection clock.)
RES
4.5 to 5.5
4.5 to 5.5
128
200
tPIL(5)
Reset acceptable
tPIH(6)
tPIL(6)
,
• Display position
controllable
HS VS
µs
• The active edge of
HS
4.5 to 5.5
4.5 to 5.5
3
and
must be apart
VS
at least 1 tCYC.
• Refer to figure 6.
Refer to figure 6.
Rising/falling time
tTHL
tTLH
HS
500
ns
AD Converter Characteristics / Ta = -10°C to +70°C, V = 0V
SS
Limits
8
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
Absolute precision
Conversion time
ET
(Note 3)
±1.5
LSB
tCAD
ADCR2=0 (Note 4)
ADCR2=1 (Note 4)
16
32
tCYC
V
4.5 to 5.5
Analog input
voltage range
Analog port
input current
VAIN
AN4 to AN7
V
V
SS
DD
IAINH
IAINL
VAIN = V
DD
1
µA
VAIN = V
SS
-1
Note 3: Absolute precision does not include quantizing error (1/2LSB).
Note 4: Conversion time is the time till the complete digital conversion value for analog input value is set to a register
after the instruction to start conversion is sent.
No.A0119-13/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Current Dissipation Characteristics / Ta = -10°C to +70°C, V = 0V
SS
The sample current dissipation characteristics is the measurement result of SANYO provided evaluation board when
the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The
currents through the output transistors and the pull-up MOS transistors are ignored.
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Current dissipation
during basic
operation
IDDOP(1)
V
• FmX’tal=32.768kHz
X’tal oscillation
DD
• System clock : VCO
• VCO for OSD operating
• Internal RC oscillation stops
• FmX’tal=32.768kHz
X’tal oscillation
4.5 to 5.5
10
55
24
mA
(Note 5)
IDDOP(2)
• System clock : X'tal
(Instruction cycle time: 366.2µs)
• VCO for system, VCO for OSD,
Internal RC oscillation stop
• Data slicer, AD converters stop
• HALT mode
4.5 to 5.5
300
µA
Current dissipation
in HALT mode
(Note 5)
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
• FmX’tal=32.768kHz
X’tal oscillation
4.5 to 5.5
3
9
mA
• System clock : VCO
• VCO for OSD stops
• Internal RC oscillation stops
• HALT mode
• FmX’tal=32.768kHz
X’tal oscillation
4.5 to 5.5
300
1000
• VCO for system stops
• VCO for OSD stops
• System clock : Internal RC
• HALT mode
• FmX’tal=32.768kHz
X’tal oscillation
µA
• VCO for system stops
• VCO for OSD stops
• System clock : X’tal
(Instruction cycle time: 366.2µs)
• HOLD mode
4.5 to 5.5
4.5 to 5.5
45
200
20
Current dissipation
in HOLD mode
(Note 5)
IDDHOLD
• All oscillation stops.
0.05
(Note 5) The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A0119-14/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions :
• Recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation
evaluation board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected
externally.
Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C)
Oscillation
Recommended circuit parameters
Operating supply
voltage range
stabilizing time
Frequency
Manufacturer
Oscillator
Notes
C1
C2
Rf
Rd
typ
max
1.5s
32.768kHz
Seiko Epson
C-002RX
18pF
18pF
OPEN
390kΩ
4.5 to 5.5V
1.0s
Notes : The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes
stable after the following conditions. (Refer to Figure 2.)
1. The V
2. The HOLD mode is released.
becomes higher than the minimum operating voltage after the power is supplied.
DD
The sample oscillation circuit characteristics may differ applications.
For further assistance, please contact with oscillator manufacturer with the following notes in your mind.
• Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of
-10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high
reliability such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with
SANYO sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed
with low gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
• The capacitors’ V should be allocated close to the microcontroller’s GND terminal and be away from other GND.
SS
• The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
C2
X’tal
Figure 1 Recommended oscillation circuit
No.A0119-15/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
V
V
0V
DD
DD
Power supply
RES
limit
Reset time
Internal RC
resonator
oscillation
XT1, XT2
VCO for system
Operation mode
tmsVCO
Reset
stable
Unfixed
Instruction execution mode
<Reset time and oscillation stabilizing time>
HOLD release
Valid
Internal RC
resonator
oscillation
XT1, XT2
VCO for system
Operation mode
tmsVCO
stable
HOLD
Instruction execution mode
<HOLD release signal and oscillation stabilizing time>
Figure 2 Oscillation stabilizing time
No.A0119-16/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
V
DD
(Note) Determine the CRES, RRES value to generate
R
RES
more than 200µs reset time.
RES
C
RES
Figure 3 Reset circuit
0.5V
DD
<AC timing measurement point>
V
tCKCY
DD
tCKL
tCKH
SCK0
1kΩ
tCKI
tICK
SI0
tCKO
50pF
SO0
SB0
<Timing>
Figure 4 Serial input / output test condition
<Test load>
No.A0119-17/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
tPIL (1) to (5)
tPIH (1) to (4)
Figure 5 Pulse input timing condition - 1
tPIL(6)
HS
0.75V
DD
0.25V
DD
tTLH
VS
tPIL(6)
more than ±1tCYC
Figure 6 Pulse input timing condition - 2
LC863864B
10kΩ
HS
HS
C536
Figure 7 Recommended Interface circuit
No.A0119-18/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
Noise filter
1µF
C-Video
CVIN
200Ω
1000pF
Coupling capacitor
Output impedance of C-Video before Noise filter should be less then 100Ω.
Figure 8 CVIN recommended circuit
100Ω
FILT
+
2.2µF
33000pF
1MΩ
-
Figure 9 FILT recommended circuit
Note : Place FILT parts on board as close to the microcontroller as possible.
S
Sr
P
P
SDA
SCL
tBUF
tF
tsp
tR
tHD ; STA
tHD ; STA
tLOW
tHIGH
tHD ; DAT
tSU ; DAT
tSU ; STA
tSU ; STO
S : start condition
P : stop condition
Sr : restart condition
tsp : Spike suppression
Figure 10 IIC timing
Standard mode : not exist
High speed mode : less than 50ns
No.A0119-19/20
LC863864B/56B/48B/40B/32B/28B/24B/20B/16B
No.A0119-20/20
PS
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