LC875BH4A(TQFP100) [ONSEMI]
IC,MICROCONTROLLER,8-BIT,CMOS,TQFP,100PIN,PLASTIC;
| 型号： | LC875BH4A(TQFP100) |
| 厂家： | 
ONSEMI |
| 描述： | IC,MICROCONTROLLER,8-BIT,CMOS,TQFP,100PIN,PLASTIC |
| 文件： | 总25页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7972
LC875BP4A
LC875BM2A
LC875BJ0A
LC875BH4A
CMOS IC
ROM 256K/224K/192K/176K byte, RAM 4096K byte on-chip
8-bit 1-chip Microcontroller
Overview
The LC875BP4A, LC875BM2A, LC875BJ0A, LC875BH4A is 8-bit single chip microcontroller with the following one-
chip features :
• CPU : Operable at a minimum bus cycle time of 100ns
• On-chip ROM Capacity : LC875BP4A 256K bytes
: LC875BM2A 224K bytes
: LC875BJ0A 192K bytes
: LC875BH4A 176K bytes
• On-chip RAM Capacity : 4K bytes
• Two high performance 16-bit timer/counters (can be divided into 8-bit timers)
• Four 8-bit timers with prescalers
• Timer for use as date/time clock
• Two synchronous serial I/O ports (with automatic block transmit/receive function)
• One asynchronous/synchronous serial I/O port
• Two UART ports (full duplex)
• 12-bit PWM × 4
• 12-channel × 8-bit AD converter
• High speed clock counter
• System clock divider
• 27-source 10-vectored interrupt system
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.00
92706 / 81205HKIM B8-7735 No.7972-1/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Features
Read Only Memory (ROM)
• 262144 × 8-bits (LC875BP4A)
• 229376 × 8-bits (LC875BM2A)
• 196608 × 8-bits (LC875BJ0A)
• 180224 × 8-bits (LC875BH4A)
Random Access Memory (RAM) : 4096 × 9-bit
Bus Cycle Time
• 100ns (10MHz)
Note : Bus cycle time indicates the speed to read ROM.
Minimum Instruction Cycle Time (tCYC)
• 300ns (10MHz)
Ports
• Input/output ports
Input/output programmable for each bit individually
64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn, S2Pn,
PWM0, PWM1, XT2)
16 (PEn, PFn)
8 (P0n)
Data direction programmable in two bits
Data direction programmable in nibble units
• Input ports
1 (XT1)
• Oscillator pins
• Reset pin
2 (CF1, CF2)
1 (RES)
• Power supply
8 (V 1 to 4, V 1 to 4)
SS DD
Timer
• Timer 0 : 16-bit timer/counter with capture register
Mode 0 :8-bit timer with 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels
Mode 1 :8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with 8-bit capture register)
Mode 2 :16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 :16-bit counter (with a 16-bit capture register)
• Timer 1 : 16-bit timer/counter that support PWM/ toggle output
Mode 0 :8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter
(with toggle outputs )
Mode 1 :8-bit PWM with an 8-bit prescaler × 2-channels
Mode 2 :16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(Toggle outputs also present at the lower-order 8-bits)
Mode 3 :16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8-bits can be used as PWM.)
• Timer 4 : 8-bit timer with a 6-bit prescaler
• Timer 5 : 8-bit timer with a 6-bit prescaler
• Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1. The clock is selectable from sub-clock (32.768kHz crystal oscillation), system clock or programmable
prescaler output of timer 0.
2. Interrupt are programmablein 5 different time schemes.
High Speed Clock Counter
1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2. Can generate output real time.
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LC875BP4A/875BM2A/875BJ0A/875BH4A
Serial Interface
• SIO 0 : 8-bit synchronous serial interface
1. LSB first/MSB first-function available
2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3. Consecutive automatic data communication (1 to 256-bits)
• SIO 1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
O
Mode 1 : Asynchronous serial I (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tCYC)
O
Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection)
• SIO2 : 8-bit synchronous serial interface
1. LSB-first
2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3. Consecutive automatic data communication (1 to 32 bytes)
UART :2-channels
1. Full duplex
2. 7/8/9 bit data bits selectable
3. 1stop bit
4. built-in baudrate generator
AD Converter
• 12-channel × 8-bit AD converter
PWM
• 4-channel × synchronous variable 12-bit PWM
Remote Receiver Circuit (share with P73/INT3/T0IN terminal)
• Noise rejection function (The filtering time of the noise rejection filter (1tCYC/32 tCYC/128 tCYC) can be switched
by program.)
Watchdog Ttimer
• External RC circuit is required.
• Interrupt or system reset is activated when the timer overflows.
Interrupts
• 27-source and 10-vectored interrupt function :
1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible.
During interrupt handling, an equal or lower level interrupt request is refused.
2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes
precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
Interrupt Signal
INT0
X or L
INT1
2
H or L
INT2/T0L/INT4
3
H or L
INT3/INT5/base timer
T0H
4
H or L
5
H or L
T1L/T1H
6
H or L
SIO0/UART1, 2 receive
SIO1/SIO2/UART1, 2 transmit
ADC/T6/T7/PWM4, PWM5
Port 0/T4/T5/PWM0, PWM1
7
H or L
8
H or L
9
H or L
10
• Priority Level : X > H > L
• For equal priority levels, vector with lowest address takes precedence.
No.7972-3/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Subroutine Stack Levels
• A maximum of 3072 levels (set stack inside RAM)
Multiplication and division
• 16-bits × 8-bits (5 instruction-cycle times)
• 24-bits × 16-bits (12 instruction-cycle times)
• 16-bits ÷ 8-bits (8 instruction-cycle times)
• 24-bits ÷ 16-bits (12 instruction-cycle times)
Oscillation Circuits
• Built-in RC oscillation circuit used for the system clock
• CF oscillation circuit used for the system clock
• Crystal oscillation circuit used for the system clock
System Clock Divider
• Operable on the lowest power consumption
• Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by
program (when using 10MHz main clock)
Standby Function
• HALT mode
The HALT mode stops program execution while the peripheral circuits keep operating and minimizes power
consumption. This operation mode can be released by a system reset or an interrupt request.
• HOLD mode
The HOLD mode stops program execution and all oscillation circuits : CF, RC and Crystal oscillations.
This mode can be released by the following conditions.
1. Supply "L" level to the reset terminal (RES)
2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4, INT5.
3. Supply an interrupt condition to Port 0.
• X’tal HOLD mode
The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer. The crystal
oscillator maintains its state at HOLD mode inception. This mode can be released by the following conditions.
1. Supply "L" level to the reset terminal (RES).
2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5.
3. Supply an interrupt condition to Port 0.
4. Supply an interrupt condition to the base timer circuit.
Shipping Form
• QFP100E (Lead Free Product)
• TQFP100 (Lead Free Product)
Development Tools
• Evaluation (EVA) chip : LC87EV690
• Emulator
: EVA62S + ECB876600D + SUB875200 + POD100QFP or POD100SQFP Type B
: ICE-B877300 + SUB875200 + POD100QFP or POD100SQFP Type B
No.7972-4/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Package Dimensions
unit : mm
3151A
Package Dimensions
unit : mm
3274
No.7972-5/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PB6
PB5
PB4
PB3
PB2
PB1
PB0
SI2P1/SI2/SB2
SI2P0/SO2
PF7
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PF6
PF5
PF4
PF3
LC875BP4A/
LC875BM2A/
LC875BJ0A/
LC875BH4A
V
V
3
PF2
SS
3
PF1
DD
PC7
PF0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
V
V
4
DD
4
SS
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
QIP100E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Top view
No.7972-6/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P36
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PWM1
SI2P3/SCK20
SI2P2/SCK2
SI2P1/SI2/SB2
SI2P0/SO2
PF7
PF6
PF5
PF4
V
V
3
PF3
SS
LC875BP4A/
LC875BM2A/
LC875BJ0A/
LC875BH4A
3
PF2
DD
PC7
PF1
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
PA3
PA4
PA5
PF0
V
V
4
DD
4
SS
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
TQFP100
P17/T1PWMH/BUZ
P16/T1PWML
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Top view
No.7972-7/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
PAD Coordinate Values
QIP
NAME
TQFP
98
99
100
1
QIP
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NAME
SI2P2/SCK2
SI2P3/SCK20
PWM1
TQFP
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
PA3
1
PA4
2
PA5
3
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
RES
PWM0
4
2
V
2
5
DD
3
V
SS
2
6
4
P00
P01
7
5
8
XT1/AN10
XT2/AN11
6
P02
9
7
P03
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
1
8
P04
SS
CF1
CF2
9
P05/CKO
P06/T6O
P07/T7O
P20/INT4/T1IN
P21/INT4/T1IN
P22/INT4/T1IN
P23/INT4/T1IN
P24/INT5/T1IN
P25/INT5/T1IN
P26/INT5/T1IN
P27/INT5/T1IN
P30/PWM4
P31/PWM5
P32/UTX1
P33/URX1
P34/UTX2
P35/URX2
P36
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
V
1
DD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
PE0
PB7
PB6
PE1
PB5
PE2
PB4
PE3
PB3
PE4
PB2
PE5
PB1
PE6
PB0
PE7
V
V
3
3
SS
V
V
4
4
SS
DD
PC7
DD
PF0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
PF1
PF2
PF3
PF4
PF5
PF6
PF7
SI2P0/SO2
SI2P1/SI2/SB2
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LC875BP4A/875BM2A/875BJ0A/875BH4A
System Block Diagram
IR
PLA
Interrupt Control
ROM
Standby Control
CF
RC
PC
Xtal
MRC
ACC
SIO0
SIO1
Bus Interface
Port 0
B Register
C Register
SIO2
Port 1
Timer 0
Timer 1
Timer 4
Timer 5
PWM0
PWM1
Base Timer
Port 3
ALU
Port 7
Port 8
PSW
RAR
RAM
ADC
INT0-3
Noise Rejection Filter
Port 2
INT4, 5
Stack Pointer
Port A
Watch Dog Timer
Timer 6
Timer 7
UART1
Port B
Port C
Port E
UART2
PWM5
Port F
PWM4
No.7972-9/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Pin Description
Name
I/O
-
Function description
Power supply pin (-)
Option
V
V
1, V
3, V
2
4
No
SS
SS
SS
SS
V
V
1, V
3, V
2
-
Power supply pin (+)
No
DD
DD
DD
DD
4
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
P00 to P07
• Port 0 interrupt input
• Pin functions
P05 : System clock output
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
• 8-bit I/O port
Port 1
I/O
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10 to P17
P10: SIO0 data output
P11 : SIO0 data input, bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input, bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/buzzer output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20 to P27
P20 to P23 : INT4 input/HOLD release input/timer 1 event input/timer 0L capture
input/timer 0H capture input
P24 to P27 : NT5 input/HOLD release input/timer 1 event input/timer 0L capture
input/timer 0H capture input
• Interrupt detection style
Rising/
Rising
Falling
H level
L level
falling
INT4
INT5
enable
enable
enable
enable
enable
disable
disable
disable
disable
enable
Port 3
I/O
• 7-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P36
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30 : PWM4 output
P31 : PWM5 output
P32 : UART1 transmit
P33 : UART1 receive
P34 : UART2 transmit
P35 : UART2 receive
Continued on next page.
No.7972-10/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Continued from preceding page.
Name
I/O
I/O
Function description
Option
Port 7
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P70 : INT0 input/HOLD release input/timer 0L capture input/output for watchdog timer
P71 : INT1 input/HOLD release input/timer 0H capture input
P72 : INT2 input/HOLD release input/timer 0 event input/timer 0L capture input
P73 : INT3 input with noise filter/timer 0 event input/timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
• AD converter input port : AN8 (P70), AN9 (P71)
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
• Other functions
P80 to P87
P80 to P87 : AD converter input port
• 6-bit I/O port
Port A
I/O
I/O
I/O
I/O
I/O
I/O
Yes
Yes
Yes
No
• I/O specifiable in 1-bit units
PA0 to PA5
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
Port B
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
PB0 to PB7
Port C
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
PC0 to PC7
Port E
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
PE0 to PE7
Port F
No
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 4-bit I/O port
PF0 to PF7
SIO2 Port
No
• I/O specifiable in 1-bit units
• Other functions
SI2P0 to SI2P3
SI2P0 : SIO2 data output
SI2P1 : SIO2 data input, bus input/output
SI2P2 : SIO2 clock input/output
SI2P3 : SIO2 clock output
PWM0
PWM1
O
O
• PWM0 output port
No
No
• General-purpose I/O available
• PWM1 output port
• General-purpose I/O available
Reset pin
RES
XT1
I
I
No
No
• Input terminal for 32.768kHz X'tal oscillation
• Other function
AN10 : AD converter input port
General input port
When not in use, connect terminal to V 1.
DD
XT2
I/O
• Output terminal for 32.768kHz X'tal oscillation
• Other function
No
AN11 : AD converter input port
General input port
When not in use, set as oscillation and leave terminal open
Input terminal for ceramic resonator
CF1
CF2
I
No
No
O
Output terminal for ceramic resonator
No.7972-11/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Port Output Configuration
Output configuration and pull-up resistor options are shown in the following table.
Input is possible even when a port is in output mode.
Terminal
Option applies to :
1 bit
Option
Output format
Pull-up resistor
Programmable (Note 1)
None
P00 to P07
1
2
1
2
CMOS
Nch-open drain
CMOS
P10 to P17
P20 to P27
P30 to P36
PA0 to PA5
PB0 to PB7
PC0 to PC7
PE0 to PE7
PF0 to PF7
P70
1 bit
1 bit
-
Programmable
Programmable
Nch-open drain
1
2
CMOS
Programmable
Programmable
Nch-open drain
None
CMOS
Programmable
-
-
-
-
None
None
None
None
Nch-open drain
CMOS
Programmable
Programmable
None
P71 to P73
P80 to P87
Nch-open drain
CMOS
SI2P0, SI2P2
SI2P3
None
PWM0, PWM1
SI2P1
-
None
CMOS (when used as general port)
Nch-open drain (when used for SIO2 data)
Input only
None
XT1
XT2
-
-
None
None
None
None
Output for 32.768kHz crystal oscillation
Nch-open drain (when in general-purpose output mode)
Note 1 Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07).
Note : To reduce V signal noise and to increase the duration of the backup battery supply,
DD
V
1, V 2, V 3 and V 4 should connect to each other and they should also be grounded.
SS SS SS SS
Example 1 : During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor.
Back-up
LSI
capacitor
V
V
V
V
1
2
3
4
DD
DD
DD
DD
Power
Supply
V
1 V 2 V 3V 4
SS SS SS SS
No.7972-12/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Example 2 : During backup in hold mode, output is not held high and its value in unsettled.
Back-up
capacitor
LSI
V
V
V
V
1
2
3
4
DD
DD
DD
DD
Power
Supply
V
1 V 2 V 3 V 4
SS SS SS SS
No.7972-13/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Absolute Maximum Ratings / Ta = 25°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
max
Parameter
Symbol
Pins
Conditions
V
[V]
DD
min
typ
unit
Supply voltage
V
max
V
V
1, V 2,
DD
V
1=V
2
DD
DD
DD
DD
DD
-0.3
+6.5
3, V
4
=V 3=V
DD
4
DD
DD
Input voltage
V (1)
XT1, XT2, CF1
PWM0, PWM1
-0.3
-0.3
V
+0.3
+0.3
I
DD
Output voltage
V
(1)
V
O
DD
DD
V
Input/output
voltage
VIO (1)
• Ports 0, 1, 2
• Ports 3, 7, 8
• Ports A, B, C, E, F
• SI2P00 to SI2P03
• PWM0, PWM1
• Ports 0, 1, 2, 3
• Ports A, B, C, E, F
• SI2P00 to SI2P03
• PWM0, PWM1
P71 to P73
-0.3
-10
V
+0.3
High
Peak
IOPH (1)
IOPH (2)
• CMOS output
• For each pin.
level
output
current
output
current
For each pin.
-5
-5
Total
Σ
IOAH (1)
IOAH (2)
P71 to P73
Total of all pins
Total of all pins
output
current
Σ
• Port 1
• PWM0, PWM1
• Port 3
-30
• SI2P00 to SI2P03
Ports 0, 2
Σ
Σ
Σ
IOAH (3)
IOAH (4)
IOAH (5)
Total of all pins
Total of all pins
Total of all pins
For each pin.
-20
-20
-20
Port B
Ports A, C
Low
Peak
IOPL (1)
• P02 to P07
level
output
current
• Ports 1, 2, 3
mA
output
current
• Ports A, B, C, E, F
• SI2P00 to SI2P03
• PWM0, PWM1
P00, P01
20
IOPL (2)
IOPL (3)
For each pin.
For each pin.
Total of all pins
Total of all pins
Total of all pins
30
5
Ports 7, 8
Port 7
Total
ΣIOAL (1)
ΣIOAL (2)
ΣIOAL (3)
15
15
output
current
Port 8
• PWM0, PWM1
• Port 3
40
• SI2P00 to SI2P03
Ports 0, 2, 3
Σ
Σ
Σ
Σ
Σ
IOAL (4)
IOAL (5)
IOAL (6)
IOAL (7)
IOAL (8)
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Ta= -30 to +70°C
80
40
Port B
Ports A, C
Port F
40
40
Port 1, E
QIP100E
TQFP100
70
Maximum power
consumption
Pd max
519
363
mW
°C
Operating temperature
range
Topr
Tstg
-30
-55
70
Storage temperature
range
125
No.7972-14/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Recommended Operating Range / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
DD
min
4.5
typ
max
unit
Operating
V
(1)
V
1=V
2
0.294
0.588
µ
s
s
≤
≤
tCYC
tCYC
≤
≤
200
200
µ
s
s
DD
DD
DD
5.5
supply voltage
range
=V 3=V
DD
4
DD
µ
µ
2.5
2.0
5.5
5.5
HOLD voltage
VHD
V
1=V
DD
2
RAM and register data are kept
in HOLD mode.
DD
=V 3=V
DD
4
DD
Input high voltage
V
(1)
• Ports 1, 2, 3
• SI2P00 to 03
• P71 to P73
2.5 to 5.5
2.5 to 5.5
IH
0.3V
DD
V
DD
+0.7
• P70 port input
/interrupt
V
(2)
• Ports 0, 8
0.3V
DD
IH
V
V
V
DD
DD
DD
• Ports A, B, C, E, F
Port 70 watchdog timer
+0.7
V
V
(3)
(4)
2.5 to 5.5
2.5 to 5.5
0.9V
IH
IH
DD
V
XT1, XT2, CF1,
RES
0.75V
DD
Input low
voltage
V
(1)
• Ports 1, 2, 3
• SI2P00 to 03
• P71 to P73
2.5 to 5.5
IL
0.1V
DD
+0.4
V
SS
• P70 port input
/interrupt
V
V
V
(2)
(5)
(6)
• Ports 0, 8
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
0.15V
DD
IL
IL
IL
V
V
V
SS
SS
SS
• Ports A, B, C, E, F
Port 70 Watchdog timer
+0.4
0.8V
DD
-1.0
XT1, XT2, CF1,
RES
0.25V
DD
Operation
cycle time
tCYC
4.5 to 5.5
2.5 to 5.5
4.5 to 5.5
0.294
0.588
200
200
µs
External system
clock frequency
FEXCF (1)
CF1
• Leave CF2 pin open
• System clock divider set to 1/1
• External clock
0.1
0.1
10
5
DUTY=50±5%
• Leave CF2 pin open
• System clock divider set to 1/1
• External clock
2.5 to 5.5
DUTY=50±5%
• Leave CF2 pin open
• System clock divider set to 1/2
• Leave CF2 pin open
• System clock divider set to 1/2
10MHz ceramic resonator
oscillation
4.5 to 5.5
2.5 to 5.5
4.5 to 5.5
0.2
0.1
20.4
10
MHz
Oscillation
frequency
Range
FmCF (1)
FmCF (2)
CF1, CF2
CF1, CF2
10
Refer to figure 1
(Note1)
5MHz ceramic resonator
oscillation
2.5 to 5.5
5
Refer to figure 1
FmRC
RC oscillation
2.5 to 5.5
2.5 to 5.5
0.3
1.0
50
2.0
FmMRC
Frequency variable RC
oscillation source oscillation
32.768kHz crystal resonator
oscillation Refer to figure 2
FsX’tal
XT1, XT2
2.5 to 5.5
32.768
kHz
Note 1 : The oscillation parameters are shown on Tables 1 and 2.
No.7972-15/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Electrical Characteristics / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
DD
min
typ
max
unit
Input high
I
(1)
IH
• Ports 0, 1, 2
• Ports 3, 7, 8
• Ports A, B, C
• SI2P00 to SI2P03
• RES
• Output disable
2.5 to 5.5
current
• Pull-up resistor OFF
• V =V
IN DD
(including the off-leak current
1
of the output Tr.)
• PWM0, PWM1
XT1, XT2
I
(2)
IH
• Using as an input port
2.5 to 5.5
1
• V =V
IN DD
I
I
(3)
IH
CF1
V
=V
2.5 to 5.5
2.5 to 5.5
15
IN DD
µ
A
Input low
current
(1)
IL
• Ports 0, 1, 2
• Ports 3, 7, 8
• Ports A, B, C, E, F
• SI2P00 to SI2P03
• RES
• Output disable
• Pull-up resistor OFF
• V =V
IN SS
(including the off-leak current
-1
-1
of the output Tr.)
• PWM0, PWM1
XT1, XT2
I
I
(2)
IL
• Using as an input port
2.5 to 5.5
• V =V
IN SS
(3)
IL
CF1
V =V
IN SS
2.5 to 5.5
4.5 to 5.5
-15
-1
Output high
voltage
V
(1)
• Ports 0, 1, 2, 3
• Ports A, B, C, E, F
• SI2P00 to SI2P03
Port 71, 72, 73
I
= -1.0mA
OH
OH
OH
V
DD
V
(2)
I
= -0.1mA
2.5 to 5.5
OH
V
-0.5
DD
V
V
V
V
V
(3)
(4)
(5)
(6)
(1)
I
I
I
I
I
= -1.5mA
= -6.0mA
= -1.6mA
= -1.0mA
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
2.5 to 5.5
4.5 to 5.5
V
-1
-1
OH
OH
OH
OH
OL
OH
OH
OH
OH
DD
PWM0, PWM1
P30, P31
V
DD
V
V
-0.4
DD
DD
(PWM4, 5 output mode)
V
-0.4
Output low
voltage
• Ports 0, 1, 2, 3
• Ports A, B, C, E, F
• SI2P00 to SI2P03
• PWM0, PWM1
P00, P01
=10mA
=1.6mA
=1.0mA
1.5
0.4
OL
OL
OL
V
V
(2)
(3)
I
I
4.5 to 5.5
2.5 to 5.5
OL
OL
0.4
1.5
0.4
V
V
(4)
(5)
I
=30mA
=1.0mA
=0.9V
4.5 to 5.5
2.5 to 5.5
2.5 to 5.5
OL
OL
OL
OL
Ports 7, 8
I
Pull-up resistor
Rpu
• Ports 0, 1, 2, 3
• Port 7
V
OH
DD
15
40
70
k
Ω
• Ports A, B, C, E, F
• RES
Hysteresis
voltage
VHIS
2.5 to 5.5
• Port 1
• Port 2
0.1V
V
DD
• Port 3
• Port 7
• SIP00 to SIP03
All pins
Pin capacitance
CP
• All pins except the measured
2.5 to 5.5
terminal : V =V
IN SS
• f=1MHz
10
pF
• Ta=25°C
No.7972-16/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Serial Input/Output Characteristics / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Cycle
tSCK (1)
SCK0 (P12),
SI2P2
Refer to figure 6
2.5 to 5.5
2
Low level
tSCKL (1)
tSCKLA (1)
tSCKH (1)
tSCKHA (1)
1
1
1
pulse width
High level
pulse width
4(SIO0)
5(SIO2)
tCYC
Cycle
tSCK (2)
SCK1 (P15)
Refer to figure 6
2.5 to 5.5
2
Low level
pulse width
High level
pulse width
Cycle
tSCKL (2)
1
tSCKH (2)
1
tSCK (3)
SCK0 (P12),
SI2P2
• CMOS output
2.5 to 5.5
4/3
• Refer to figure 6
Low level
tSCKL (3)
tSCKLA (2)
1/2
3/4
SI2P3
pulse width
SCK0 (P12)
SIO0
SI2P2, SI2P3
SIO2
1
1/2
2
tSCK
High level
tSCKH (3)
pulse width
tSCKHA (2)
SCK0 (P12)
SIO0
SI2P2, SI2P3
SIO2
7/4
Cycle
tSCK (4)
SCK1 (P15)
• CMOS output
2.5 to 5.5
2
tCYC
tSCK
• Refer to figure 6
Low level
pulse width
tSCKL (4)
1/2
1/2
High level
tSCKH (4)
tsDI
pulse width
Data set-up time
SB0 (P11),
SB1 (P14),
SI2P1
• Data set-up to SI0CLK
• Data hold from SI0CLK
• Refer to figure 6
2.5 to 5.5
2.5 to 5.5
0.03
0.03
Data hold time
thDI
SI0
SI1
µs
Output delay time
tdD0
SO0 (P10),
SO1 (P13),
SB0 (O11),
SB1 (P14),
SI2P0,
• Data hold from SI0CLK
• Time delay from SI0CLK
trailing edge to the SO
data change in the open
drain
1/3tCYC
+0.05
SI2P1
• Refer to figure 6
No.7972-17/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Pulse Input Conditions / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
High/low level
pulse width
tPIH (1)
tPIL (1)
INT0 (P70),
• Interrupt acceptable
• Timer 0 and 1 event
input acceptable
2.5 to 5.5
INT1 (P71),
INT2 (P72)
1
INT4 (P20 to P23)
INT5 (P24 to P27)
INT3 (P73)
tPIH (2)
tPIL (2)
• Interrupt acceptable
• Timer 0 event input
acceptable
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
(The noise rejection clock
is selected to 1/1.)
INT3 (P73)
2
tCYC
tPIH (3)
tPIL (3)
• Interrupt acceptable
• Timer 0 event input
acceptable
(The noise rejection clock
is selected to 1/32.)
INT3 (P73)
64
tPIH (4)
tPIL (4)
• Interrupt acceptable
• Timer 0 event input
acceptable
(The noise rejection clock
is selected to 1/128.)
RES
256
200
tPIL (5)
Reset acceptable
µs
AD Converter Characteristics / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
AN0 (P80)
to AN7 (P87)
AN8 (P70)
AN9 (P71)
AN10 (XT1)
AN11 (XT2)
3.0 to 5.5
3.0 to 5.5
4.5 to 5.5
8
Absolute precision
Conversion time
ET
(Note 2)
AD conversion time=32 × tCYC
(ADCR2=0) (Note 3)
±1.5
LSB
TCAD
15.10
(tCYC=
0.588 s)
97.92
(tCYC=
µ
3.06µs)
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
31.36
97.92
(tCYC=
(tCYC=
0.980
µ
s)
3.06µs)
µs
AD conversion time=64 × tCYC
18.82
97.92
(ADCR2=1)
(Note 3)
(tCYC=
(tCYC=
0.294
µ
s)
1.53µs)
62.72
97.92
(tCYC=
(tCYC=
0.980
µ
s)
1.53
µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
1
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
µA
VAIN=V
SS
-1
Note 2 : Absolute precision excludes the quantizing error (±1/2 LSB).
Note 3 : The conversion time is the time from executing the AD conversion instruction to setting the complete digital
conversion value in the register.
No.7972-18/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Current Dissipation Characteristics / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Current drain
during basic
operation
IDDOP (1)
V
1
• FmCF=10MHz by ceramic resonator
• FmX’tal=32.768kHz by crystal oscillation
• System clock : CF oscillation (10MHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/1 divided
4.5 to 5.5
2.5 to 5.5
4.5 to 5.5
DD
=V
=V
=V
2
3
4
DD
DD
DD
10
15
16
(Note 4)
IDDOP (2)
• CF1=20MHz by external clock
• FmX’tal=32.768kHz by crystal oscillation
• System clock : CF1 oscillation (20MHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/2 divided
10.5
IDDOP (3)
• FmCF=5MHz by ceramic resonator
• FmX'tal=32.768kHz by crystal oscillation
• System clock : CF oscillation (5MHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/1 divided
5.5
3
8
6
mA
IDDOP (4)
IDDOP (5)
2.5 to 4.5
4.5 to 5.5
• FmCF=0Hz
(when oscillation stops)
0.7
0.3
4
• FmX'tal=32.768kHz by crystal oscillation
• System clock : RC oscillation
• Frequency variable RC oscillation stops
• 1/2 divided
IDDOP (6)
IDDOP (7)
2.5 to 4.5
4.5 to 5.5
1.5
• FmCF=0Hz
(when oscillation stops)
2
0.7
27
6
3.5
60
• FmX'al=32.768kHz by crystal oscillation
• System clock : 1MHz with frequency
variable RC oscilatin
IDDOP (8)
IDDOP (9)
2.5 to 5.5
4.5 to 5.5
• Internal RC oscillation stops
• 1/2 divided
• FmCF=0Hz
(when oscillation stops)
• FmX'al=32.768kHz by crystal oscillation
• System clock : X'tal oscillation (32.768kHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/2 divided
µA
IDDOP (10)
2.5 to 4.5
12
40
Note 4 : The current of the output transistors and pull-up MOS transistors are excluded.
Continued on next page.
No.7972-19/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Continued from preceding page.
Limits
typ
Parameter
Symbol
Pins
Conditions
V
[V]
min
max
unit
DD
Current drain in
HALT mode
(Note 4)
IDDHALT (1)
IDDHALT (2)
IDDHALT (3)
V
1
• HALT mode
4.5 to 5.5
4.5 to 5.5
4.5 to 6.0
DD
=V
=V
=V
2
3
4
• FmCF=10MHz by ceramic resonator
• FmX’tal=32.768kHz by crystal oscillation
• System clock : CF oscillation (10MHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/1 divided
DD
DD
DD
2.5
5
• HALT mode
• CF1=20MHz by external clock
• FmX’tal=32.768kHz by crystal oscillation
• System clock : CF1 oscillation (20MHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/2 divided
3.2
6
• HALT mode
• FmCF=5MHz by ceramic resonator
• FmX’tal=32.768kHz by crystal oscillation
• System clock : CF oscillation (5MHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/1 divided
1.5
0.7
3
1.5
1
mA
IDDHALT (4)
IDDHALT (5)
IDDHALT (6)
2.5 to 4.5
4.5 to 5.5
2.5 to 4.5
• HALT mode
• FmCF=0Hz
0.3
(when oscillation stops)
• FmX’tal=32.768kHz by crystal oscillation
• System clock : RC oscillation
• Frequency variable RC oscillation stops
• 1/2 divided
0.15
0.5
IDDHALT (7)
• HALT mode
4.5 to 5.5
• FmCF=0Hz
1.6
0.6
16
5
2.5
1.8
40
(when oscillation stops)
• FmX'tal=32.768kHz by crystal oscillation
• System clock : 1MHz with frequency
variable RC oscilatin
IDDHALT (8)
IDDHALT (9)
2.5 to 4.5
4.5 to 5.5
• Internal RC oscillation stops
• 1/2 divided
• HALT mode
• FmCF=0Hz
(when oscillation stops)
• FmX'tal=32.768kHz by crystal oscillation
• System clock : X'tal oscillation (32.768kHz)
• Internal RC oscillation stops
• Frequency variable RC oscillation stops
• 1/2 divided
IDDHALT (10)
IDDHOLD (1)
2.5 to 4.5
4.5 to 5.5
25
µA
Current drain
during HOLD
mode
V
1
1
• HOLD mode
DD
0.015
0.001
10
5
• CF1=V
DD
or leave it open
IDDHOLD (2)
IDDHOLD (3)
2.5 to 4.5
4.5 to 5.5
(when using external clock)
Current drain
during time-base
clock HOLD mode
V
• Time-base clock HOLD mode
DD
14
35
20
• CF1=V
DD
or leave it open
(when using external clock)
IDDHOLD (4)
2.5 to 4.5
3.8
• FmX'tal=32.768kHz by crystal oscillation
Note 4 : The current of the output transistors and pull-up MOS transistors are excluded.
No.7972-20/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
UART (full duplex) Operating Conditions / Ta = -30°C to +70°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
Limits
SS
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Clock rate
UBR, UBR2
UTX1 (P32),
RTX1 (P33),
UTX2 (P33),
RTX2 (P34)
2.5 to 5.5
16/3
8192/3
tCYC
Data length :
Stop bits :
7, 8 and 9 bits (LSB first)
1-bit
Non
Parity bits :
Continuous 8-bit data transmit mode (first transmit data = 55H)
Start bit
Stop bit
Beginning of
transmission
End of
transmittion
Transmit data (LSB first)
UBR,
UBR2
Continuous 8-bit data receive mode (first transmit data = 55H)
Stop bit
Start bit
Received data (LSB first)
Beginning of
reception
End of
reception
UBR,
UBR2
No.7972-21/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions :
1. Using the standard oscillation evaluation board SANYO has provided.
2. Using the external peripheral parts with the indicated value.
3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer.
Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator
Recommended circuit
Oscillation stabilizing
Operating supply
voltage range
parameters
time
Frequency
Manufacturer
Oscillator
Note
C1
C2
Rd1
typ
max
CSLS10M0G53-R0
CSTLS10M0G52-B0
CSTLS5M00G53-R0
CSTLS5M00G53-B0
(10pF)
(10pF)
(15pF)
(15pF)
(10pF)
(10pF)
(15pF)
(15pF)
150
100
470
470
Ω
Ω
Ω
Ω
4.5 to 5.5V
4.5 to 5.5V
2.5 to 5.5V
2.5 to 5.5V
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
10MHz
5MHz
MURATA
MURATA
*The oscillation stabilizing time is a period until the oscillation becomes stable after V
minimum operating voltage. (Refer to Figure 4)
becomes higher than
DD
Subsystem Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions :
1. Using the standard oscillation evaluation board SANYO has provided.
2. Using the external peripheral parts with the indicated value.
3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer.
Table 2. Recommended circuit parameters for the subsystem clock using the crystal oscillation
Recommended circuit
Parameters
Oscillation
Operating supply
voltage range
stabilizing time
Frequency
32.768kHz
Manufacturer
Oscillator
MC-306
Note
C3
C4
Rf
Rd2
typ
max
SEIKO EPSON
15pF 15pF OPEN 390k
Ω
2.5 to 5.5V
*The oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which
starts the sub-clock oscillator or after releasing a HOLD mode. (Refer to Figure 4)
Notes : Since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as
close to the oscillation pins as possible, using the shortest possible pattern length.
XT1
XT2
CF1
CF2
Rd1
C2
Rf
Rd2
C4
CF
C1
C3
X’tal
Figure 1 Ceramic oscillation circuit
Figure 2 Crystal oscillation circuit
0.5V
DD
Figure 3 AC timing point
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V
V
DD
DD
Power Supply
limit
GND
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution
Reset time and oscillation stabilizing time
HOLD release signal
HOLD release signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stabilizing time
Figure 4 Oscillation stabilizing time
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V
DD
R
C
(Note)
RES
Select C
and R value to assure that at least
RES
RES
200µs reset time is generated after the V
higher than the minimum operating voltage.
becomes
RES
DD
RES
Figure 5 Reset circuit
SI0CLK :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAIN :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DATAOUT :
Data RAM
transmission period
(only SIO0, 2)
tSCK
tSCKH
thDI
tSCKL
SI0CLK :
DATAIN :
tsDI
tdDO
DATAOUT :
Data RAM
transmission period
(only SIO0, 2)
tSCKLA
tSCKHA
SI0CLK :
DATAIN :
tsDI
thDI
tdDO
DATAOUT :
Figure 6 Serial input/output test condition
tPIL
tPIH
Figure 7 Pulse input timing condition
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Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of August, 2005. Specifications and information herein are subject
to change without notice.
No.7972-25/25
PS
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