LC877808A(QIP64E) [ONSEMI]
Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PQFP64,;
| 型号： | LC877808A(QIP64E) |
| 厂家： | 
ONSEMI |
| 描述： | Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PQFP64, 微控制器 |
| 文件： | 总21页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0635A
LC877816A
LC877812A
LC877808A
CMOS IC
16K/12K/8K-byte ROM and 512-byte RAM
8-bit 1-chip Microcontroller
Overview
The LC877816A/12A/08A is an 8-bit single chip microcontroller with the following on-chip functional blocks:
• CPU: operable at a minimum bus cycle time of 250ns
• ROM: 16 K/12K/8K bytes
• RAM: 512 × 9 bits
• LCD controller/driver
• 16bit timer × 2ch + 8bit timer × 1ch or more
• Synchronous serial I/O port (with automatic block transmit/receive function)
• Asynchronous/synchronous serial I/O port
• System clock divider
• 8-bit AD converter × 9-channel
• 17-source 10-vectored interrupt system
• Power save mode
All of the above functions are fabricated on a single chip.
Features
ROM
• 16384 × 8 bits
• 12288 × 8 bits
• 8192 × 8 bits
RAM
• 512 × 9 bits
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.01
82008HKIM 20071003-S00010 No.A0635-1/21
LC877816A/12A/08A
Minimum Bus Cycle Time
• 250ns (4MHz)
Note: The bus cycle time indicates ROM read time.
Minimum Instruction Cycle Time (tCYC)
• 750ns (4MHz)
Power Save Mode
• Power save mode is available, when system clock is RC oscillation or crystal oscillation.
Ports
• Input/output ports
Data direction programmable for each bit individually:
12 (P1n, P70 to P73)
8 (P0n)
Data direction programmable in nibble units:
(When N-channel open drain output is selected, data can be input in bit units.)
• LCD ports
Segment output:
Common output:
Bias terminals for LCD driver
Other functions
24 (S00 to S23)
4 (COM0 to COM3)
5 (V1 to V3, CUP1, CUP2)
Input/output ports:
• Oscillator pins:
• Reset pin:
8(PCn)
4 (CF1, CF2, XT1, XT2)
1 (
RES
)
• Power supply:
4 (V 1 to 2, V 1 to 2)
SS DD
1 (VDC)
LCD Controller
• Seven display modes are available.
• Segment output (S16 to S23) can be switched to general purpose input/output ports.
• Duty: 1/3duty, 1/4duty
• Bias: 1/2bias, 1/3bias
• LCD power
1) 1/3bias V1: 1.2V to 1.8V
V2: 2.4V to 3.6V
V3: 3.6V to 5.4V
2) 1/2bias V1: 1.2V to 1.8V
V2: 2.4V to 3.6V
V3: 2.4V to 3.6V
(connect V2 and V3)
Timers
• Timer 0: 16 bit timer/counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register
+ 8 bit counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
• Timer 1: PWM/16 bit timer/counter with toggle output function
Mode 0: 2 channel 8 bit timer/counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer/counter (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Timer 6: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with 6-bit prescaler (with toggle output)
Continued on next page.
No.A0635-2/21
LC877816A/12A/08A
Continued from preceding page.
• Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
SIO
• SIO0: 8 bit synchronous serial interface
1) LSB first/MSB first is selectable
2) Internal 8 bit baud rate generator (fastest clock period 4/3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
• SIO1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial I/O (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial I/O (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
AD Converter:
• 8 bits × 9 channels
Remote Control Receiver Circuit (connected to P73/INT3/T0IN terminal)
• Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC)
Watchdog Timer
• Watchdog timer can produce interrupt or system reset.
• Watchdog timer has two types.
1) Use an external RC circuit
2) Use the microcontroller’s base timer
Interrupts
• 17 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector Address
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
1
00003H
INT0
2
0000BH
00013H
INT1
3
INT2/T0L
4
0001BH
00023H
INT3/Base timer
T0H
5
6
0002BH
00033H
T1L/T1H
SIO0
7
8
0003BH
00043H
SIO1
9
ADC/T6/T7
Port 0/T4/T5
10
0004BH
• Priority levels X > H > L
• For equal priority levels, vector with lowest address takes precedence.
Subroutine Stack Levels
• 256 levels maximum (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
No.A0635-3/21
LC877816A/12A/08A
Oscillation Circuits
• On-chip RC oscillation for system clock use.
• CF oscillation (4MHz) for system clock use. (Rf built in)
• Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in)
System Clock Divider Function
• Low power consumption operation is available
• Minimum instruction cycle time (0.75μs, 1.5μs, 3μs, 6μs, 12μs, 24μs, 48μs, 96μs, 192μs can be switched by
program (when using 4MHz main clock)
Standby Function
• HALT mode: HALT mode is used to reduce power consumption. During the HALT mode, program execution is
stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.)
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
• HOLD mode: HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are
stopped.
1) CF, RC and crystal oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
• X'tal HOLD mode: X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
(4) Base-timer interrupt
Development Tools
• On chip debugger (LC87F7032A)
LC87F7032A and LC877816A differ in following points.
When LC87F7032A is power save mode, Current consumption doesn’t decrease.
When LC87F7032A is power save mode, X’tal voltage level doesn’t change.
LC87F7032A has P2 registers (P2, P2DDR). But, LC877816A doesn’t have them.
Package Form
• ΤQFP64J(7×7): Lead-free type
• QIP64E(14×14): Lead-free type
No.A0635-4/21
LC877816A/12A/08A
Package Dimensions
unit : mm (typ)
3289
9.0
7.0
48
33
49
32
17
64
1
16
0.125
0.4
0.16
(0.5)
SANYO : TQFP64J(7X7)
Package Dimensions
unit : mm (typ)
3159A
17.2
14.0
48
33
32
49
64
17
1
16
0.8
0.35
0.15
(1.0)
SANYO : QIP64E(14X14)
No.A0635-5/21
LC877816A/12A/08A
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RES
XT1
XT2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S07
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
S06
S05
S04
V
1
SS
S03
CF1
CF2
S02
S01
V
1
DD
LC877816A
LC877812A
LC877808A
S00
P00/AN0
P01/AN1
COM3
COM2
COM1
COM0
V3
P02/AN2
P03/AN3
P04/AN4
P05/CKO/DBGP0
P06/T6O/DBGP1
P07/T7O/DBGP2
NC
V2
V1
VDC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Top view
SANYO: TQFP64J(7×7) “Lead-free Type”
SANYO: QIP64E(14×14) “Lead-free Type”
No.A0635-6/21
LC877816A/12A/08A
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF
RC
ROM
X’tal
PC
SIO0
SIO1
Bus interface
Port 0
ACC
B Register
C Register
Timer 0
Timer 1
Port 1
Port 7
ADC
Timer 4
Timer 5
ALU
Timer 6
PSW
RAR
RAM
INT0 to 3
Noise rejection filter
Timer 7
Base timer
LCD controller
Stack pointer
Watchdog timer
No.A0635-7/21
LC877816A/12A/08A
Pin Description
Pin name
I/O
Function
Option
No
V
V
1, V
2
-
-
- Power supply
+ Power supply
+ Power supply
SS
SS
1, V
2
No
DD
DD
VDC
-
No
CUP1, CUP2
-
• Capacitor connecting terminals for step-up/step-down
No
PORT0
I/O
• 8bit input/output port
Yes
P00 to P07
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• Other pin functions
Input for ADC channel (AN0 to AN4)
P05: Clock output (system clock/subclock)
When it’s LC87F7032A, P05 uses as DBGP0.
P06: Timer 6 toggle output
When it’s LC87F7032A, P06 uses as DBGP1.
P07: Timer 7 toggle output
When it’s LC87F7032A, P07 uses as DBGP2.
• 8bit input/output port
PORT1
I/O
Yes
P10 to P17
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10: SIO0 data output
P11: SIO0 data input or bus input/output
P12: SIO0 clock input/output
P13: IO1 data output
P14: SIO1 data input or bus input/output
P15: SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
• 4bit Input/output port
PORT7
I/O
No
P70 to P73
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/output for watchdog timer/AN5
P71: INT1 input/HOLD release input/Timer 0H capture input/AN6
P72: INT2 input/HOLD release input/timer 0 event input/Timer 0L capture input/AN7
P73: INT3 input (noise rejection filter attached)/timer 0 event input/Timer 0H capture input/AN8
Input for ADC channel (AN5 to AN8)
• Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
S0 to S15
O
• Segment output for LCD
• Segment output for LCD
No
No
S16/PC0 to
S23/PC7
I/O
• Can be used as general purpose input/output port (PC)
• Common output for LCD
COM0 to COM3
O
No
No
V1 to V3
I/O
• LCD output bias power supply
• Capacitor connecting terminals for step-up/step-down
• Reset terminal
RES
XT1
I
I
No
No
• Input for 32.768kHz crystal oscillation
• When not in use, connect to V
2
DD
XT2
CF1
CF2
I/O
I
• Output for 32.768kHz crystal oscillation
No
No
No
• When not in use, set to oscillation mode and leave open
• Input terminal for ceramic oscillator
• When not in use, connect to V
2
DD
O
• Output terminal for ceramic oscillator
• When not in use, leave open
No.A0635-8/21
LC877816A/12A/08A
Port Output Types
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
P00 to P07
1
2
CMOS
Programmable(Note 1)
No
Nch-open drain
CMOS
P10 to P17
1 bit
1
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
Nch-open drain
CMOS
P70
-
-
-
No
No
1
P71 to P73
S16(PC0) to
S23(PC7)
CMOS
2
Pch-open drain
Nch-open drain
3
Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
*1: Connect as follows to reduce noise on V
.
DD
V
1 and V 2 must be connected together and grounded.
SS SS
LSI
V
1
2
DD
Power
supply
V
DD
V1
V2
V3
CUP1
CUP2
VDC
V
1 V
2
SS
SS
Back up capacitors *2
*2: The power supply for the internal memory is VDC. V 1 and V 2 are used as the power supply for ports.
DD DD
When V 1 and V 2 are not backed up, the port level does not become “H” even if the port latch is in the “H”
DD DD
level. Therefore, when V 1 and V 2 are not backed up and the port latch is “H” level, the port level is unstable
DD DD
in the HOLD mode, and the back up time becomes shorter because the through current runs from V
to GND in
DD
the input buffer. If V 1 and V 2 are not backed up, output “L” by the program or pull the port to “L” by the
DD DD
external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is
prevented.
No.A0635-9/21
LC877816A/12A/08A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
+4.3
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
V
DD
Supply voltage
V
max
V
1, V 2, V2
V 1=V 2=V2
DD DD
DD
DD
DD
Supply voltage
For LCD
VLCD
V1
V2
V3
-0.3
-0.3
-0.3
-0.3
-0.3
1/2 V
DD
DD
DD
V
3/2 V
RES
XT1, CF1,
Input voltage
V
I
V
+0.3
DD
DD
Input/Output voltage
V
(1)
IO
• Ports 0, 1, 7, C
Ports 0, 1, 7, C
V
+0.3
Peak output
current
IOPH(1)
• CMOS output selected
• Current at each pin
-4
Total output
current
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
IOPL(1)
Port 7
Port 0
Port 1
Port C
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Current at each pin
-10
-25
-25
-15
mA
Peak output
current
Ports 02 to 07
Port 1, 7, C
Port 00, 01
6
IOPL(2)
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Ta=-30 to +70°C
15
10
Total output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Pd max
Port 7
Port 0
35
Port 1
25
Port C
15
Allowable power
dissipation
TQFP64J(7×7)
QIP64E(14×14)
200
420
mW
Operating ambient
temperature
Topr
Tstg
-30
-55
+70
°C
Storage ambient
temperature
+125
Note 1-1: The average current per applicable pin must not exceed 1mA
No.A0635-10/21
LC877816A/12A/08A
Allowable Operating Conditions at Ta = -30°C to +70°C, V 1 = V 2 = 0V
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
min
typ max
unit
DD
Operating
V
V
V
V
(1)
V
1=V 2=V2
0.37μs≤tCYC≤200μs
0.75μs≤tCYC≤200μs
2.25μs≤tCYC≤200μs
4.28μs≤tCYC≤200μs
3.0
3.6
3.6
3.6
3.6
DD
DD
DD
supply voltage
range
Normal mode
(2)
(3)
(4)
2.4
3.0
2.4
DD
DD
DD
V
=V 2=V2
DD1 DD
Power save mode
Supply
VHD
V
1=V 2=V2
DD DD
Keep RAM and register data in
HOLD mode.
voltage range
in Hold mode
Input high
voltage
2.2
3.6
V
(1)
• Ports 1
Output disable
IH
• P71 to P73
• Port 70
0.3V
DD
2.4 to 3.6
2.4 to 3.6
V
V
DD
+0.7
input/interrupt
• Ports 0, C
V
V
(2)
Output disable
Output disable
0.3V
DD
IH
IH
IH
V
DD
+0.7
(3)
Port 70
2.4 to 3.6
2.4 to 3.6
0.9V
DD
V
V
DD
Watchdog timer
RES
V
V
(4)
XT1, CF1,
• Ports 1
0.75V
DD
DD
Input low
Voltage
(1)
Output disable
IL
• P71 to P73
• Port 70
2.4 to 3.6
V
0.2V
SS
DD
input/interrupt
• Ports 0, C
V
(2)
Output disable
Output disable
2.4 to 3.6
2.4 to 3.6
V
V
V
0.2V
0.8V
IL
SS
SS
SS
DD
DD
V
(3)
Port 70
IL
Watchdog timer
-1.0
RES
V
(4)
XT1, CF1,
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
0.25V
DD
IL
Operation
cycle time
tCYC
Power save mode
2.25
4.28
200
μs
(Note 2-1)
200
4
External
FEXCF(1)
CF1
• CF2 open
system clock
frequency
• System clock divider:1/1
• External clock DUTY=50 ± 5%
• Normal mode
2.4 to 3.6
0.1
MHz
Oscillation
frequency
range
FmCF
CF1, CF2
XT1, XT2
4MHz ceramic resonator
oscillation
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
4
MHz
kHz
kHz
See fig. 1
(Note 2-2)
FmRC
FsX’tal
RC oscillation
300
500
700
V
=3.0V, Ta=25°C
DD
32.768kHz crystal resonator
oscillation
32.768
See fig. 2
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-2: See Table 1 and 2 for the oscillation constants.
No.A0635-11/21
LC877816A/12A/08A
Electrical Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High level
I
(1)
• Ports 0, 1, 7
• Port C
• Output disabled
IH
input current
• Pull-up resister OFF.
RES
•
• V =V
IN DD
2.4 to 3.6
1
(including OFF state leak current of
the output Tr.)
I
(2)
(3)
XT1, XT2
CF1
When configured as an input port
IH
2.4 to 3.6
2.4 to 3.6
1
8
V
=V
IN DD
I
I
V
=V
IH
IN DD
μA
Low level
(1)
• Ports 0, 1, 7
• Port C
• Output disabled
IL
input current
• Pull-up resister OFF.
RES
•
• V =V
IN SS
2.4 to 3.6
-1
(including OFF state leak current of
the output Tr.)
I
I
(2)
XT1, XT2
CF1
When configured as an input port
IL
IL
2.4 to 3.6
-1
-8
V
V
=V
IN SS
(3)
=V
2.4 to 3.6
3.0 to 3.6
IN SS
High level
output
V
Ports 0, 1, 7
CMOS
I
=-0.4mA
OH
V
V
V
-0.4
-0.4
-0.4
OH(1)
DD
DD
DD
I
=-0.2mA
OH
2.4 to 3.6
voltage
output option
Port C
V
V
(2)
I
I
I
I
I
I
I
=-0.1mA
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
2.4 to 3.6
OH
OH
Low level
output
(1)
OL
Ports 0, 1, 7
=1.6mA
=0.8mA
=5.0mA
=2.5mA
=0.1mA
0.4
0.4
0.4
0.4
0.4
OL
OL
OL
OL
OL
voltage
V
(2)
OL
P00, P01
V
V
(3)
OL
Port C
LCD output
voltage
VODLS
VODLC
Rpu
S0 to S23
=0mA
O
V1, V2, V3
2.4 to 3.6
2.4 to 3.6
0
0
±0.2
±0.2
200
regulation
LCD level output
COM0 to COM3
• Ports 0, 1, 7
• Ports 1, 7
I =0mA
O
V1, V2, V3
LCD level output
Resistance
of pull-up
MOS Tr.
Hysterisis
voltage
V
=0.9V
OH
DD
2.4 to 3.6
2.4 to 3.6
25
50
kΩ
VHYS
CP
0.1
DD
V
RES
•
×V
Pin
All pins
• All other terminals connected to
capacitance
V
.
SS
2.4 to 3.6
10
pF
• F=4MHz
• Ta=25°C
No.A0635-12/21
LC877816A/12A/08A
Serial I/O Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = 0V
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
See Fig. 6.
V
min
typ
max
unit
DD
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.4 to 3.6
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.4 to 3.6
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
0.03
0.03
• See Fig. 6.
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
• (Note 4-1-3)
(1/3)tCYC
+0.15
2.4 to 3.6
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0635-13/21
LC877816A/12A/08A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
See Fig. 6.
V
min
typ
max
unit
DD
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.4 to 3.6
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.4 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
2.4 to 3.6
2.4 to 3.6
0.03
0.03
• See Fig. 6.
Data hold time
thDI(2)
tdD0(4)
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
SIOCLK.
μs
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.4 to 3.6
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -30°C to +70°C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
tCYC
μs
DD
High/low
tPIH(1)
tPIL(1)
INT0(P70),
• Condition that interrupt is accepted
• Condition that event input to timer
0 is accepted
level pulse
width
INT1(P71),
INT2(P72)
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
1
tPIH(2)
tPIL(2)
INT3(P73)
• Condition that interrupt is accepted
• Condition that event input to timer
0 is accepted
(Noise rejection
ratio is 1/1.)
INT3(P73)
2
tPIH(3)
tPIL(3)
• Condition that interrupt is accepted
• Condition that event input to timer
0 is accepted
(Noise rejection
ratio is 1/32.)
INT3(P73)
64
tPIH(4)
tPIL(4)
• Condition that interrupt is accepted
• Condition that event input to timer
0 is accepted
(Noise rejection
ratio is 1/128.)
RES
2.4 to 3.6
2.4 to 3.6
256
200
tPIL(5)
• Condition that reset is accepted
No.A0635-14/21
LC877816A/12A/08A
AD Converter Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P00) to
AN4(P04),
AN5(P70) to
AN8(P73)
2.4 to 3.6
2.4 to 3.6
8
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
1.5
LSB
tCAD
AD conversion time=32×tCYC
(ADCR2=0) (Note 6-2)
Normal mode
22.4
640
(tCYC=
20μs)
640
3.0 to 3.6
2.4 to 3.6
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
(tCYC=
0.70μs)
128
(tCYC=
4.00μs)
128
(tCYC=
20μs)
640
AD conversion time=32×tCYC
(ADCR2=0) (Note6-2)
Power save mode
(tCYC=
4.00μs)
44.8
(tCYC=
20μs)
1280
μs
AD conversion time=64×tCYC
(When ADCR2=1) (Note 6-2)
Normal mode
(tCYC=
0.70μs)
256
(tCYC=
20μs)
1280
(tCYC=
4.00μs)
256
(tCYC=
20μs)
1280
AD conversion time=32×tCYC
(ADCR2=0) (Note6-2)
Power save mode
2.4 to 3.6
2.4 to 3.6
(tCYC=
4.00μs)
(tCYC=
20μs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.4 to 3.6
2.4 to 3.6
1
μA
VAIN=V
SS
-1
Note 6-1: The quantization error ( 1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0635-15/21
LC877816A/12A/08A
Consumption Current Characteristics at Ta = -30°C to +70°C, V 1 = V 2 = 0V
SS
SS
Specification
Pins/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Current
IDDOP(1)
V
V
1=
2=
• FmCF=4MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
• Divider: 1/1
DD
consumption
during normal
operation
DD
V2
2.4 to 3.6
1100
3200
(Note 7-1)
• Normal mode
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Divider: 1/1
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
150
50
600
225
180
• Normal mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Divider: 1/1
• Power save mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Divider: 1/2
40
• Power save mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
15
2.5
1.5
60
17
15
• Normal mode
IDDOP(6)
IDDOP(7)
IDDHALT(1)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
μA
• Power save mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/2
• Power save mode
Current
HALT mode
consumption
during HALT
mode
• FmCF=4MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
460
1600
(Note 7-1)
• Normal mode
IDDHALT(2)
IDDHALT(3)
HALT mode
• FmCF=0H (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Divider: 1/1
2.4 to 3.6
50
35
300
150
• Normal mode
HALT mode
• FmCF=0H (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Divider: 1/1
2.4 to 3.6
• Power save mode
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A0635-16/21
LC877816A/12A/08A
Continued from preceding page.
Specification
typ max
Pins/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Current
IDDHALT(4)
V
V
1=
2=
HALT mode
DD
consumption
during HALT
mode
• FmCF=0H (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: RC oscillation
• Divider: 1/2
DD
V2
2.4 to 3.6
30
135
(Note 7-1)
• Power save mode
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
HALT mode
• FmCF=0Hz (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
7.0
60
• Normal mode
HALT mode
• FmCF=0Hz (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
1.0
15
• Power save mode
HALT mode
• FmCF=0Hz (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/2
μA
2.4 to 3.6
2.4 to 3.6
0.8
14
30
• Power save mode
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
HOLD mode
• CF1=V
DD
or open
0.03
(when using external clock)
Date/time clock
Timer HOLD
mode
HOLD mode
consumption
current
• CF1=V or open
DD
(when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
5.0
45
(Note 7-1)
• Normal mode
IDDHOLD(3)
Date/time clock
HOLD mode
• CF1=V
DD
or open
(when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
0.5
15
• Power save mode
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A0635-17/21
LC877816A/12A/08A
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions:
Use the standard evaluation board SANYO has provided.
Use the peripheral parts with indicated value externally.
The peripheral parts value is a recommended value of oscillator manufacturer
Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Oscillation
Circuit parameters
Operating
stabilizing time
Frequency
Manufacturer
Type
Oscillator
supply voltage
range[V]
Notes
C1
C2
Rd
typ
max
[ms]
[pF]
(15)
[pF]
[Ω]
[ms]
SMD
Lead
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(15)
(15)
1k
2.4 to 3.6
2.4 to 3.6
0.2
0.2
0.6
0.6
Internal
C1, C2
4.00MHz
Murata
(15)
2.2k
The oscillation stabilizing time is a period until the oscillation becomes stable after V
minimum operating voltage. (See Fig. 4)
becomes higher than
DD
Subsystem Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions:
Use the standard evaluation board SANYO has provided.
Use the peripheral parts with indicated value externally.
The peripheral parts value is a recommended value of oscillator manufacturer
Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Operating
supply voltage
range
Oscillation
Circuit parameters
stabilizing time
Frequency
Manufacturer
Oscillator
Notes
C3
C4
Rf
Rd2
typ
[s]
max
[s]
[V]
[pF]
[pF]
[Ω]
[Ω]
Applicable CL
value = 12.5pF
32.768kHz
Epson Toyocom
MC-146
10
10
Open
0
2.4 to 3.6
1
3
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode. (See Fig. 4)
Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the
oscillation pins as possible with the shortest possible pattern length.
XT1
XT2
CF1
CF2
Rd
Rf
Rd2
C3
C1
C4
CF
C2
X’tal
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0635-18/21
LC877816A/12A/08A
V
V
DD
DD
Power Supply
RES
limit
0V
Reset time
Internal RC
Resonator
oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX’tal
Operation
mode
Reset
Instruction execution
Unfixed
Reset Time and Oscillation Stabilization Time
HOLD release
signal
Without HOLD
Release signal
HOLD release signal VALID
Internal RC
Resonator
oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX’tal
Operation mode
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilizing Time
No.A0635-19/21
LC877816A/12A/08A
V
DD
Note:
Select C
and R value to assure that at least
RES
RES
R
C
RES
200μs reset time is generated after the V
higher than the minimum operating voltage.
becomes
DD
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(only SIO0)
tSCK
tSCKL
tSCKH
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Data RAM
transfer period
(only SIO0)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
No.A0635-20/21
LC877816A/12A/08A
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of August, 2007. Specifications and information herein are subject
to change without notice.
No.A0635-21/21
PS
相关型号：
©2020 ICPDF网 联系我们和版权申明