LC87F0G08A [ONSEMI]
8-bit 1-chip Microcontroller;
| 型号： | LC87F0G08A |
| 厂家： | 
ONSEMI |
| 描述： | 8-bit 1-chip Microcontroller 微控制器 |
| 文件： | 总31页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2304
LC87F0G08A
CMOS LSI
8-bit 1-chip Microcontroller
http://onsemi.com
8K-byte Flash ROM / 256-byte RAM / 24-pin
Features
a 10 /20 amplifier
a 8/10-bit High-speed PWM(150kHz)
a Reference Voltage Generator Circuit(2V/4V) for an AD converter
a Temperature sensor
an internal reset circuit
a 7-channel AD converter with 12-/8-bit resolution selector
Internal oscillation circuits (30kHz/1MHz/8MHz)
Performance
SSOP24(225mil)
83.3ns (12.0MHz) V =2.7V to 5.5V Ta= 40C to + 85C
DD
DD
DD
125ns (8.0MHz)
250ns (4.0MHz)
V
V
=2.0V to 5.5V Ta= 40C to + 85C
=1.8V to 5.5V Ta= 40C to + 85C
Function Descriptions
Ports
-
I/O ports
: 18
-
-
Reference voltage outputs : 1 (VREF)
Power supply pins : 3 (V 1, V 2, V 1)
SS SS DD
Timers (3ch)
- Timer 0 : 16-bit timer/counter with a capture register.
- Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs
- a Base timer serving as a realtime clock
SIO (1ch)
- SIO1 : 8-bit asynchronous/synchronous serial interface
Comparator
Watchdog Timer
OWP0
1
24
23
22
21
20
19
18
17
16
15
14
13
P70/INT0/T0LCP/AN09
RES
P06/T1PWMH
2
Frequency tunable 12-bit PWM 2ch
P05/T1PWML /CKO
P04/AN4/VCPWM1
P03/AN3/VCPWM0
P02/AN2/CPIM
P01/APIP
3
VSS1
CF1/XT1
4
System Clock Divider Function
5
CF2/XT2
CF Oscillation Circuit, X'tal Oscillation Circuit
15 sources, 10 vectors interrupts
On-chip Debugger Function
6
VDD1
LC87F0G08A
7
P10/SO1
P00/APIM
8
P11/SI1/SB1
P12/SCK1
VREF
9
VSS2
10
11
12
P13/INT4/T1IN/AN7
P14/INT4/T1IN/AN6
P15/INT3/T0IN/AN5
P17/BUZ/INT1/T0HCP/HPWM2
P16/INT2/T0IN/CPOUT/HPWM2
Application
Shaver, Battery charge control
Pin Assignment (Top view)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of this data sheet.
Semiconductor Components Industries, LLC, 2014
March, 2014 Ver. 1.01
31014HKIM 20130905-S00003 No.A2304-1/31
LC87F0G08A
Function Details
Flash ROM
Capable of on-board programming with a wide range of supply voltages : 2.2 to 5.5V
Block-erasable in 128 byte units
Writes data in 2-byte units
8192 × 8 bits
RAM
256 × 9 bits
Bus Cycle Time
83.3ns ( 12MHz, V =2.7V to 5.5V, Ta=40C to 85C)
DD
125ns ( 8MHz, V =2.0V to 5.5V, Ta=40C to 85C)
DD
250ns ( 4MHz, V =1.8V to 5.5V, Ta=40C to 85C)
DD
Note : The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time (tCYC)
250ns (12MHz, V =2.7V to 5.5V, Ta=40C to 85C)
DD
375ns ( 8MHz, V =2.0V to 5.5V, Ta=40C to 85C)
DD
750ns ( 4MHz, V =1,8V to 5.5V, Ta=40C to 85C)
DD
Potrs
Normal withstand voltage I/O ports whose I/O direction can be designated in 1-bit units
18(P0n, P1n, P70, CF1, CF2)
Reset pins
1( )
RES
Power supply pins
Reference voltage outputs
Dedicated debugger port
3(V 1, V 2,V 1)
1(VREF)
1(OWP0)
SS SS DD
Timers
Timer 0 : 16-bit timer/counter with 2 capture registers.
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3 : 16-bit counter (with two 16-bit capture registers)
Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1 : 8-bit PWM with an 8-bit prescaler 2 channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from lower-order 8 bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs)
(lower-order 8 bits may be used as a PWM output)
Base timer
(1) The clock is selectable from the subclock (32.768kHz crystal oscillation), the low speed RC, system clock, and
timer 0 prescaler output.
(2) with an 8-bit programmable prescaler
(3) Interrupts programmable in 5 different time schemes
No.A2304-2/31
LC87F0G08A
SIO
SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
AD Converter:
AD converter input port with 10 /20 amplifier (1channel)
AD converter input port (7channel)
12-/8-bit resolution selectable AD converter
Selectable reference voltage source for an AD converter
( Selectable from V
, Internal Reference Voltage Generator Circuit(VREF) .)
DD
Internal Reference Voltage Generator Circuit(VREF)
Generates 2.0V/4.0V for AD converter.
Comparator
Comparator input pin (1 channel)
Comparator output pin (1 channel)
Comparator output set high when (comparator input level) < 1.22V
Comparator output set low when (comparator input level) > 1.22V
Clock Output Function
Generates clocks with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillation clock that is
selected as the system clock.
Watchdog Timer
Generates an internal reset on an overflow occurring in the timer running on the low-speed RC oscillator clock
(approx. 30kHz) or subclock.
Operating mode at standby is selectable from 3 modes
(continue counting/suspend operation/suspend counting with the count value retained)
No.A2304-3/31
LC87F0G08A
Interrupts
15 sources, 10 vectors
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address is given priority.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
2
0000BH
00013H
INT1
3
INT2/T0L/INT4
INT3/BT
T0H
4
0001BH
00023H
5
6
0002BH
00033H
T1L/T1H
HPWM2
SIO1
7
8
0003BH
00043H
9
ADC
10
0004BH
P0/VCPWM
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: Up to 128levels (the stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
16 bits 8 bits
24 bits 16 bits
16 bits 8 bits
24 bits 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
Internal oscillation circuits
1) Low-speed RC oscillation circuit:
For system clock (approx.30kHz)
2) Medium-speed RC oscillation circuit: For system clock (1MHz)
3) Hi-speed RC oscillation circuit1:
4) Hi-speed RC oscillation circuit2:
For system clock (8MHz)
For High speed PWM (40MHz)
System Clock Divider Function
Can run on low consumption current.
Minimum instruction cycle selectable from 375ns, 750ns, 1.5s, 3.0s, 6.0s, 12.0s, 24.0s, 48.0s, and
96.0s (at 8MHz main clock)
Internal Reset Circuit
Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level is 1.67V.
Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level can be selected from 7 levels
(1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V and 4.28V), through option configuration.
No.A2304-4/31
LC87F0G08A
Standby Function
● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) Having the watchdog timer or LVD function generate a reset
(3) Having an interrupt generated
● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC and crystal oscillators automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
2) There are four ways of resetting the HOLD mode:
(1) Setting the reset pin to the lower level
(2) Having the watchdog timer or LVD function generate a reset
(3) Having an interrupt source established at one of the INT0, INT1, INT2 and INT4 pins
* INT0 and INT1 can be used in the level sense mode only.
(4) Having an interrupt source established at port 0.
● X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
(when X’tal oscillation or low-speed RC oscillation is selected).
1) The CF, low-speed, and medium-speed RC oscillators automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
Note: If the base timer is run with low-speed RC oscillation selected as the base timer input clock source and the
X’tal HOLD mode is entered, the low-speed RC oscillator retains the state that is established when the
X’tal HOLD mode is entered.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Having the watchdog timer or LVD function generate a reset
(3) Having an interrupt source established at one of the INT0, INT1, INT2, and INT4 pins
* INT0 and INT1 can be used in the level sense mode only.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
VCPWM: Frequency tunable 12-bit PWM × 2ch
High speed PWM (HPWM2)
8-/10- bits PWM ×1ch
1) The PWM clock is selectable from system clock and Hi-speed RC2 (40MHz)
2) The PWM type is selectable from 8 bits(Normal mode) and 10 bits( additive puls mode).
Temperature sensor
Senseor voltage can be comapred by the AD converter.
On-chip Debugger Function
Supports software debugging with the IC mounted on the target board.
Provides 1 channel of on-chip debugger pin.
OWP0
Data Security Function
Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
Package Form
SSOP24 (225mil): Lead-free and halogen-free type
No.A2304-5/31
LC87F0G08A
Development Tools
On-chip debugger: TCB87 Type C (1-wire interface cable) + LC87F0G08A
Programming Boards
Package
Programming boards
W87F0GS
SSOP24(225mil)
Flash Programmer
Maker
Model
Supported version
Rev 03.28 or later
Device
Flash Support Group,
Single
Inc.
AF9709C
87F008SU
Programmer
(FSG)
Flash Support Group,
AF9101/AF9103(Main unit)
(FSG models)
Inc.
(FSG)
Onboard
Single/Gang
Programmer
(Note 2)
-
+
SIB87 Type C(Inter Face Driver)
(Our company model)
Our company
(Note 1)
Single/Gang
Programmer
Onboard
SKK Type B / SKK Type C
SKK-DBG Type C
Application Version
1.08 or later
Our company
LC87F0G08
Chip Data Version
2.46 or later
Single/Gang
Programmer
For information about AF-Series :
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: sales@j-fsg.co.jp
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company
(SIB87 Type C) together can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.
No.A2304-6/31
LC87F0G08A
Package Dimensions
unit : mm
SSOP24 (225mil)
CASE 565AR
ISSUE A
SOLDERING FOOTPRINT*
5.80
(Unit: mm)
GENERIC
1.0
MARKING DIAGRAM*
0.32
0.50
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
NOTE: The measurements are not to guarantee but for reference only.
*This information is generic. Please refer to
device data sheet for actual part marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
No.A2304-7/31
LC87F0G08A
Pin Assignment
P70/INT0/T0LCP/AN09
RES
OWP0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
P06/T1PWMH
P05/T1PWML /CKO
P04/AN4/VCPWM1
P03/AN3/VCPWM0
P02/AN2/CPIM
P01/APIP
V
1
SS
CF1/XT1
CF2/XT2
LC87F0G08A
V
1
DD
P10/SO1
P11/SI1/SB1
P00/APIM
VREF
P12/SCK1
9
P13/INT4/T1IN/AN7
P14/INT4/T1IN/AN6
P15/INT3/T0IN/AN5
V
2
10
11
12
SS
P17/BUZ/INT1/T0HCP/HPWM2
P16/INT2/T0IN/CPOUT/HPWM2
SSOP24(225mil) "Lead-/Halogen-free Type"
SSOP24
NAME
SSOP24
13
NAME
1
2
P70/INT0/T0LCP/AN09
RES
P16/INT2/T0IN/CPOUT/HPWM2
P17/BUZ/INT1/T0HCP/HPWM2
14
3
15
V
1
V
2
SS
SS
4
16
CF1/XT1
CF2/XT2
VREF
5
17
P00/APIM
6
18
V
1
P01/APIP
DD
7
19
P10/SO1
P11/SI1/SB1
P02/AN2/CPIM
P03/AN3/VCPWM0
P04/AN4/VCPWM1
P05/T1PWML/CKO
P06/T1PWMH
OWP0
8
20
9
21
P12/SCK1
10
11
12
22
P13/INT4/T1IN/AN7
P14/INT4/T1IN/AN6
P15/INT3/T0IN/AN5
23
24
No.A2304-8/31
LC87F0G08A
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF/XT
Flash ROM
low speed RC
medium speed RC
High speed RC
PC
RES
ACC
WDT
(low speed RC)
B register
Reset circuit
(LVD/POR)
C register
SIO1
Bus interface
Port0
ALU
Timer0
Timer1
Port1
PSW
RAR
Base timer
VCPWM
Port7
HPWM2
RAM
High speed RC2
Temperature sensor
Stack pointer
INT0-4
(INT3 with Noise filter)
On-chip debugger
+
-
ADC
10x/20x amplifier
(1 channel)
Vref
Comparator
No.A2304-9/31
LC87F0G08A
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
1
-
- power supply pin
+ power supply pin
- power supply pin
SS
No
No
1
-
DD
2
-
SS
No
VREF
I/O
I/O
I/O
Reference voltage output(2.0V/4.0V) or External input
On-chip debugger pin
No
OWP0
7-bit I/O port
Yes
Port 0
I/O specifiable in 1-bit units.
P00 to P06
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions
P00 (AN0), P01 (AN1): AD converter input port with 10x/20x operational amplifier
P02: AD converter input port (AN2) / Comparator input (CPIM)
P03: AD converter input port (AN3) / VCPWM0 output
P04: AD converter input port (AN4) / VCPWM1 output
P05: Timer 1 PWML output / System clock output
P06: Timer 1 PWMH output
P07: On-chip debugger pin (OWP0)
8-bit I/O port
Yes
Port 1
I/O
I/O specifiable in 1-bit units.
P10 to P15
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions
P10: SIO1 data output
P11: SIO1 data input/bus input/output
P12: SIO1 clock input/output
P13: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H
capture input/ AD converter input port (AN7)
P14: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H
capture input/ AD converter input port (AN6)
P15: INT3 input(with noise filter)/timer 0 event input/timer 0H capture input/
AD converter input port (AN5)
P16: INT2 input/HOLD release input/timer 0 event input/
timer 0L capture input/HPWM2 output
P17: beeper output/INT1 input/HOLD release input/timer 0H capture input/HPWM2 output
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
disable
enable
enable
enable
INT1
INT2
INT3
INT4
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
enable
disable
disable
disable
Continued on next page.
No.A2304-10/31
LC87F0G08A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
1-bit I/O port
I/O specifiable
P70
Pull-up resistors can be turned on and off.
Pin functions
P70 : INT0 input/HOLD release input/timer 0L capture input/AD converter input port (AN9)
Interrupt acknowledge type
Rising &
Rising
Falling
H level
enable
L level
enable
Falling
disable
INT0
enable
enable
External reset input/internal reset output pin
Yes
Internal pullup
ON/OFF
No
RES
I
Ceramic oscillator/32.768kHz crystal oscillator input pin
CF1/XT1
I/O
Pin functions
1-bit I/O port
I/O specifiable
(only Nch-open drain)
Ceramic oscillator/32.768kHz crystal oscillator output pin
No
No
CF2/XT2
OWP0
I/O
I/O
Pin functions
1-bit I/O port
I/O specifiable
On-chip debugger pin
No.A2304-11/31
LC87F0G08A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option selected in
Port Name
Option type
Output type
Pull-up resistor
Programmable
units of
1
2
1
2
CMOS
P00 to P06
1 bit
Nch-open drain
CMOS
Programmable
Programmable
Programmable
P10 to P17
CF1/XT1
1 bit
-
Nch-open drain
Nch-open drain
No
No
when general I/O port is selected.
CMOS / Nch-open drain
CF2/XT2
P70
-
-
No
No
No
when general I/O port is selected.(programmable)
Nch-open drain
Programmable
User Option Table
Option Name
Option Type
P00 to P06
Flash Version
Option Selected in Units of
1 bit
Option Selection
CMOS
enable
enable
Nch-open drain
CMOS
Port output form
P10 to P17
1 bit
Nch-open drain
00000h or 01E00h
When protected area 1) is selected
00000h
Program start
address
-
enable
enable
-
When either of protected area 2), 3) or
4) is selected
1) 1800h-1FFFh
2) 0000h-1DFFh,1F00h-1FFFh
3) 0000h-1CFFh,1F00h-1FFFh
Protected area
(Note1)
-
-
4) 0000h-1AFFh,1F00h-1FFFh
ON
Reset pin
Internal pullup ON/OFF
Detect function
enable
enable
-
-
OFF
Enable: Use
Low-voltage detection
reset function
Disable: Not Used
7-level
Detect level
enable
enable
-
-
Power-on reset
function
Power-On reset level
1-level
Note1: onboard programming inhbited address
No.A2304-12/31
LC87F0G08A
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Open
Open
Open
Open
Output low
Output low
Output low
P10 to P17
P70
CF1/XT1
CF2/XT2
OWP0
General I/O port output low
General I/O port output low
-
Pulled low with a 100k resistor
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “Rd87 On-chip
Debugger Installation Manual”
Power Pin Treatment Recommendations (V 1, V 1)
DD SS
Connect bypass capacitors that meet the following conditions between the V 1 and V 1 pins:
DD SS
Connect among the V 1 and V 1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead
DD SS
wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible
(L1=L1’, L2=L2’).
Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1F.
L2
L1
V
1
SS
C2
C1
V
1
DD
L1’
L2’
No.A2304-13/31
LC87F0G08A
Absolute Maximum Ratings at Ta = 25C, V 1 = V 2 = 0V
SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1
Conditions
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
MAX
V
DD
DD
to
to
+6.5
Input/output voltage
VIO
Port0,1
Port7
CF1,CF2,
Port0
Port1
CF2
-0.3
-10
V
DD
+0.3
RES
Peak output
current
IOPH(1)
IOMH(1)
ΣIOAH(1)
When CMOS output
type is selected
Per 1 applicable pin
When CMOS output
type is selected
Average
Port0
Port1
CF2
output current
(Note 1-1)
Total output
current
-7.5
-30
Per 1 applicable pin
Total current of all
applicable pins
Port0,1,
CF2
Peak output
current
IOPL(1)
IOPL(2)
IOPL(3)
IOML(1)
IOML(2)
IOML(3)
ΣIOAL(1)
Port0
Per 1 applicable pin
mA
20
20
10
15
15
7.5
Port1
Per 1 applicable pin
Per 1 applicable pin
Per 1 applicable pin
Per 1 applicable pin
Per 1 applicable pin
Port7,CF1,CF2
Port0
Average
output current
(Note 1-1)
Port1
Port7,CF1,CF2
Total output
current
Port0,1,7,
Total current of all
applicable pins
80
260
+85
CF1,CF2
Allowable power
Dissipation
Pdmax(1)
SSOP24(225mil)
Ta=-40 to + 85C
Package with thermal
resistance board
(Note 1-2)
mW
Operating ambient
Topr
Tstg
-40
-55
Temperature
Storage ambient
temperature
C
+125
Note 1-1: The average output current is an average of current values measured over 100ms intervals.
Note 1-2: SEMI standards thermal resistance board (size: 76.1114.31.6tmm, glass epoxy) is used.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
No.A2304-14/31
LC87F0G08A
Allowable Operating Conditions at Ta = -40C to +85C, V 1 = V 2 = 0V
SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
VDD1
Conditions
V
[V]
min
2.7
unit
DD
Operating
VDD(1)
0.245s tCYC 200s
0.367s tCYC 200s
0.735s tCYC 200s
5.5
5.5
5.5
supply voltage
(Note 2-1)
VDD(2)
VDD(3)
VHD
2.0
1.8
Memory
VDD1
RAM and register contents
sustained in HOLD mode.
sustaining
supply voltage
High level
1.6
V
V
VIH(1)
Port 0,1
P70
0.3V
DD
DD
1.8 to 5.5
input voltage
+0.7
0.75V
V
1.8 to 5.5
4.0 to 5.5
1.8 to 4.0
1.8 to 5.5
2.7 to 5.5
2.0 to 5.5
1.8 to 5.5
2.7 to 5.5
VIH(4)
VIL(1)
CF1,CF2,
Port 0,1
P70
DD
RES
RES
DD
0.1V +0.4
DD
Low level
V
SS
SS
SS
0.2V
DD
input voltage
V
V
0.25V
DD
VIL(4)
CF1,CF2,
CF1
Instruction
cycle time
tCYC
0.245
0.367
0.735
0.1
200
200
200
12
(Note 2-2)
s
(Note 2-2)
External
FEXCF
CF2 pin open
system clock
frequency
System clock frequency
division ratio=1/1
MHz
2.2 to 5.5
0.1
8
External system clock
duty=50 5%
Oscillation
frequency
range
FmCF(1)
FmCF(2)
FmCF(3)
FmFRC(1)
CF1,CF2
CF1,CF2
CF1,CF2
When 12MHz ceramic oscillation
See Fig. 1.
2.7 to 5.5
2.2 to 5.5
1.8 to 5.5
12
When 8MHz ceramic oscillation
See Fig. 1.
8
4
(Note 2-3)
When 4MHz ceramic oscillation
See Fig. 1.
Internal high-speed RC oscillation
Ta=-10C to +85C
(Note 2-4)
MHz
7.76
7.60
8.0
8.24
8.40
1.8 to 5.5
FmFRC(2)
Internal high-speed RC oscillation
Ta=-40C to +85C
(Note 2-4)
8.0
1.0
1.8 to 5.5
1.8 to 5.5
FmRC
Internal medium-speed RC
oscillation
0.5
27
2.0
33
FmSRC
Internal low-speed RC oscillation
(Note 2-5)
30
32.768
40
kHz
kHz
MHz
1.8 to 5.5
1.8 to 5.5
2.7 to 5.5
FsX’tal
XT1,XT2
CF1,CF2
32.768kHz crystal oscillation
See Fig. 2.
FmPWMRC
Internal high-speed RC oscillation
for HPWM2
38
42
See Table 1
Oscillation
Stabilization
Time
tmsCF
When oscillation circuit is
switched from “oscillation
stopped” to “oscillation
enabled” .
tmsFRC
(Note 2-4)
tmsPWMR
C
1.8 to 5.5
100
100
s
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
See Fig. 3.
tmsRC
0
tmsSRC
(Note2-5)
tmsX’tal
1
ms
XT1,XT2
See Table 2
Note 2-1: V
DD
must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Note 2-4: An oscillation stabilization time of 100s or longer must be provided before switching the system clock
source after the state of the high-speed RC oscillation circuit is switched from “oscillation stopped” to
“oscillation enabled” .
Note 2-5: An oscillation stabilization time of 1ms or longer must be provided before switching the system clock source
after the state of the low-speed RC oscillation circuit is switched from “oscillation stopped” to “oscillation
enabled” .
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A2304-15/31
LC87F0G08A
Electrical Characteristics at Ta = -40C to +85C, V 1 = V 2 = 0V
SS
SS
Specification
typ
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
max
unit
DD
High level input
current
I
(1)
Port 0,1,
Port 7,
RES
Output disabled
Pull-up resistor off
=V
IH
V
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1
IN DD
(Including output Tr's off
leakage current)
I
I
(2)
IH
CF1
V
=V
15
IN DD
A
Low level input
current
(1)
Port 0,1,
Port 7,
RES
Output disabled
IL
Pull-up resistor off
V
=V
-1
IN SS
(Including output Tr's off
leakage current)
I
(2)
CF1
V
I
=V
1.8 to 5.5
4.5 to 5.5
1.8 to 5.5
4.5 to 5.5
1.8 to 5.5
4.5 to 5.5
-15
-1
IL
IN SS
High level output
voltage
V
V
V
V
(1)
Port 0,1,
CF2
=-1mA
V
OH
OH
DD
V
(2)
I
I
I
=-0.2mA
V
-0.4
OH
OH
DD
Low level output
voltage
(1)
(2)
Port 0,1,
=10mA
=1.0mA
=0.9V
1.5
0.4
80
OL
OL
P70,CF1,CF2
OL
OL
Pull-up resistance
Rpu(1)
Rpu(2)
Port 0,1,
P70
V
OH
15
18
35
50
DD
1.8 to 4.5
230
500
k
Rpu(3)
RES
1.8 to 5.5
2.7 to 5.5
300
400
Hysteresis voltage
Pin capacitance
VHYS(1)
Port 0,1,
P70
0.1V
DD
V
1.8 to 5.5
0.07V
DD
RES
CP
All pins
For pins other than that under
test:
V
=V
1.8 to 5.5
10
pF
IN SS
f=1MHz
Ta=25C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2304-16/31
LC87F0G08A
SIO1 Serial I/O Characteristics (Note 4-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(1)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK1(P12)
See Fig. 5.
2
Low level
tSCKL(1)
tSCKH(1)
tSCK(2)
tSCKL(2)
tSCKH(2)
tsDI(1)
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1
1
2
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P12)
CMOS output type selected
See Fig. 5.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
SI1(P11),
SB1(P11)
Specified with respect to rising
edge of SIOCLK.
0.05
0.05
See Fig. 5.
Data hold time
thDI(1)
s
Output delay time
tdDO(1)
SO1(P10),
SB1(P11)
Specified with respect to falling
edge of SIOCLK
Specified as the time up to the
beginning of output change in
open drain output mode.
See Fig. 5.
(1/3)tCYC
+0.08
Note 4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Pulse Input Conditions at Ta = -40C to +85C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
tCYC
s
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
Interrupt source flag can be set.
Event inputs for timer 0 or 1 are
enabled.
INT1(P71),
1.8 to 5.5
1
INT2(P16),
INT4(P13, P14)
INT3(P15) when noise
filter time constant is
1/1
tPIH(2)
tPIL(2)
Interrupt source flag can be set.
Event inputs for timer 0 are
enabled.
1.8 to 5.5
1.8 to 5.5
2
tPIH(3)
tPIL(3)
INT3(P15) when noise
filter time constant is
1/32
Interrupt source flag can be set.
Event inputs for timer 0 are
enabled.
64
tPIH(4)
tPIL(4)
INT3(P15) when noise
filter time constant is
1/128
Interrupt source flag can be set.
Event inputs for timer 0 are
enabled.
1.8 to 5.5
1.8 to 5.5
256
200
RES
tPIL(5)
Resetting is enabled.
No.A2304-17/31
LC87F0G08A
AD Converter Characteristics at V 1 = V 2 = 0V
SS SS
<12bits AD Converter Mode/Ta = -40C to +85C >
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN2(P02)
AN3(P03)
AN4(P04)
AN5(P15)
AN6(P14)
AN7(P13)
AN9(P70)
1.8 to 5.5
1.8 to 5.5
12
Absolute
ET
(Note 6-1)
LSB
16
accuracy
Conversion time
TCAD
See conversion time
calculation method.
(Note 6-2)
2.7 to 5.5
2.2 to 5.5
1.8 to 5.5
1.8 to 5.5
32
115
215
430
134
400
s
Analog input
voltage range
VAIN(1)
VAIN(2)
When V is selected
DD
V
V
DD
SS
(Note 6-3)
When internal VREF=4V is
selected.
4.3 to 5.5
2.3 to 3.6
V
VREF
SS
V
VREFV
DD
When internal VREF=2V is
selected
V
VREF
1
SS
-1
VREFV
DD
Analog port
input current
IAINH
IAINL
VAIN=V
1.8 to 5.5
1.8 to 5.5
DD
SS
A
VAIN=V
<8bits AD Converter Mode/Ta = -40C to +85C >
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN2(P02)
AN3(P03)
AN4(P04)
AN5(P15)
AN6(P14)
AN7(P13)
AN9(P70)
1.8 to 5.5
1.8 to 5.5
8
Absolute
ET
(Note 6-1)
LSB
1.5
accuracy
Conversion time
TCAD
See conversion time calculation
2.7 to 5.5
2.2 to 5.5
1.8 to 5.5
1.8 to 5.5
20
80
90
135
265
method.
s
(Note 6-2)
245
Analog input
voltage range
VAIN(1)
VAIN(2)
When V is selected
DD
V
V
SS
DD
(Note 6-3)
When internal VREF=4V is
selected.
4.3 to 5.5
2.3 to 3.6
V
VREF
SS
V
VREFV
DD
When internal VREF=2V is
selected.
V
VREF
1
SS
-1
VREFV
DD
Analog port
input current
IAINH
IAINL
VAIN=V
1.8 to 5.5
1.8 to 5.5
DD
SS
A
VAIN=V
<Conversion time calculation method>
12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)(1/3)tCYC
8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2) (1/3)tCYC
No.A2304-18/31
LC87F0G08A
<Recommended Operating Conditions>
AD conversion time
(TCAD)
External
oscillation
(FmCF)
Operating supply
voltage range
AD division
ratio
System division ratio
Cycle time
(tCYC)
(SYSDIV)
(V
)
(ADDIV)
12bit AD
8bit AD
32.25s
128.25s
64.5s
DD
2.7V to 5.5V
2.2V to 5.5V
2.7V to 5.5V
2.2V to 5.5V
1.8V to 5.5V
1/1
1/1
1/1
1/1
1/1
375ns
375ns
750ns
750ns
750ns
1/8
1/32
1/8
52.25s
208.25s
104.5s
208.5s
416.5s
CF-8MHz
CF-4MHz
1/16
1/32
128.5s
256.5s
Note 6-1: The quantization error (1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is
measured when no change occurs in the I/O state of the pins that are adjacent to the analog input channel
during AD conversion processing.
Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
The first AD conversion executed in the 12-bit AD conversion mode after a system reset
The first AD conversion executed after the AD conversion mode is switched from 8-bit to 12-bit AD
conversion mode
Note 6-3: See section 8, “10×/20× amplifier characteristics”, for analog channel 0 (10×/20× amplifier output).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Reference Voltage Generator Circuit (VREF) Characteristics
at Ta = -40C to +85C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
V
DD
VREF=2V voltage
accuracy
VREF2VO
VREF4VO
VREF
1.8 to 2.0
2.0 to 5.5
2.3 to 5.5
1.8 to 4.0
4.0 to 5.5
4.3 to 5.5
1.8 to 5.5
V
V
-0.1
V
DD
DD
1.90
(Note 7-2)
2.02
2.02
1.98
-0.1
VREF=4V voltage
accuracy
V
DD
DD
3.90
3.96
4.04
4.04
0.5
VREFoutput current
VREFIO
tVREFW
V
mA
ms
SS
Operation
1.8 to 5.5
stabilization time
(Note 7-1)
5
Note 7-1: Refers to the interval between the time VR12ON and VR24ON are set to 1 and the time operation gets
stabilized.
Note 7-2: An external 4.7F capacitor must be connected to the VREF pin to stabilize the VREF voltage.
No.A2304-19/31
LC87F0G08A
10x/20x Amplifier Characteristics at Ta = -40C to +85C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
mV
DD
20x Amplifier gain
APGAIN20
See Fig7
VAPIO20
P00/APIM
P01/APIP
Ta=-40 to +85C
20
1)APDIR=0 & GAIN20=1.
P01=0V,P000V or
P00=0V,P010V
20x Amplifier
offset
2)APDIR=1 & GAIN20=1.
P01=0V,P000V or
P00=0V,P010V
200
600
20x Amplifier
input voltage
range
VAPIM20-1
VAPIP20-1
VAPIM20-2
VAPIP20-2
P00/APIM
P01/APIP
P00/APIM
P01/APIP
P01/APIP=0V
1)
-0.17
0
0
0.17
0.17
0
V
V
P00/APIM=0V
P01/APIP=0V
2)
0
P00/APIM=0V
-0.17
10x Amplifier gain
APGAIN10
See Fig7
VAPIO10
P00/APIM
P01/APIP
Ta=-40 to +85C
10
3)APDIR=0 & GAIN20=0.
P01=0V,P000V or
P00=0V,P010V
10x Amplifier
offset
4.3 to 5.0
4)APDIR=1 & GAIN20=0.
P01=0V,P000V or
P00=0V,P010V
100
300
mV
10x Amplifier
input voltage
range
VAPIM10-3
VAPIP10-3
VAPIM10-4
VAPIP10-4
IAPINL
P00/APIM
P01/APIP
P00/APIM
P01/APIP
P00/APIM
P01/APIP
P01/APIP=0V
3)
-0.24
0
0
0.24
0.24
0
V
V
P00/APIM=0V
P01/APIP=0V
4)
0
P00/APIM=0V
-0.24
-1
Amplifier input
P00/APIM=V -0.2V
SS
A
port input current
IAPINH
P01/APIP=V
DD
1
Operation
tAPW
stabilization time
(Note 8-1)
20
s
Note 8-1: Refers to the interval between the time APON is set to 1 and the time operation gets stabilized.
<Amplifier input vaoltage calculation method:See Fig7>
VAPFUL = ( VREFAD - VAPIO ) / APGAIN
( VREFAD can be selected from internal-VREF4V, internal-VREF2V and V . )
DD
Note: VAPFUL must not exceed VAPIP or VAPIM.
No.A2304-20/31
LC87F0G08A
Comparator Characteristics at Ta = -40C to +85C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
VCMVT
Pin/Remarks
P02/CPIM
Conditions
V
[V]
min
unit
V
DD
Comparator
2.5 to 5.5
threshold voltage
(Note 9-1)
1.12
1.22
1.32
Input voltage range
VCMIN
VOFF
2.5 to 5.5
2.5 to 5.5
V
V
V
SS
DD
Offset voltage
Within input voltage
range
±10
200
±30
mV
Response time
tRT
Within input voltage
range
2.5 to 5.5
Input amplitude
=100mV
600
ns
Overdrive=50mV
Operation
tCMW
2.5 to 5.5
1.0
s
stabilization time
(Note 9-2)
Note 9-1: Comparator output=High level when (P02/CPIM voltage) < VCMVT
Comparator output=Low level when (P02/CPIM voltage) > (VCMVT +VOFF)
Note 9-2: Refers to the interval between the time CPON is set to 1 and the time operation gets stabilized.
Temperature Sensor Characteristics at Ta = -40C to +85C, V 1 = V 2 = 0V
SS SS
<4-diode mode>
Specification
typ max
3.25 3.27
Parameter
Symbol
Pin/Remarks
Conditions
Ta=-40C
V
[V]
min
3.23
unit
V
DD
Output voltage
sensitivity
VOTMP4(1)
VOTMP4(2)
VOTMP4(3)
Vsen4
5.0
5.0
5.0
Ta=+25C
2.75
2.28
2.77
2.31
2.80
2.34
Ta=+85C
Ta=-40 to +85C
3.5 to 5.5
3.5 to 5.5
3.5 to 5.5
mV/C
C
-7.63
-7.54
-7.45
Absolute accuracy
(Note 10-1)
ETTMP4
Vref=4[V]
Ta=(60±10) C
(Note 10-3)
±2.5
±5
±5
(Note 10-2)
Ta=-40 to +85C
±10
<2-diode mode>
Specification
typ max
1.63
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
V
DD
Output voltage
sensitivity
VOTMP2(1)
VOTMP2(2)
VOTMP2(3)
Vsen2
Ta=-40C
3.3
3.3
3.3
1.61
1.37
1.14
-3.81
1.64
1.40
1.17
-3.72
Ta=+25C
1.39
1.16
Ta=+85C
Ta=-40 to +85C
2.0 to 5.5
2.0 to 5.5
2.0 to 5.5
mV/C
C
-3.77
Absolute accuracy
(Note 10-1)
ETTMP2
Vref=2[V]
Ta=(60±10) C
(Note 10-4)
±2.5
±5
(Note 10-2)
Ta=-40 to +85C
±5
±10
Note 10-1: There are cases when the absolute accuracy specification value is exceeded when a large current flows
through the ports.
Note 10-2: Including error of AD Converter.
Note 10-3: When using the Temperature sensor 60C 2-diodes reference register D2TL/ D2TH.
Note 10-4: When using the Temperature sensor 60C 4-diodes reference register D4TL/ D4TH.
No.A2304-21/31
LC87F0G08A
Power-on Reset (POR) Characteristics at Ta = -40C to +85C, V 1 = V 2 = 0V
SS SS
Specification
typ max
Parameter
Symbol
Pin / Remarks
Conditions
Option Selected
Voltage
min
unit
V
POR release
voltage
PORRL
Option selected
(Note 11-1)
1.67V
1.10
1.79
0.95
100
Detection voltage
unpredictable
area
POUKS
PORIS
See Fig. 8.
(Note 11-2)
0.7
Power supply rise
time
Power startup time from
VDD=0V to 1.6V
ms
Note 11-1: The POR release voltage can be selected when the low-voltage detection feature is deselected.
Note 11-2: There is an unpredictable area before the transistor starts to turn on.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40C to +85C, V 1= V 2= 0V
SS SS
Specification
typ max
1.91
Parameter
Symbol
Pin / Remarks
Conditions
Option Selected
Voltage
unit
min
1.81
LVD reset voltage
(Note 12-2)
LVDET
Option selected
See Fig. 9.
1.91V
2.01
2.11
2.41
2.61
2.93
3.92
4.41
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
1.91
2.21
2.41
2.71
3.69
4.18
2.01
2.31
2.51
2.81
3.79
4.28
55
(Note 12-1)
(Note 12-3)
V
LVD voltage
hysteresis
LVHYS
55
55
55
mV
60
65
65
Detection voltage
unpredictable
area
LVUKS
TLVDW
See Fig. 9.
(Note 12-4)
0.7
0.95
V
Minimum low
voltage detection
width (response
sensitivity)
LVDET-0.5V
See Fig. 10.
0.2
ms
Note 12-1: The LVD reset voltage can be selected from 7 levels when the low-voltage detection feature is selected.
Note 12-2: The hysteresis voltage is not included in the LVD reset voltage specification value.
Note 12-3: There are cases when the LVD reset voltage specification value is exceeded when a greater change in the
output level or large current is applied to the port.
Note 12-4: There is an unpredictable area before the transistor starts to turn on.
No.A2304-22/31
LC87F0G08A
Consumption Current Characteristics at Ta = -40C to +85C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Pin /
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
FmCF=8MHz ceramic oscillation mode
System clock set to 8MHz mode
DD
2.2 to 5.5
2.2 to 3.6
1.8 to 5.5
1.8 to 3.6
1.8 to 5.5
1.8 to 3.6
1.8 to 5.5
3.8
5.2
2.9
Internal low-/medium-speed RC oscillation
(Note 13-1)
(Note 13-2)
stopped
2.2
2.1
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/1
IDDOP(2)
IDDOP(3)
IDDOP(4)
FmCF=4MHz ceramic oscillation mode
System clock set to 4MHz mode
Internal low-/medium-speed RC oscillation
stopped
3.5
1.1
1.7
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/1
mA
FsX’tal=32.768kHz crystal oscillation mode
Internal low-speed RC oscillation stopped
System clock set to internal medium-speed RC
oscillation mode
0.23
0.13
2.7
0.39
0.19
3.6
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/2
FsX’tal=32.768kHz crystal oscillation mode
Internal low-/medium-speed RC oscillation
stopped
System clock set to internal high-speed RC
oscillation mode
1.8 to 3.6
1.8 to 5.5
1.7
10
2.3
42
Frequency division ratio set to 1/1
External oscillation FsX’tal/FmCF stopped
System clock set to internal low-speed RC
oscillation mode
IDDOP(5)
IDDOP(6)
Internal medium-speed RC oscillation stopped
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/1
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz mode
Internal low-/medium-speed RC oscillation
stopped
1.8 to 3.6
1.8 to 5.5
6
21
A
46
101
1.8 to 3.6
16
40
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/2
Continued on next page.
No.A2304-23/31
LC87F0G08A
Continued from preceding page.
Specification
Typ max
Pin /
Parameter
Symbol
Conditions
Remarks
V
V]
min
unit
DD[
HALT mode
consumption
current
IDDHALT(1)
V
1
HALT mode
DD
FmCF=8MHz ceramic oscillation mode
System clock set to 8MHz mode
Internal low-/medium-speed RC oscillation
stopped
2.2 to 5.5
2.2 to 3.6
1.8 to 5.5
1.8 to 3.6
1.8 to 5.5
1.8 to 3.6
2.0
1.0
3.2
1.6
(Note 13-1)
(Note 13-2)
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/1
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
HALT mode
FmCF=4MHz ceramic oscillation mode
System clock set to 4MHz mode
Internal low-/medium-speed RC oscillation
stopped
1.2
2.4
0.5
1.0
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/1
mA
HALT mode
FsX’tal=32.768kHz crystal oscillation mode
Internal low-speed RC oscillation stopped
System clock set to internal medium-speed
RC oscillation mode
0.12
0.06
0.25
0.11
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/2
HALT mode
FsX’tal=32.768kHz crystal oscillation mode
Internal low-/medium-speed RC oscillation
stopped
1.8 to 5.5
1.8 to 3.6
1.1
0.7
1.7
1.0
System clock set to internal high-speed RC
oscillation mode
Frequency division ratio set to 1/1
HALT mode
External oscillation FsX’tal/FmCF stopped
System clock set to internal low-speed RC
oscillation mode
1.8 to 5.5
1.8 to 3.6
3.8
2.4
37
17
Internal medium-speed RC oscillation
stopped
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/1
A
IDDHALT(6)
HALT mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz mode
Internal low-/medium-speed RC oscillation
stopped
1.8 to 5.5
1.8 to 3.6
42
13
97
38
Internal high-speed RC oscillation stopped
Frequency division ratio set to 1/2
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
V
V
1
1
HOLD mode
0.023
0.012
1.09
0.86
39
33.2
1.8 to 5.5
1.8 to 3.6
1.8 to 5.5
1.8 to 3.6
1.8 to 5.5
1.8 to 3.6
DD
14.2
26.9
11.8
94
HOLD mode
(Note 13-1)
(Note 13-2)
LVD option selected
A
Timer HOLD
mode
Timer HOLD mode
DD
FsX’tal=32.768kHz crystal oscillation mode
12
36
consumption
current
Timer HOLD mode
0.63
0.53
34
15
1.8 to 5.5
1.8 to 3.6
FmSRC=30kHz internal low-speed RC
oscillation mode
(Note 13-1)
(Note 13-2)
Note 13-1: The consumption current value includes none of the currents that flow into the output transistors and internal
pull-up resistors.
Note 13-2: Unless otherwise specified, the consumption current for the LVD circuit is not included.
No.A2304-24/31
LC87F0G08A
F-ROM Programming Characteristics at Ta = +10C to +55C, V 1 = V 2 = 0V
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
mA
DD
Onboard
IDDFW(1)
V
1
DD
Excluding power
programming
current
dissipation in the
microcontroller block
Erasing time
2.2 to 5.5
2.2 to 5.5
5
10
Programming
time
tFW(1)
tFW(2)
20
40
30
60
ms
Programming time
s
No.A2304-25/31
LC87F0G08A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
MURATA Manufacturing Co., Ltd.
Oscillation
Circuit Constant
Operating
Voltage Range
[V]
Stabilization Time
Nominal
Type
Oscillator Name
Remarks
Frequency
C1
C2
Rf
Rd
typ
max
[ms]
[pF]
[pF]
[]
[]
[ms]
12MHz
8MHz
4MHz
SMD
SMD
SMD
CSTCE12M0G52-R0
CSTCE8M00G52-R0
CSTCR4M00G53-R0
(10)
(10)
(15)
(10)
(10)
(15)
Open
Open
Open
680
1k
2.6 to 5.5
2.1 to 5.5
1.8 to 5.5
0.02
0.02
0.03
0.3
0.3
C1 and C2
integrated
type
1.5k
0.45
Characteristics of a Sample Subsystem Clock Oscillation Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit that Uses a Crystal Oscillator
EPSON TOYOCOM
Oscillation
Circuit Constant
Operating
Voltage Range
[V]
Stabilization Time
Nominal
Type
Oscillator Name
Remarks
Frequency
C1
C2
Rf
Rd
typ
max
[ms]
[pF]
[pF]
[]
[]
[ms]
Applicable
CL value =
7.0pF
32.768kHz
SMD
MC-306
9
9
Open
330k
1.8 to 5.5
1.4
4.0
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 3):
Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed
Till the oscillation gets stabilized after the HOLD mode is released.
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF2/XT2
CF1/XT1
Rf
Rd
C1
C2
CF/X’tal
Figure 1 CF/XT Oscillator Circuit
0.5V
DD
Figure 2 AC Timing Measurement Point
No.A2304-26/31
LC87F0G08A
V
DD
Operating V
lower limit
0V
DD
Power supply
Reset time
RES
Internal medium speed
RC oscillation
tmsCF/tmsX’tal
CF1, CF2
Operating
Unpredictable
Reset
Instruction execution
mode
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD release
signal absent
HOLD release signal valid
Internal medium speed
RC oscillation or
internal low speed RC
oscillation
tmsCF/tmsX’tal
CF1, CF2
(Note)
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Note: When an external oscillation circuit is selected.
Figure 3 Oscillation Stabilization Time
No.A2304-27/31
LC87F0G08A
V
DD
Note:
The external circuit for reset may vary depending on
the usage of POR and LVD. See “Reset Function” in
the user's manual.
R
RES
RES
C
RES
Figure 4 Sample Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DATAOUT:
tSCK
tSCKH
thDI
tSCKL
SIOCL
DATAIN:
tsDI
tdDO
DATAOUT:
Figure 5 Serial I/O Waveform
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A2304-28/31
LC87F0G08A
AMPoutput
VREF
AMPoutput
VREF
APGAIN
APGAIN
VAPIO
0
VAPIO
0
0V
0V
+VAPFUL
1) P01/APIPinput
2) P00/APIMinput
-VAPFUL
(b)
1) P00/APIM input
2) P01/APIPinput
(a)
Figure 7 10/20 Amplifier Characteristics
(a) 1) When P01/APIP is 0V, P00/APIM 0V.
2) When P00/APIM is 0V, P01/APIP 0V.
(b) 1) When P00/APIM is 0V, P01/APIP 0V.
2) When P01/APIP is 0V, P00/APIM 0V.
No.A2304-29/31
LC87F0G08A
POR release voltage
(PORRL)
(a)
(b)
V
DD
Reset period
Reset period
100s or longer
Reset unknown
area (POUKS)
RES
Figure 8 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with R
RES
Pull-up Resistor Only)
The POR function generates a reset only when the power voltage goes up from the V level.
No stable reset will be generated if power is turned on again when the power level does not go down to the V level
SS
SS
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit as shown below.
A reset is generated only when the power level goes down to the V level as shown in (b) and power is turned on
SS
again after this condition continues for 100s or longer.
LVD hysteresis width
LVD release voltage
(LVHYS)
(LVDET+LVHYS)
V
DD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Reset unknown
area (LVUKS)
RES
Figure 9 Example of POR + LVD Mode Waveforms (at Reset Pin with R
RES
Pull-up Resistor Only)
Resets are generated both when power is turned on and when the power level lowers.
A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
.
level
No.A2304-30/31
LC87F0G08A
V
DD
LVD release voltage
LVD detect voltage
LVDET-0.5V
TLVDW
V
SS
Figure 10 Minimum Low Voltage Detection Width (Example of Voltage Sag/Fluctuation Waveform)
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
2000 / Tape & Reel
SSOP24(225mil)
(Pb-Free / Halogen Free)
LC87F0G08AUJA-AH
SSOP24(225mil)
(Pb-Free / Halogen Free)
LC87F0G08AUJA-FH
LC87F0G08AUJA-ZH
2000 / Tape & Reel
1400 / Fan-Fold
SSOP24(225mil)
(Pb-Free / Halogen Free)
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warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any
such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
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PS No.A2304-31/31
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