LC87F5864B(QIP64E) [ONSEMI]
IC,MICROCONTROLLER,8-BIT,CMOS,QFP,64PIN,PLASTIC;
| 型号： | LC87F5864B(QIP64E) |
| 厂家： | 
ONSEMI |
| 描述： | IC,MICROCONTROLLER,8-BIT,CMOS,QFP,64PIN,PLASTIC 微控制器 |
| 文件： | 总23页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN8296A
CMOS IC
FROM 64K byte, RAM 2048 byte on-chip
LC87F5864B
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F5864B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
100ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard programmable),
2048-byte RAM, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit
timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit
11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 23-source 10-vector interrupt
feature.
Features
Flash ROM
• Runs on a 3V single power source and supports onboard programming.
• Block-erasable in 128 byte units
• 65536 × 8-bits (LC87F5864B)
RAM
• 2048 × 9 bits (LC87F5864B)
Minimum Bus Cycle
• 100ns (10MHz)
• 125ns (8MHz)
• 500ns (2MHz)
V
V
V
=3.0 to 3.6V
=2.5 to 3.6V
=2.2 to 3.6V
DD
DD
DD
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 300ns (10MHz)
• 375ns (8MHz)
• 1.5µs (2MHz)
V
V
V
=3.0 to 3.6V
=2.5 to 3.6V
=2.2 to 3.6V
DD
DD
DD
*This product incorporates technology licensed from Silicon Storage Technology Inc
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.05
83006 / 42706HKIM No.8296-1/23
LC87F5864B
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (V 1 to 3, V 1 to 3)
SS DD
• Power pins
Timers
• Timer 0 : 16-bit timer/counter with a capture register
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 : 16-bit counter (with a 16-bit capture register)
• Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter
(with toggle outputs)
Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as PWM)
• Timer 4 : 8-bit timer with a 6-bit prescaler
• Timer 5 : 8-bit timer with a 6-bit prescaler
• Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz)
2) Can generate output real-time
SIO
• SIO0 : 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
No.8296-2/23
LC87F5864B
AD Converter : 8-bits × 11-channels
PWM : Multifrequency 12-bit PWM × 2-channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 23 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4
4
0001BH
00023H
INT3/INT5/base timer0/ base timer1
T0H
5
6
0002BH
00033H
T1L/T1H
7
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
8
0003BH
00043H
9
10
0004BH
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels : 1024 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits
• 24-bits × 16-bits
• 16-bits ÷ 8-bits
• 24-bits ÷ 16-bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal) : For system clock
• CF oscillation circuit :
• Crystal oscillation circuit :
For system clock, with internal Rf
For low-speed system clock, with internal Rf
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and
76.8µs (at a main clock rate of 10MHz).
No.8296-3/23
LC87F5864B
Standby Function
• HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base
timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the Xtal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size : 128 bytes
Onchip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QIP64E (14 × 14): Lead-free type
• TQFP64 (10 × 10): Lead-free type
• TQFP64J (10 × 10): Lead-free type
• TQFP64J (7 × 7):
Lead-free type
• VQFN64 (10 × 10): Lead-free type
Development Tools
• Evaluation chip :
• Emulator :
LC87EV690
EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP
(* Tools for VQFN64 (10 × 10) and TQFP64J(7 × 7) version of PODs to be determined)
Programming Boards
• W87F50256Q (For QIP64E (14 × 14) package)
• W87F57256SQ (For TQFP64 (10 × 10) and TQFP64J (10 × 10) packages)
• W87F58256TQ7 (For TQFP64J (7 × 7) packages)
• W87F58256VQ (For VQFN64 (10 × 10) package)
No.8296-4/23
LC87F5864B
Package Dimensions
Package Dimensions
unit : mm
unit : mm
3159A
3296
12.0
10.0
17.2
14.0
48
33
48
33
32
49
49
32
17
64
64
17
1
16
0.2
1
16
0.5
0.15
0.8
0.35
0.15
(1.0)
(1.25)
SANYO : TQFP64(10X10)
SANYO : QIP64E(14X14)
Package Dimensions
Package Dimensions
unit : mm
unit : mm
3310
3289
12.0
10.0
9.0
7.0
48
33
48
33
49
32
17
49
32
17
64
64
1
16
0.18
1
16
0.16
0.125
0.125
0.5
0.4
(1.25)
(0.5)
SANYO : TQFP64J(10X10)
SANYO : TQFP64J(7X7)
No.8296-5/23
LC87F5864B
Package Dimensions
unit : mm
3323
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Depth:0.03 MIN
0.5
10.2
10.0
0.3
2
.
48
33
0
49
32
11
8.0 Typ
64
1
16
(1.25)
Do Not Connect
0.2
0.5
SIDE VIEW
SANYO : VQFN64(10X10)
Pin Assignments
48 47 46 45 44 43 42
40 39 38 37 36 35 34 33
41
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
RES
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB2
49
PB3
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PB4
PB5
PB6
XT1/AN10
PB7
XT2/AN11
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/URX/INT4/T1IN
P20/UTX/INT4/T1IN
P07/T7O
V
1
SS
LC87F5864B
CF1
CF2
1
V
DD
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
P06/T6O
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Top view
SANYO: QIP64E (14 × 14) “Lead-free Type”
SANYO: TQFP64 (10 × 10) “Lead-free Type”
SANYO: TQFP64J (10 × 10)“Lead-free Type”
SANYO: TQFP64J (7 × 7) “Lead-free Type”
No.8296-6/23
LC87F5864B
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P05/CKO
P04
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PB1
PB0
P03
V
V
3
SS
P02
3
DD
P01
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
P00
V
V
2
2
SS
DD
LC87F5864B
PWM3
PWM2
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P86/AN6
P85/AN5
P84/AN4
P83/AN3
P14/SI1/SB1
P13/SO1
P12/SCK0
15
16
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Top view
SANYO: VQFN64 (10 × 10) “Lead-free Type”
No.8296-7/23
LC87F5864B
System Block Diagram
Interrupt control
Standby control
IR
PLA
ROM correct
CF
RC
Flash ROM
X’tal
PC
SIO0
Bus interface
Port 0
SIO1
ACC
B register
Timer 0
Timer 1
Timer 4
Timer 5
Timer 6
Port 1
Port 2
Port 7
Port 8
ADC
C register
ALU
PSW
RAR
INT0 to INT5
Noise filter
Timer 7
Base timer
PWM2/3
RAM
Port B
Stack pointer
Watchdog timer
Port C
UART
On-chip debugger
No.8296-8/23
LC87F5864B
Pin Description
Pin Name
I/O
-
Description
Option
V
V
1, V
3
2
SS
- Power supply pin
+ Power supply pin
• 8-bit I/O port
No
SS
SS
V
V
1, V
3
2
DD
-
No
DD
DD
Port 0
I/O
Yes
• I/O specifiable in 4-bit units
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
P00 to P07
• Port 0 interrupt input
• Shared Pins
P05 : System clock output (system clock / can selected from sub clock)
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
P10 to P17
P10 : SIO0 data output
P11 : SIO0 data input/bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input/bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/beeper output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units
• Shared pins
P20 to P27
P20 : UART transmit
P21 : UART receive
P20 to P23 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input
/timer 0H capture input
P24 to P27 : INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input
/timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
enable
INT4
INT5
enable
enable
enable
enable
disable
disable
disable
disable
enable
Port 7
I/O
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
AD converter input port : AN8 (P70), AN9 (P71)
P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71 : INT1 input/HOLD reset input/timer 0H capture input
P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input /
high speed clock counter input
P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Continued on next page.
No.8296-9/23
LC87F5864B
Continued from preceding page.
Pin Name
Port 8
I/O
I/O
Description
Option
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared pins
AD converter input port : AN0 (P80) to AN6 (P86)
• PWM2 and PWM3 output ports
• General-purpose I/O available
• 8-bit I/O port
PWM2, PWM3
I/O
I/O
No
Port B
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
Port C
I/O
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
On-chip debugger pins : DBGP0 to DBGP2 (PC5 to PC7)
RES
XT1
Input
Input
Reset pin
No
No
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to V 1 if not to be used.
DD
XT2
I/O
• 32.768kHz crystal oscillator output pin
• Shared pins
No
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.8296-10/23
LC87F5864B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected
Port Name
P00 to P07
Option Type
Output Type
Pull-up Resistor
in Units of
1-bit
1
2
CMOS
Programmable (Note 1)
No
Nch-open drain
CMOS
P10 to P17
P20 to P27
1-bit
1-bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
No
No
No
No
1
P71 to P73
P80 to P86
PWM2, PWM3
PB0 to PB7
-
-
-
Nch-open drain
CMOS
No
1-bit
CMOS
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
PC0 to PC7
1-bit
1
2
Nch-open drain
Input only
XT1
XT2
-
-
No
No
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose output mode)
Note 1 : Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1 : Connect the IC as shown below to minimize the noise input to the V 1 pin.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS SS SS
LSI
V
1
DD
Power
Supply
For backup *2
V
V
2
3
DD
DD
V
1
V
2
V
3
SS
SS
SS
*2 : The internal memory is sustained by V 1. If none of V 2 and V 3 are backed up, the high level output at
DD DD DD
the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.8296-11/23
LC87F5864B
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
max
DD
V
1, V 2, V
3
V
1=V 2=V
DD
3
DD
DD
DD
DD
DD
+4.6
Input voltage
V (1)
I
XT1, CF1
-0.3
V
V
+0.3
DD
DD
Input/output voltage
VIO(1)
Ports 0, 1, 2
Ports 7, 8
-0.3
+0.3
Ports B, C
PWM2, PWM3, XT2
Ports 0, 1, 2, 7
Ports B, C
Peak output
current
IOPH(1)
CMOS output select
Per 1 applicable pin
-4
(Note 1-1)
Total output
current
PWM2, PWM3
Port 7
Σ
IOAH(1)
IOAH(2)
Total of all applicable pins
Total of all applicable pins
-10
-25
Σ
Port 1
PWM2, PWM3
Ports 0, 2
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Per 1 applicable pin
-25
-25
-25
Port B
Port C
Peak output
current
IOPL(1)
P02 to P07
Ports 1, 2, 7, 8
Ports B, C
6
mA
(Note 1-1)
PWM2, PWM3, XT2
P00, P01
IOPL(2)
Per 1 applicable pin
15
10
10
25
Total output
current
ΣIOAL(1)
Port 7
Total of all applicable pins
P83 to P86, XT2
P80 to P82
Σ
IOAL(2)
IOAL(3)
Total of all applicable pins
Total of all applicable pins
Σ
Port 1
PWM2, PWM3
Ports 0, 2
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
25
25
25
Port B
Port C
Power dissipation
Pd max
QIP64E (14
TQFP64 (10
×
14)
10)
Ta= -20 to +70°C
414
236
284
192
209
×
TQFP64J (10
×
10)
7)
10)
mW
TQFP64J (7
VQFN64 (10
×
×
Operating ambient
temperature
Topr
Tstg
-20
-55
+70
°
C
Storage ambient
temperature
+125
Note 1-1 : The average current per applicable pin must not exceed 1mA.
No.8296-12/23
LC87F5864B
Allowable Operating Conditions at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
typ
max
unit
DD
Operating
V
(1)
V
0.294
0.367
µ
s
s
≤
≤
tCYC
tCYC
≤
≤
200
200
µ
s
s
3.0
2.5
3.6
DD
DD
DD
supply voltage
(Note 2-1)
µ
µ
Except for FROM onboard
programming
3.6
1.47µs ≤ tCYC ≤ 200µs
Except for FROM onboard
programming
2.2
2.0
3.6
3.6
Memory
VHD
V
1=V 2=V
DD
3
DD
RAM and register contents
sustained in HOLD mode.
DD
sustaining
supply voltage
High level input
voltage
V
(1)
Ports 1, 2
IH
P71 to P73
0.3V
DD
2.2 to 3.6
2.2 to 3.6
V
V
DD
DD
P70 port input
/interrupt side
Ports 0, 8, B, C
PWM2, PWM3
+0.7
V
V
(2)
(3)
(4)
0.3V
V
IH
IH
IH
DD
+0.7
Port 70 watchdog
timer side
2.2 to 3.6
2.2 to 3.6
0.9V
V
V
DD
DD
DD
DD
RES
V
V
XT1, XT2, CF1,
0.75V
Low level input
voltage
(1)
Ports 1, 2
IL
P71 to P73
2.2 to 3.6
V
0.2V
SS
DD
P70 port input
/interrupt side
Ports 0, 8, B, C
PWM2, PWM3
V
V
V
(2)
(3)
(4)
IL
IL
IL
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
V
V
V
0.2V
0.8V
SS
SS
SS
DD
DD
Port 70 watchdog
timer side
-1.0
RES
XT1, XT2, CF1,
0.25V
DD
Instruction cycle
time
tCYC
3.0 to 3.6
2.5 to 3.6
2.2 to 3.6
3.0 to 3.6
2.5 to 3.6
0.294
0.367
1.47
0.1
200
200
200
10
Except for FROM onboard
programming
µs
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division ratio=1/1
0.1
8
• External system clock
duty=50 5%
2.2 to 3.6
0.1
2
• CF2 pin open
3.0 to 3.6
2.5 to 3.6
2.2 to 3.6
0.2
0.2
0.2
20
16
4
• System clock frequency
division ratio=1/2
MHz
Oscillation
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
10MHz ceramic oscillation
See Fig. 1.
3.0 to 3.6
2.5 to 3.6
10
frequency range
(Note 2-3)
8MHz ceramic oscillation
See Fig. 1.
8
4MHz ceramic oscillation
See Fig. 1.
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
4
1.0
FmRC
FsX’tal
Internal RC oscillation
0.3
2.0
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
32.768
kHz
Note 2-1 : V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2 : Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3 : See Tables 1 and 2 for the oscillation constants.
No.8296-13/23
LC87F5864B
Electrical Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 2
Ports 7, 8
Ports B, C
RES
Output disabled
Pull-up resistor off
=V
V
2.2 to 3.6
1
IN DD
(Including output Tr's off leakage
PWM2, PWM3
XT1, XT2
current)
I
(2)
IH
For input port specification
2.2 to 3.6
2.2 to 3.6
1
8
V
V
=V
IN DD
I
I
(3)
IH
CF1
=V
IN DD
µA
Low level input
current
(1)
IL
Ports 0, 1, 2
Ports 7, 8
Ports B, C
RES
Output disabled
Pull-up resistor off
V
=V
IN SS
2.2 to 3.6
-1
(Including output Tr's off leakage
PWM2, PWM3
XT1, XT2
current)
I
I
(2)
IL
For input port specification
2.2 to 3.6
-1
-8
V
V
I
=V
IN SS
(3)
IL
CF1
=V
2.2 to 3.6
3.0 to 3.6
IN SS
High level output
voltage
V
(1)
Ports 0, 1, 2, 7
Ports B, C
= -0.4mA
OH
OH
OH
V
V
-0.4
-0.4
DD
DD
V
(2)
I
= -0.2mA
OH
2.2 to 3.6
PWM2, PWM3
PWM2, PWM3
V
V
V
(3)
(4)
I
I
I
= -1.6mA
= -0.8mA
3.0 to 3.6
2.2 to 3.6
V
V
-0.4
-0.4
OH
OH
OH
OH
DD
DD
V
Low level output
voltage
(1)
Ports 0, 1, 2, 7, 8
Ports B, C
PWM2, PWM3
XT2
=1.6mA
OL
OL
3.0 to 3.6
2.2 to 3.6
0.4
0.4
V
(2)
I
=0.8mA
OL
OL
V
V
(3)
(4)
P00, P01
I
I
=5mA
3.0 to 3.6
2.2 to 3.6
0.4
0.4
OL
OL
OL
OL
=2.5mA
=0.9V
Pull-up resistor
Rpu
Ports 0, 1, 2, 7
Ports B, C
RES
V
OH
DD
2.2 to 3.6
2.2 to 3.6
25
50
200
10
k
Ω
Hysteresis
voltage
VHYS
CP
0.1
V
Ports 1, 2, 7
All pins
Pin capacitance
For pins other than that under test :
V
=V
IN SS
f=1MHz
Ta=25
2.2 to 3.6
pF
°
C
No.8296-14/23
LC87F5864B
Serial Input/Output Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
V
[V]
min
typ
max
unit
DD
See Fig. 6.
2
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
1
1
pulse width
High level
pulse width
2.2 to 3.6
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.2 to 3.6
• Continuous data
tSCKH(2)
+(10/3)
tCYC
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
0.03
0.03
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
µs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.15
2.2 to 3.6
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans / rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.8296-15/23
LC87F5864B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
V
[V]
min
typ
max
unit
DD
See Fig. 6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 3.6
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.2 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.2 to 3.6
2.2 to 3.6
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
µs
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.2 to 3.6
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.8296-16/23
LC87F5864B
Pulse Input Conditions at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
unit
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1
are enabled.
INT1(P71),
INT2(P72),
2.2 to 3.6
1
INT4(P20 to P23),
INT5(P24 to P27)
INT3(P73) when noise
filter time constant is 1/1
tPIH(2)
tPIL(2)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.2 to 3.6
2.2 to 3.6
2
tCYC
tPIH(3)
tPIL(3)
INT3(P73) when noise
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
filter time constant is 1/32
64
tPIH(4)
tPIL(4)
INT3(P73) when noise
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
filter time constant is 1/128
2.2 to 3.6
2.2 to 3.6
256
200
RES
tPIL(5)
Resetting is enabled.
µs
AD Converter Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
bit
DD
Resolution
N
AN0(P80)
to AN6(P86)
AN8(P70)
AN9(P71)
AN10(XT1)
AN11(XT2)
3.0 to 3.6
3.0 to 3.6
8
Absolute accuracy
Conversion time
ET
(Note 6-1)
AD conversion time=32 × tCYC
(when ADCR2=0) (Note 6-2)
±1.5
LSB
TCAD
31.36
(tCYC=
0.980 s)
97.92
3.0 to 3.6
(tCYC=
µ
3.06µs)
µs
AD conversion time=64 × tCYC
31.36
97.92
(when ADCR2=1)
(Note 6-2)
3.0 to 3.6
3.0 to 3.6
(tCYC=
(tCYC=
0.490
µs)
1.53
µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
1
IAINH
IAINL
VAIN=V
DD
3.0 to 3.6
3.0 to 3.6
µA
VAIN=V
SS
-1
Note 6-1 : The quantization error ( 1/2LSB) is excluded from the absolute accuracy value.
Note 6-2 : The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.8296-17/23
LC87F5864B
Consumption Current Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=10MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 10MHz side
• Internal RC oscillation stopped
• 1/1 frequency division ratio
DD
=V
2
3
DD
DD
=V
3.0 to 3.6
3.0 to 3.6
5.2
12
14
(Note 7-1)
IDDOP(2)
• CF1=20MHz external clock
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to CF1 side
5.6
• Internal RC oscillation stopped
• 1/2 frequency division ratio
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• 1/1 frequency division ratio
3.0 to 3.6
2.5 to 3.0
3.0 to 3.6
2.2 to 3.0
4.2
3.2
9.8
7.1
3.3
2.5
mA
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ratio
1.4
0.94
IDDOP(7)
IDDOP(8)
IDDOP(9)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• 1/2 frequency division ratio
3.0 to 3.6
2.2 to 3.0
0.39
0.27
1.7
1.3
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• 1/2 frequency division ratio
3.0 to 3.6
2.2 to 3.0
24
15
81
58
µA
IDDOP(10)
HALT mode
consumption
current
IDDHALT(1)
HALT mode
• FmCF=10MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 10MHz side
• Internal RC oscillation stopped
• 1/1 frequency division ratio
3.0 to 3.6
2.1
2.6
5.1
6.8
(Note 7-1)
IDDHALT(2)
• CF1=20MHz external clock
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to CF1 side
3.0 to 3.6
• Internal RC oscillation stopped
• 1/2 frequency division ratio
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• 1/1 frequency division ratio
3.0 to 3.6
2.5 to 3.0
3.0 to 3.6
2.2 to 3.0
1.8
1.3
4.3
3.2
2.0
1.5
mA
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ratio
0.81
0.53
IDDHALT(7)
IDDHALT(8)
• HALT mode
3.0 to 3.6
2.2 to 3.0
0.23
0.16
1.0
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• 1/2 frequency division ratio
0.77
Note 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.8296-18/23
LC87F5864B
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
HALT mode
IDDHALT(9)
IDDHALT(10)
IDDHOLD(1)
V
1
• HALT mode
DD
consumption
current
=V
=V
2
3
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• 1/2 frequency division ratio
3.0 to 3.6
2.2 to 3.0
7.0
24
17
DD
DD
(Note 7-1)
4.6
µA
HOLD mode
consumption
current
V
1
HOLD mode
DD
3.0 to 3.6
2.2 to 3.0
0.04
0.03
8
6
• CF1=V
or open
DD
IDDHOLD(2)
IDDHOLD(3)
(external clock mode)
Timer HOLD mode
Timer HOLD mode
consumption
current
3.0 to 3.6
2.2 to 3.0
4.7
3.0
16
11
• CF1=V
or open
DD
(external clock mode)
IDDHOLD(4)
• FmX’tal=32.768kHz crystal oscillation mode
Note 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
mA
DD
Onboard
IDDFW(1)
V
1
• 128-byte programming
• Erasing current included
DD
programming
current
3.0 to 3.6
3.0 to 3.6
15
40
Programming
time
tFW(1)
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte data is
excluded.
20
40
ms
UART (Full Duplex) Operating Conditions at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
16/3
typ
max
unit
DD
2.2 to 3.6
Transfer rate
UBR
UTX(P20),
URX(P21)
8192/3
tCYC
Data length:
Stop bits:
Parity bits:
7, 8, and 9 bits (LSB first)
1-bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Stop bit
End of
transmission
Start bit
Start of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
End of
reception
Start bit
Start of
reception
Receive data (LSB first)
UBR
No.8296-19/23
LC87F5864B
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation Stabilization
Circuit Constant
Nominal
Time
Vendor Name
Oscillator Name
Remarks
Frequency
C1
C2
Rd1
typ
max
[ms]
[pF]
[pF]
[
Ω]
[ms]
MURATA
KYOCERA
MURATA
KYOCERA
MURATA
KYOCERA
CSTCE10M0G52-R0
PBRC10.00HR
(10)
(10)
(10)
(30)
(15)
(30)
(10)
(10)
(10)
(30)
(15)
(30)
470
0
3.0 to 3.6
3.0 to 3.6
2.5 to 3.6
2.5 to 3.6
2.2 to 3.6
2.2 to 3.6
0.1
0.09
0.1
0.5
0.45
0.5
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
10MHz
8MHz
4MHz
CSTCE8M00G52-R0
PBRC8.00HR
1k
0
0.07
0.1
0.35
0.5
CSTCR4M00G53-R0
PBRC4.00HR
2.2k
0
0.07
0.35
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Figure 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Circuit Constant
Operating Voltage
Nominal
Stabilization Time
Vendor Name
Oscillator Name
Range
[V]
Remarks
Frequency
C3
C4
Rf
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[
Ω]
[Ω]
Applicable
CL value
=12.5pF
32.768kHz
SEIKO EPSON
MC-306
10
10
10M
510k
2.2 to 3.6
1.0
3.0
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf
Rd1
C2
Rd2
C4
C1
C3
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.8296-20/23
LC87F5864B
V
DD
Power supply
Operating V
0V
lower limit
DD
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating
Reset
Instruction execution
Unpredictable
mode
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.8296-21/23
LC87F5864B
V
DD
R
C
Note :
RES
Determine the value of C
and R so that the
RES
RES
reset signal is present for a period of 200µs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK :
DATAIN :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKL
tSCKH
thDI
SIOCLK :
DATAIN :
tsDI
tdDO
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK :
DATAIN :
tsDI
thDI
tdDO
DATAOUT :
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.8296-22/23
LC87F5864B
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No.8296-23/23
PS
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