LC88FC3K0AUTJ-2H [ONSEMI]
16 位微控制器，配备 768K 字节闪存和 47.5K 字节 RAM，100 引脚;
| 型号： | LC88FC3K0AUTJ-2H |
| 厂家： | 
ONSEMI |
| 描述： | 16 位微控制器，配备 768K 字节闪存和 47.5K 字节 RAM，100 引脚 控制器 微控制器 闪存 |
| 文件： | 总48页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC88FC3K0A
16-bit Microcontroller
768K-byte Flash ROM / 47.5K-byte RAM / 100-pin
LC88FC3K0A is a 16-bit Microcontroller with 768K-byte Flash ROM/47.5K-
byte RAM in 100-pin package. Main features are infrared remote controller
receiver circuit (supports PPM and Manchester encoding), 16 channels of 12-
bit resolution ADC, internal reset circuit, CRC circuit and etc. that are software
friendly circuits and these peripheral circuit can contribute to less external
components. Also, plenty of serial interface circuits (synchronous serial × 3,
I2C × 3, UART × 3) can communicate with other LSIs and are suitable for
home appliances and white goods which need complicated control. For
software development, there is our original software development environment
and with On-Chip Debugging function, it is easy to debug with user’s actual
application.
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Features
16-channel 12-bit resolution AD converter
Infrared remote controller receiver circuit
CRC operating circuit
TQFP 100,14X14
Internal Reset Function
Performance
100ns (10.0MHz) V =2.7 to 3.6V Ta=40C to +85C
DD
Function Descriptions
Xstromy16 CPU
- 4G-byte address space
7574 73 72 71 70 69 6867 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PB6/SM1DO
P70/AN8
P71/AN9
- General-purpose registers: 16 bits 16 registers
Ports
- I/O Ports 86
- Power supply pins 8 (VSS1 to VSS4, VDD1 to VDD4)
Timer
- 16-bit timers 8
- Base timer serving as a time-of-day clock
Serial interfaces
- Synchronous SIO interfaces 3
(with automatic transmission capability)
- Single master I2C/synchronous SIO interface 2
- Slave I2C/synchronous SIO interface
- Asynchronous SIO (UART) interfaces 3
Multifrequency 12-bit PWM modules
16-channel 12-bit resolution AD converter
Watchdog timer
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P41/INT7
P42
P43/SO1
P44/SI1/SB1
P45/SCK1
P46/PWM0A
P47/PWM0B
P27
P72/AN10
P73/AN11
P74/AN12
P75/AN13
P76/AN14
P77/AN15
P26/T5O
P25/T4O
P24/SM0DO
P23/SM0DA
P22/SM0CK
VDD2
V
SS4
V 4
DD
PA0/SO4
PA1/SI4/SB4
PA2/SCK4
PA3/SCS4
PA4/SL0CK
PA5/SL0DA
PA6/SL0DO
PA7
LC88FC3K0A
VSS2
P21/INT5
P20/INT4
PD5
PD4
PD3
PD2
PD1
PD0
P17/U2TX
P16/U2RX
PC2/FILT
P50/P5INT0
P51/P5INT1
P52/P5INT2
P53/P5INT3
P54/P5INT4
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Top view
Infrared remote controller receiver circuit
CRC operating circuit
Real time clock
Pin Assignment (Top view)
System clock frequency divider
CF oscillator circuit, Crystal oscillator circuit, RC oscillator circuit
61-source 14-vector interrupt feature
On-chip debugger function
Application
Home audio, White goods
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 48 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
September 2015 - Rev. 0
1
Publication Order Number :
LC88FC3K0A/D
LC88FC3K0A
Function Details
Xstromy16 CPU
4G-byte address space
General-purpose registers : 16 bits 16 registers
Flash ROM
786432 8 bits
Programming voltage level : 2.7 to 3.6V.
Block-erasable in 2K byte units.
Data written in 2-byte units.
RAM
48640 8 bits
Minimum instruction cycle time (tCYC)
100 ns (10 MHz),
V
= 2.7 to 3.6V
DD
Ports
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units : 86 (P0n P1n, P2n, P3n, P4n, P5n, P6n, P7n, PAn
PB0 to PB6, PC2, PD0 to PD5)
: 4 (PC0, PC1, PC3, PC4)
: 1 (RESB)
Oscillation/normal withstand voltage I/O ports
Reset pins
TEST pins
Power pins
: 1 (TEST)
: 8 (V 1 to 4, V 1 to 4)
SS DD
Timers
Timer 0 : 16-bit timer that supports PWM/toggle outputs
<1> 5-bit prescaler
<2> 8-bit PWM 2, 8-bit timer + 8-bit PWM mode selectable
<3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator.
Timer 1 : 16-bit timer with capture registers
<1> 5-bit prescaler
<2> May be divided into 2 channels of 8-bit timer
<3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
Timer 2 : 16-bit timer with capture registers
<1> 4-bit prescaler
<2> May be divided into 2 channels of 8-bit timer
<3> Clock source selectable from system clock, OSC0, OSC1, and external events
Timer 3 : 16-bit timer that shpports PWM/toggle outputs
<1> 8-bit prescaler
<2> 8-bit timer 2ch or 8-bit timer+8-bit PWM mode selectable
<3> Clock source selectable from system clock, OSC0, OSC1, and external events
Timer 4 : 16-bit timer that supports toggle outputs
<1> Clock source selectable from system clock and prescaler 0
Timer 5 : 16-bit timer that supports toggle output
<1> Clock source selectable from system clock and prescaler 0
Timer 6 : 16-bit timer that supports toggle outputs
<1> Clock source selectable from system clock and prescaler 1
Timer 7 : 16-bit timer that supports toggle output
<1> Clock source selectable from system clock and prescaler 1
*Prescaler 0 and 1 are consisted of 4bits and can choose their clock source from OSC0 or OSC1.
Base timer
<1> Clock may be selected from OSC0 (32.768 kHz crystal oscillator) and frequency-divided output of
system clock.
<2> Interrupts can be generated in 7 timing schemes.
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LC88FC3K0A
Real time clock
<1> Calender with Jan. 1, 2000 to Dec.31, 2799 including automatic leapyear calculation function.
<2> Consisted of Indipendent second-minuit-hour-day-month-yeare-century counters.
Serial interfaces
SIO0 : 8-bit synchronous SIO
<1> LSB first/MSB first mode selectable
<2> Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
<3> Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
<4> Continuous/automatic data transmission (9- to 32768-bit units specifiable)
<5> Interval function (intervals specifiable in 0 to 64tSCK units)
<6> Wakeup function
SIO1 : 8-bit synchronous SIO
<1> LSB first/MSB first mode selectable
<2> Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
<3> Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
<4> Continuous/automatic data transmission (9- to 32768-bit units specifiable)
<5> Interval function (intervals specifiable in 0 to 64tSCK units)
<6> Wakeup function
SIO4 : 8-bit synchronous SIO
<1> LSB first/MSB first mode selectable
<2> Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
<3> Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
<4> Continuous/automatic data transmission (9- to 32768-bit units specifiable)
<5> Interval function (intervals specifiable in 0 to 64tSCK units)
<6> Wakeup function
2
SMIIC0 : Single master I C/8-bit synchronous SIO
Mode 0 : Single-master mode communication
Mode 1 : Synchronous 8-bit serial I/O (MSB first)
2
SMIIC1 : Single master I C/8-bit synchronous SIO
Mode 0 : Single-master mode communication
Mode 1 : Synchronous 8-bit serial I/O (MSB first)
2
SLIIC0 : Slave I C/8-bit synchronous SIO
Mode 0 : I2C slave mode communication
Mode 1 : Synchronous 8-bit serial I/O (MSB first)
Note: usable only with the external clock source
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3
LC88FC3K0A
UART0
<1> Data length : 8 bits (LSB first)
<2> Start bits
<3> Stop bits
: 1 bit
: 1 bit
<4> Parity bits : None/even parity/odd parity
<5> Transfer rate : 4/8 cycle
<6> Baudrate source clock: P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock
source) or Timer4 cycle.
<7> Full duplex communication
Note : The “cycle” refers to one period of the baudrate clock source.
UART2
<1> Data length : 8 bits (LSB first)
<2> Start bits
<3> Stop bits
: 1 bit
: 1/2 bit
<4> Parity bits : None/even parity/odd parity
<5> Transfer rate : 8 to 4096 cycle
<6> Baudrate source clock: System clock/OSC0/OSC1/P26 input signal
<7> Wakeup function
<8> Full duplex communication
Note : The “cycle” refers to one period of the baudrate clock source.
UART3
<1> Data length : 8 bits (LSB first)
<2> Start bits
<3> Stop bits
<4> Parity bits
: 1 bit
: 1/2 bit
: None/even parity/odd parity
<5> Transfer rate : 8 to 4096 cycle
<6> Baudrate source clock: System clock/OSC0/OSC1/P36 input signal
<7> Wakeup function
<8> Full duplex communication
Note : The “cycle” refers to one period of the baudrate clock source.
AD converter
<1> 12/8 bits resolution selectable
<2> Analog input: 16 channels
<3> Comparator mode
PWM
PWM0 : Multifrequency 12-bit PWM 2 channels (PWM0A and PWM0B)
<1> 2-channel pairs controlled independently of one another
<2> Clock source selectable from system clock or OSC1
<3> 8-bit prescaler: TPWMR0= (prescaler value + 1) clock period
<4> 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit
<5> Fundamental wave PWM mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
<6> Fundamental wave + additional pulse mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
Overall period
: Fundamental wave period 16
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
CRC operating circuit
Watchdog timer
<1> Driven by the base timer + internal watchdog timer dedicated counter
<2> Interrupt or reset mode selectable
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4
LC88FC3K0A
Infrared Remote Controller Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120s when the 32.768kHz crystal oscillator
is selected as the reference clock source)
2) Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording
3) X’tal HOLD mode release function
Internal Reset Function
Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected through option configuration.
Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power
voltage falls below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level can be selected by option
configuration.
Interrupts (peripheral function)
61 sources (33 modules), 14 vector addresses
<1> Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
<2> When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the
highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt
into the smallest vector address takes precedence.
No. Vector Address
Interrupt Module
1
2
08000H
08004H
08008H
0800CH
08014H
08018H
0801CH
08020H
08024H
0802CH
08030H
08034H
08038H
0803CH
Watchdog timer (1)
Base timer (2)
Timer 0 (2)
3
4
INT0 (1)
5
INT1 (1)
6
INT2 (1) / timer 1 (2) / UART2 (4)
INT3 (1) / timer 2 (4) / SMIIC0 (1) / SLIIC1 (1)
INT4 (1) / timer 3 (2) / Infared remote control receiver(4)
INT5 (1) / timer 4 (1) / SIO1 (2)
7
8
9
10
11
12
13
14
PWM0 (1) / SMIIC1(1)
ADC (1) / timer 5 (1) / SIO4(2)
INT6 (1) / timer 6 (1) / UART 3 (4)
INT7 (1) / SIO0 (2) / SIO0(2)
Port 0 (3) / Port 5 (8) / RTC (1) / CRC (1)
3 priority levels selectable
Of interrupts of the same level, the one with the smallest vector address takes precedence.
A number enclosed in parentheses denotes the number of sources.
Subroutine stack : RAM area
Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes
Subroutine calls that do not automatically save PSW: 4 bytes
Multiplication/division instructions
16 bits × 16 bits (4 tCYC execution time)
16 bits ÷ 16 bits (18 to 19 tCYC execution time)
32 bits ÷ 16 bits (18 to 19 tCYC execution time)
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5
LC88FC3K0A
Oscillator circuits
RC oscillator circuit (internal)
CF oscillator circuit ( built-in Rf circuit )
Crystal oscillator circuit ( built-in Rf circuit ) : For low-speed system clock (OSC0)
SLRC oscillator circuit (internal)
VCO oscillator circuit
: For system clock
: For system clock( OSC1 )
: For system clock (In the case of exception processing)
: For timer3, 4, 5, 6, 7 clock
System clock divider function
Can run on low current.
1/1 to 1/128 of the system clock frequency can be set.
Standby function
HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.
<1> Oscillation is not stopped automatically.
<2> Released by a system reset or occurrence of an interrupt.
HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.
<1> OSC1, RC, and OSC0 oscillations automatically stop.
<2> There are six ways of releasing the HOLD mode:
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified
level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt established at SIO0, SIO1 or SIO4
(6) Having an interrupt established at UART2 or UART3
HOLDX mode : Suspends instruction execution and the operation of the peripheral circuits except those
which run on OSC0.
<1> OSC1 and RC oscillations automatically stop.
<2> OSC0 maintains the state that is established when the HOLDX mode is entered.
<3> There are nine ways of releasing the HOLDX mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6,and INT7 pins to the specified
level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt source established at the base timer circuit
(6) Having an interrupt established at SIO0, SIO1 or SIO4
(7) Having an interrupt established at UART2 or UATR3
(8) Having an interrupt established at Infared remote control receiver.
(9) Having an interrupt source established at the real time clock circuit
On-chip debugger function
Supports software debugging with the IC mounted on the target board.
Supports source line debugging and tracing functions, and breakpoint setting and real time display.
Single-wire communication
Package form
TQFP100, 14 14 : Pb-Free and Halogen Free type
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LC88FC3K0A
Development tools
On-chip debugger : EOCUIF1 or EOCUIF2 + LC88FC3K0A
Programming board
Package
Programming Board
W88F52TQ
TQFP 100, 14 14
Flash ROM Programmer
Maker
Model
Supported Version
Application Version
After 1.08A
Chip Data Version
After 2.51
Device
Single /
Gang
SKK Type C
(SanyoFWS)
LC88FC3x0
programmer
ON
Semiconductor
Application Version
After 1.08A
Chip Data Version
After 2.51
On-board
Single
programmer
FWS-X16DI Type 3
LC88FC3x0
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7
LC88FC3K0A
Package Dimensions
unit : mm
TQFP 100, 14x14
CASE 932AN-01
ISSUE O
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8
LC88FC3K0A
Pin Assignment
75 74 73 72 71 70 69 6867 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PB6/SM1DO
P70/AN8
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P41/INT7
P42
P71/AN9
P43/SO1
P44/SI1/SB1
P45/SCK1
P46/PWM0A
P47/PWM0B
P27
P72/AN10
P73/AN11
P74/AN12
P75/AN13
P76/AN14
P77/AN15
P26/T5O
P25/T4O
P24/SM0DO
P23/SM0DA
P22/SM0CK
VDD2
V
SS4
V
4
DD
PA0/SO4
PA1/SI4/SB4
PA2SCK4
PA3/SCS4
PA4/SL0CK
PA5/SL0DA
PA6/SL0DO
PA7
LC88FC3K0A
VSS2
P21/INT5
P20/INT4
PD5
PD4
PC2/FILT
PD3
P50/P5INT0
P51/P5INT1
P52/P5INT2
P53/P5INT3
P54/P5INT4
PD2
PD1
PD0
P17/U2TX
P16/U2RX
100
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Top view
TQFP100,14×14 (Pb-Free and Halogen Free type)
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LC88FC3K0A
System Block Diagram
Base timer
Watchdog timer
Timer 0
Xstromy16
CPU
FLASH ROM
RAM
Timer 1
On-chip debugger
PLL
Timer 2
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Timer 3
VCO
CF
Timer 4
Timer 5
Timer 6
RC
X’tal
Low
speed
RC
Timer 7
SIO0
LVD/POR
SIO1
SIO4
Port A
Port B
SMIIC0
SMIIC1
SLIIC0
Port C
Port D
UART0
UART2
UART3
PWM0
INT0 to INT7
AD
DA
RTC
Remote control
receiver circuit
CRC
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LC88FC3K0A
Pin Description
Pin Name
I/O
Description
VSS1, VSS2,
VSS3, VSS4
VDD1, VDD2,
VDD3, VDD4
Port 0
–
– power sources
+ power sources
–
I/O
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
HOLD release input (P00 to P03, P04, P05)
Port 0 interrupt input (P00 to P03, P04, P05)
Pin functions
P00 to P07
P06 : Timer 0L output
P07 : Timer 0L output/UART0 clock input
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
Pin functions
Port 1
I/O
P10 to P17
P10 : SIO0 data output
P11 : SIO0 data input/pulse input/output
P12 : SIO0 clock input/output
P13 : UART0 transmit
P14 : Timer 3L output/UART0 receive
P15 : Timer 3H output
P16 : UART2 receive
P17 : UART2 transmit
Port 2
I/O
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
Pin functions
P20 to P27
P20 : INT4 input/HOLD release input/timer 3 event input/
timer 2L capture input/timer 2H capture input
P21 : INT5 input/HOLD release input/timer 3 event input/
timer 2L capture input/timer 2H capture input
P22 : SMIIC0 clock input/output
P23 : SMIIC0 bus input/output/data input
P24 : SMIIC0 data output (used in 3-wire SIO mode)
P25 : Timer 4 output
P26 : Timer 5 output
Interrupt acknowledge type
INT4, INT5 : H level, L level, H edge, L edge, both edges
Continued on next page.
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LC88FC3K0A
Continued from preceding page.
Pin Name
Port 3
I/O
Description
I/O
8-bit I/O port
I/O specifiable in 1-bit units
P30 to P37
Pull-up resistors can be turned on and off in 1 bit units
Pin functions
P30 : INT0 input/HOLD release/timer 2L capture input
P31 : INT1 input/HOLD release/timer 2H capture input
P32 : INT2 input/HOLD release/timer 2 event input/timer 2L capture input/
Infrared Remote Controller Receiver input
P33 : INT3 input/HOLD release/timer 2 event input/timer 2H capture input
P34 : UART3 receive
P35 : UART3 transmit
P36 : Timer 6 output
P37 : Timer 7 output
Interrupt acknowledge type
INT0 to INT3 : H level, L level, H edge, L edge, both edges
Port 4
I/O
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
Pin functions
P40 to P47
P40 : INT6 input/HOLD release input
P41 : INT7 input/HOLD release input
P43 : SIO1 data output
P44 : SIO1 data input/bus input/output
P45 : SIO1 clock input/output
P46 : PWM0A output
P47 : PWM0Boutput
Interrupt acknowledge type
INT6, INT7 : H level, L level, H edge, L edge, both edges
Port 5
I/O
I/O
I/O
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
HOLD release input
P50 to P57
Port 0 interrupt input
Port 6
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
Pin functions
AN0 (P60) to AN7 (P67) : AD converter input port
8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
Pin functions
P60 to P67
Port 7
P70 to P77
AN8 (P70) to AN15 (P77) : AD converter input port
Continued on next page.
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LC88FC3K0A
Continued from preceding page.
Description
Pin Name
Port A
I/O
I/O
8-bit I/O port
I/O specifiable in 1-bit units
PA0 to PA7
Pull-up resistors can be turned on and off in 1 bit units
Multiplexed pin functions
PA0 : SIO4 data output
PA1 : SIO4 data input/pulse input/output
PA2 : SIO4 clock input/output
PA3 : SIO4 chip select input
PA4 : SLIIC0 clock input
PA5 : SLIIC0 bus input/output/data input
PA6 : SLIIC0 data output (used in 3-wire SIO mode)
Port B
I/o
7-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
Multiplexed pin functions
PB0 to PB6
PB4 : SMIIC1 clock input/output
PB5 : SMIIC1 bus input/output/data input
PB6 : SMIIC1 data output (used in 3-wire SIO mode)
5-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units(PC2)
Pin functions
Port C
I/O
PC0 to PC4
PC0 : 32.768 kHz crystal oscillator input
PC1 : 32.768 kHz crystal oscillator output
PC2 : FILT of VCO
PC3 : Ceramic oscillator input
PC4 : Ceramic oscillator output/VCO output
6-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1 bit units
TEST pin
Used to communicate with on-chip debugger.
Connects an external 100 k pull-down resistor.
Port D
I/O
I/O
I/O
PD0 to PD5
TEST
RESB
Reset pin
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LC88FC3K0A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected in
Port Name
Output Type
Pull-up Resistor
Units of
P00 to P07
CMOS
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
PA0 to PA7
PB0 to PB6
P60 to P67
P70 to p77
PD0 to PD5
PC2
Able to program special
functions’output type from CMOS
output or Nch-opendrain
1 bit
Programmable
CMOS
N-channel open drain
(32.768 kHz crystal oscillator input)
Nch-open drain
(32.768k kHz crystal oscillator
output)
PC0
None
None
PC1
CMOS
(ceramic oscillator input)
CMOS
PC3
PC4
None
None
(ceramic oscillator output)
* Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins.
Example 1 : When data is being backed up in the HOLD mode, the H level signals to the output ports are fed
by the backup capacitors.
LSI
V
1
DD
Power
supply
For buckup
V
2
DD
V
V
3
4
DD
DD
V
1
2 V 3 V
SS
4
SS
V
SS
SS
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14
LC88FC3K0A
Example 2 : When data is being backed up in the HOLD mode, the H level output at any ports is not
sustained and is unpredictable.
LSI
V
V
V
V
1
2
3
4
DD
DD
DD
DD
Power
supply
For buckup
V
1 V 2 V 3 V
SS SS
4
SS
SS
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15
LC88FC3K0A
■ Absolute Maximum Ratings at Ta=25C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
max
Conditions
V
DD
[V]
min
unit
V
Maximum supply
voltage
V
V
V
1, V 2,
DD DD
V
1=V 2=V
DD DD
= V 4
DD
3
DD
DD
+4.6
0.3
3, V
DD
4
DD
Input voltage
VI (1)
RESB
V
DD
+0.3
0.3
0.3
Input/output voltage VIO (1)
Ports 0, 1, 2
Ports 3, 4, 5
Ports 6, 7
VDD
+0.3
Ports A, B, C, D
Ports 0, 1, 2, 3
P40 to P45
Ports 7, A, D
PB2 to PB6
P46, P47
Peak output
current
IOPH (1)
CMOS output selected
Per applicable pin
7.5
IOPH (2)
IOPH (3)
Per applicable pin
Per applicable pin
12.5
4.5
PB0, PB1
Port 5, 6
PC0 to PC4
Ports 0, 1, 2, 3
P40 to P45
Ports 5, 6, 7, A
PB2 to PB6
Ports D
Average output IOMH (1)
current
(Note 1-1)
CMOS output selected
Per applicable pin
5
IOMH (2)
IOMH (3)
P46, P47
PB0, PB1
Port 5, 6
PC0 to PC4
Per applicable pin
Per applicable pin
10
3
Total output
current
Pprts 5
PC0 to PC4
Port 6
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
IOAH (1)
IOAH (2)
IOAH (3)
IOAH (4)
IOAH (5)
IOAH (6)
IOAH (7)
IOAH (8)
IOAH (9)
IOAH (10)
IOAH (11)
IOAH (12)
10
10
20
20
20
40
20
20
40
20
20
40
mA
Port 5, 6
PC0 to PC4
Ports 1,D1
P20 to P21
P22 to P27
Ports 1, 2, D
Ports 4
Ports 0, 3
Ports 0, 3, 4
Ports B, 7
Ports A
Ports 7, A, B
Note 1-1 : Average output current refers to the average of output currents measured for a period of 100 ms.
Continued on next page.
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16
LC88FC3K0A
Continued from preceding page.
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
DD
[V]
min
unit
Peak output
current
IOPL (1)
Ports 0, 1, 3, 4
Ports 7, D
Per applicable pin
P20, P21, P24 to P27
PA0 to PA4, PA6,
PA7
15
PB0 to PB4, PB6,
IOPL (2)
P22, P23
Per applicable pin
PA4, PA5
20
PB4, PB5
IOPL (3)
IOML (1)
Ports 5, 6
Per applicable pin
Per applicable pin
7.5
PC0 to PC4
Ports 0, 1, 3, 4
Ports 7, D
Average output
current
(Note 1-1)
P20, P21, P24 to P27
PA0 to PA4, PA6,
PA7
12.5
15
PB0 to PB4, PB6,
PB7
P22, P23
PA4, PA5
PB4, PB5
IOML (2)
IOML (3)
Per applicable pin
Per applicable pin
Ports 5, 6
PC0 to PC4
5
Total output
current
Ports 5
PC0 to PC2
Port 6
PC3 to PC4
Port 5, 6
PC0 to PC4
Ports 1, D
P20, P21
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
IOAL (1)
IOAL (2)
IOAL (3)
IOAL (4)
IOAL (5)
IOAL (6)
IOAL (7)
IOAL (8)
IOAL (9)
IOAL (10)
IOAL (11)
IOAL (12)
Pd max
mA
10
10
20
35
35
70
35
35
70
35
35
70
P22 to P27
Ports 1, 2, D
Port 4
Port 0, 3
Port 0, 3, 4
Port 7, B
Port A
Port 7, A, B
TQFP100
Allowable power
dissipation
Ta=40 to +85C
Package with thermal
resistance bord
460
mW
(Note 1-2)
Operating ambient
temperature
Storage ambient
temperature
Topr
Tstg
+85
40
55
C
+125
Note 1-1 : Average output current refers to the average of output currents measured for a period of 100 ms.
Note 1-2 : SEMI standerds thermal resistance board (size : 76.1 114.3 1.6 tmm, glass epoxy) is used.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
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17
LC88FC3K0A
■ Allowable Operating Conditions at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS SS SS SS
Specification
typ max
Parameter
Symbol Applicable Pin/Remarks
Conditions
V
DD
[V]
min
unit
Operating supply
voltage
V
(1)
V
1=V 2=V
DD
3
0.098s ≤ tCYC ≤ 66s
DD
DD
DD
DD
2.7
2.0
3.6
3.6
Memory
VHD
V
1=V 2=V
DD DD
3
RAM and register contents
sustained in HOLD mode
sustaining supply
voltage
0.3V
DD
V
High level input
voltage
VIH (1)
VIH (2)
Ports 0, 1, 2, 3, 4
Port 5, A, B
DD
DD
2.7 to 3.6
+0.7
0.3V
V
Ports 6, 7, D,PC2
DD
+0.7
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
VIH (3)
VIH (4)
VIL (1)
RESB
0.75V
V
V
DD
DD
PC0, PC1, PC3, PC4
P22, P23, PA4, PA5,
PB4, PB5 I2C side
V
0.7V
DD
DD
Low level input
voltage
When ports 1, 2, 3, 4,
5, A and port B,
PnFSAn=0
V
SS
0.2V
2.7 to 3.6
2.7 to 3.6
DD
DD
Ports 0, 6, 7, D, PC2
When ports 1, 2, 3, 4,
5, A and port B,
VIL (2)
V
SS
0.2V
PnFSAn=1
VIL (3)
VIL (4)
tCYC
CF1, RESB
V
V
0.25V
2.7 to 3.6
2.7 to 3.6
SS
DD
PC0, PC1,PC3, PC4
P22, P23, PA4, PA5,
PB4, PB5 I2C side
0.3V
SS
DD
Instruction cycle
time
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
0.098
0.1
66
10
20
s
(Note 2-1)
External system
clock frequency
FEXCF (1) CF1
CF2 pin open
System clock frequency
division ratio = 1/1
External system clock
DUTY505%
MHz
CF2 pin open
System clock frequency
division ratio = 1/2
0.2
Note 2-1 : Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is
1/1 and 2/FmCF when the ratio is 1/2.
Continued on next page.
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18
LC88FC3K0A
Continued from preceding page.
Specification
Applicable Pin
/Remarks
Parameter
Oscillation
Symbol
FmCF
Conditions
V
[V]
min
typ
max
unit
DD
10 MHz ceramic oscillator
mode
PC3(CF1),
PC4(CF2)
frequency range
(Note 2-2)
2.7 to 3.6
10
See Fig. 1.
MHz
Internal RC oscillation
FmRC
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
0.5
18
1.0
30
2.0
45
Internal low-speed RC
oscillation
FmSLRC
FsX'tal
32.768 kHz crystal oscillator
mode
XT1, XT2
kHz
32.768
See Fig. 2.
VCO oscillator
When setting FRQSEL=0
See Fig. 9.
FmVCO(1)
FmVCO(2)
FmVCO(5)
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
12
38
28
70
VCO oscillator
When setting FRQSEL=1
See Fig. 9.
MHz
VCO oscillator
Note 2-3
Note 2-2 : See Tables 1 and 2 for oscillator constant values.
Note 2-3 : VCO oscillation frequency = Ceramic oscillator frequency Setting point of SELREF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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19
LC88FC3K0A
■ Electrical Characteristics at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
DD
[V]
min
typ
max
unit
Output disabled
Pull-up resistor off
=V
High level input
current
IIH (1) Ports 0, 1, 2
Ports 3, 4, 5
V
IN DD
Ports 6, 7
2.7 to 3.6
2.7 to 3.6
1
(including output Tr. off
leakage current)
Ports A, B,C, D
RESB
A
Output disabled
Low level input
current
IIL (1) Ports 0, 1, 2
Ports 3, 4, 5
Pull-up resistor off
V =V
IN SS
Ports 6, 7
1
(including output Tr. off
leakage current)
Ports A, B, C, D
RESB
IOH=0.4mA
IOH=0.2mA
High level output
voltage
VOH (1) Ports 0, 1, 2, 3
Ports 5, 6
V
V
0.4
3.0 to 3.6
2.7 to 3.6
DD
Ports A, D, PC2
P40 to P45
VOH (2)
0.4
DD
PB2 to PB6
IOH=1.6mA
IOH=1.0mA
V
V
V
0.4
0.4
0.4
VOH (3) P46, P47
3.0 to 3.6
2.7 to 3.6
3.0 to 3.6
DD
DD
DD
PB0, PB1
VOH (4)
IOH=1.0mA
IOH=0.4mA
IOL=1.6mA
VOH (5) PC0, PC1,
PC3, PC4,
VOH (6)
V
DD
0.4
2.7 to 3.6
Low level output
voltage
VOL (1) Ports 0, 1, 3 , 4
Ports 5, 6, 7, D
PC2
V
3.0 to 3.6
0.4
0.4
P20 to P21,
IOL=1.0mA
VOL (2)
P24 to P27
PA0 to PA3
PA6 to PA7
2.7 to 3.6
PB0 to PB3, PB6
VOL (3) P22, P23,
IOL=3.0mA
IOL=1.3mA
3.0 to 3.6
2.7 to 3.6
0.4
0.4
PA4, PA5,
VOL (4)
PB4, PB5
IOL=1.0mA
IOL=0.4mA
VOL (5) PC0, PC1,
3.0 to 3.6
2.7 to 3.6
0.4
0.4
PC3, PC4,
VOL (6)
Pull-up resistor
Rpu (1) Ports 0, 1, 2, 3
Ports 4, 5, 6, 7
VOH=0.9V
DD
3.0 to 3.6
2.7 to 3.6
15
15
35
35
80
k
Ports A, B, D, PC2
Rpu (2)
VHYS
100
Hysteresis voltage
RESB
When ports 1, 2, 3,
4, A, B
0.1V
DD
2.7 to 3.6
2.7 to 3.6
V
PnFSAn=1
All pins
Pin capacitance
CP
Pins other than that under
test
V =V
IN SS
10
pF
f=1 MHz
Ta=25C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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20
LC88FC3K0A
■ Serial I/O Characteristics at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS SS SS SS
Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
See Fig. 6.
Pin/Remarks
V
DD
[V]
min
4
typ
max
unit
tSCK (1)
SCK0 (P12)
Low level
pulse width
High level
pulse width
tSCKL (1)
2
2
tSCKH (1)
Automatic communication
mode
tSCKHA (1)
6
2.7 to 3.6
See Fig. 6.
tCYC
Automatic communication
mode
tSCKHBSY
(1a)
23
See Fig. 6.
Mode other than automatic
communication mode
See Fig. 6.
tSCKHBSY
(1b)
4
4
CMOS output selected
See Fig. 6.
Period
tSCK (2)
tSCKL (2)
tSCKH (2)
tSCKHA (2)
SCK0 (P12)
Low level
pulse width
High level
pulse width
1/2
1/2
tSCK
Automatic communication
mode
6
4
2.7 to 3.6
CMOS output selected
See Fig. 6.
Automatic communication
mode
tSCKHBSY
(2a)
tCYC
23
CMOS output selected
See Fig. 6.
Mode other than automatic
communication mode
See Fig. 6.
tSCKHBSY
(2b)
4
Specified with respect to
rising edge of SIOCLK
See Fig. 6.
Data setup time
Data hold time
tsDI (1)
thDI (1)
SI0 (P11),
SB0 (P11)
0.03
2.7 to 3.6
0.03
(Note 4-1-2)
(Note 4-1-2)
Output delay
time
tdD0 (1)
SO0 (P10),
SB0 (P11)
1tCYC
+0.05
s
2.7 to 3.6
tdDO (2)
1tCYC
+0.05
Note 4-1-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an
output change begins in the open drain output mode. See Fig. 6.
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21
LC88FC3K0A
SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
See Fig. 6.
Pin/Remarks
V
DD
[V]
min
2
typ
max
unit
tSCK (3)
SCK0 (P12)
Low level
pulse width
High level
pulse width
tSCKL (3)
1
1
2.7 to 3.6
tCYC
tSCKH (3)
tSCKHBSY
(3)
2
Specified with respect to
rising edge of SIOCLK
See Fig. 6.
Data setup time
Data hold time
tsDI (2)
thDI (2)
SI0 (P11),
SB0 (P11)
0.03
2.7 to 3.6
2.7 to 3.6
0.03
s
(Note 4-2-2)
Output delay
time
tdD0 (3)
SO0 (P10),
SB0 (P11)
1tCYC
+0.05
Note 4-2-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-2-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an
output change begins in the open drain output mode. See Fig. 6.
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22
LC88FC3K0A
SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
Pin/Remarks
V
DD
[V]
min
4
typ
max
unit
tSCK (4)
SCK1 (P45) See Fig. 6.
Low level
pulse width
High level
pulse width
tSCKL (4)
2
2
tSCKH (4)
tSCKHA (4)
Automatic communication
mode
See Fig. 6.
6
2.7 to 3.6
tCYC
tSCKHBSY
(4a)
Automatic communication
mode
23
See Fig. 6.
tSCKHBSY
(4b)
Mode other than automatic
communication mode
See Fig. 6.
4
4
Period
tSCK (5)
SCK1 (P45) CMOS output selected
See Fig. 6.
Low level
pulse width
High level
pulse width
tSCKL (5)
tSCKH (5)
tSCKHA (5)
1/2
1/2
tSCK
Automatic communication
mode
6
4
CMOS output selected
See Fig. 6.
2.7 to 3.6
tSCKHBSY
(5a)
Automatic communication
mode
tCYC
23
CMOS output selected
See Fig. 6.
tSCKHBSY
(5b)
Mode other than automatic
communication mode
See Fig. 6.
4
Data setup time
Data hold time
tsDI (3)
thDI (3)
SI1 (P44),
SB1 (P44)
Specified with respect to
rising edge of SIOCLK
See Fig. 6.
0.03
0.03
2.7 to 3.6
Output delay
time
tdD0 (4)
tdDO (5)
SO1 (P43), (Note 4-3-2)
SB1 (P44)
1tCYC
+0.05
s
2.7 to 3.6
(Note 4-3-2)
1tCYC
+0.05
Note 4-3-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an
output change begins in the open drain output mode. See Fig. 6.
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23
LC88FC3K0A
SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
Pin/Remarks
V
DD
[V]
min
2
typ
max
unit
tSCK (6)
SCK1 (P45) See Fig. 6.
Low level
pulse width
High level
pulse width
tSCKL (6)
1
1
2.7 to 3.6
tCYC
tSCKH (6)
tSCKHBSY
(6)
2
Data setup time
Data hold time
tsDI (4)
thDI (4)
SI1 (P44),
SB1 (P44)
Specified with respect to
0.03
rising edge of SIOCLK
See Fig. 6.
2.7 to 3.6
2.7 to 3.6
0.03
s
Output delay
time
tdD0 (6)
SO1 (P43), (Note 4-4-2)
SB1 (P44)
1tCYC
+0.05
Note 4-4-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-4-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an
output change begins in the open drain output mode. See Fig. 6.
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24
LC88FC3K0A
SIO4 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-5-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
Pin/Remarks
V
DD
[V]
min
4
typ
max
unit
tSCK (7)
SCK4 (PA2) See Fig. 6.
Low level
pulse width
High level
pulse width
tSCKL (7)
2
2
tSCKH (7)
tSCKHA (7)
Automatic communication
mode
See Fig. 6.
6
2.7 to 3.6
tCYC
tSCKHBSY
(7a)
Automatic communication
mode
23
See Fig. 6.
tSCKHBSY
(7b)
Mode other than automatic
communication mode
See Fig. 6.
4
4
Period
tSCK (8)
SCK4 (PA2) CMOS output selected
See Fig. 6.
Low level
pulse width
High level
pulse width
tSCKL (8)
tSCKH (8)
tSCKHA (8)
1/2
1/2
tSCK
Automatic communication
mode
6
4
CMOS output selected
See Fig. 6.
2.7 to 3.6
tSCKHBSY
(8a)
Automatic communication
mode
tCYC
23
CMOS output selected
See Fig. 6.
tSCKHBSY
(8b)
Mode other than automatic
communication mode
See Fig. 6.
4
Data setup time
Data hold time
tsDI (5)
thDI (5)
SI4 (PA1), Specified with respect to
0.03
0.03
SB4 (PA1)
rising edge of SIOCLK
See Fig. 6.
2.7 to 3.6
Output delay
time
tdD0 (7)
tdDO (8)
SO4 (PA0), (Note 4-5-2)
SB14(PA1)
1tCYC
+0.05
s
2.7 to 3.6
(Note 4-5-2)
1tCYC
+0.05
Note 4-5-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-5-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an
output change begins in the open drain output mode. See Fig. 6.
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25
LC88FC3K0A
SIO4 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-6-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
Pin/Remarks
V
DD
[V]
min
2
typ
max
unit
tSCK (9)
SCK4 (P45) See Fig. 6.
Low level
pulse width
High level
pulse width
tSCKL (9)
1
1
2.7 to 3.6
tCYC
tSCKH (9)
tSCKHBSY
(9)
2
Data setup time
Data hold time
tsDI (6)
thDI (6)
SI4 (P44),
SB4 (P44)
Specified with respect to
0.03
rising edge of SIOCLK
See Fig. 6.
2.7 to 3.6
2.7 to 3.6
0.03
s
Output delay
time
tdD0 (9)
SO4 (P43), (Note 4-6-2)
SB4(P44)
1tCYC
+0.05
Note 4-6-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an
output change begins in the open drain output mode. See Fig. 6.
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26
LC88FC3K0A
SMIIC0 Simple SIO Mode Input/Output Characteristics (Note 4-7-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
See Fig. 6.
Pin/Remarks
V
DD
[V]
min
4
typ
max
unit
tSCK (10)
SM0CK
(P22)
Low level
pulse width
High level
pulse width
Period
tSCKL (10)
tSCKH (10)
tSCK (11)
tSCKL (11)
tSCKH (11)
tsDI (7)
2.7 to 3.6
2
2
4
tCYC
SM0CK
(P22)
CMOS output selected
See Fig. 6.
Low level
pulse width
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SM0DA
(P23),
Specified with respect to
rising edge of SIOCLK
See Fig. 6.
0.03
0.03
Data hold time
thDI (7)
Output delay time tdD0 (10)
SM0DO
(P24),
Specified with respect to
falling edge of SIOCLK
Specified as interval up to
time when output state starts
changing.
s
SM0DA
(P23)
1tCYC
+0.05
See Fig. 6.
Note 4-7-1 : These specifications are theoretical values. Add margin depending on its use.
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27
LC88FC3K0A
SMIIC0 I2C Mode Input/Output Characteristics (Note 4-8-1) (Note 4-8-2) (Note 4-8-4)
Specification
Applicable
Parameter
Period
Symbol
tSCL
Conditions
See Fig. 8.
Pin/Remarks
V
DD
[V]
min
5
typ
max
unit
SM0CK
(P22)
Low level
tSCLL
tSCLH
tSCLx
tSCLLx
tSCLHx
tsp
2.7 to 3.6
2.5
2
pulse width
High level
pulse width
Period
Tfilt
SM0CK
(P22)
Specified as interval up to
time when output state starts
changing.
10
Low level
pulse width
High level
pulse width
2.7 to 3.6
2.7 to 3.6
1/2
1/2
tSCL
SM0CK (P22) See Fig. 8.
SM0CK and SM0DA
pins input spike
SM0DA (P23)
1
Tfilt
Tfilt
suppression time
tBUF
SM0CK (P22) See Fig. 8.
2.5
5.5
SM0DA (P23)
tBUFx
SM0CK (P22) Standard clock mode
SM0DA (P23) Specified as interval up to
time when output state starts
changing.
Bus release time
between start and
stop
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
μs
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
1.6
2.0
2.5
4.1
tHD;STA
SM0CK (P22) When SMIIC register
SM0DA (P23)
control bit,
I2CSHDS=0
See Fig. 8.
Tfilt
When SMIIC register
control bit
I2CSHDS=1
See Fig. 8.
Start/restart
condition hold
time
tHD;STAx SM0CK (P22) Standard clock mode
SM0DA (P23) Specified as interval up to
time when output state starts
changing.
μs
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
1.0
1.0
tSU;STA
SM0CK (P22) See Fig. 8.
Tfilt
SM0DA (P23)
tSU;STAx SM0CK (P22) Standard clock mode
SM0DA (P23) Specified as interval up to
time when output state starts
5.5
1.6
Restart condition
setup time
changing.
μs
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
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28
LC88FC3K0A
Specification
typ max
Applicable
Pin/Remarks
Parameter
Symbol
Conditions
V
DD
[V]
Min
1.0
Unit
Tfilt
tSU;STO
SM0CK (P22) See Fig. 8.
SM0DA (P23)
tSU;STOx SM0CK (P22) Standard clock mode
SM0DA (P23) Specified as interval up to
time when output state starts
Stop condition
setup time
4.9
1.1
2.7 to 3.6
changing.
s
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
tHD;DAT SM0CK (P22) See Fig. 8.
SM0DA (P23)
0
1
Data hold time
2.7 to 3.6
Tfilt
Tfilt
tHD;DATx SM0CK (P22) Specified as interval up to
time when output state starts
changing.
SM0DA (P23)
1.5
tSU;DAT
SM0CK (P22) See Fig. 8.
SM0DA (P23)
1
Data setup time
2.7 to 3.6
2.7 to 3.6
tSU;DATx SM0CK (P22) Specified as interval up to
1tSCL-
1.5Tfilt
time when output state starts
changing.
SM0DA (P23)
tF
tF
SM0CK (P22) See Fig. 8.
SM0DA (P23)
300
SM0CK (P22) When SMIIC register
SM0CK and
SM0DA pins fall
time
20+0.1Cb
control bits
SM0DA (P23)
ns
3
250
100
(Note 4-8-3)
PSLW=1, P5V=1
SM0CK, SM0DA port
output FAST mode
Cb ≤ 100pF
3.0 to 3.6
Note 4-8-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-8-2 : The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
tCYC1
tCYC2
tCYC3
tCYC4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range :
250 ns ≥ Tfilt > 140 ns
Note 4-8-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF
Note 4-8-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100 kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400 kHz
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29
LC88FC3K0A
SMIIC1 Simple SIO Mode Input/Output Characteristics (Note 4-9-1)
Specification
Applicable
Parameter
Period
Symbol
Conditions
See Fig. 6.
Pin/Remarks
V
DD
[V]
min
4
typ
max
unit
tSCK (12)
SM0CK
(PB4)
Low level
pulse width
High level
pulse width
Period
tSCKL (12)
tSCKH (12)
tSCK (13)
tSCKL (13)
tSCKH (13)
tsDI (8)
2.7 to 3.6
2
2
4
tCYC
SM0CK
(PB4)
CMOS output selected
See Fig. 6.
Low level
pulse width
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SM0DA
(PB5),
Specified with respect to
rising edge of SIOCLK
See Fig. 6.
0.03
0.03
Data hold time
thDI (8)
Output delay time tdD0 (12)
SM0DO
(PB6),
Specified with respect to
falling edge of SIOCLK
Specified as interval up to
time when output state starts
changing.
s
SM0DA
(PB5)
1tCYC
+0.05
See Fig. 6.
Note 4-9-1 : These specifications are theoretical values. Add margin depending on its use.
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30
LC88FC3K0A
SMIIC1 I2C Mode Input/Output Characteristics (Note 4-10-1) (Note 4-10-2) (Note 4-10-4)
Specification
Applicable
Parameter
Period
Symbol
tSCL
Conditions
See Fig. 8.
Pin/Remarks
V
DD
[V]
Min
5
typ
max
unit
SM1CK
(PB4)
Low level
tSCLL
tSCLH
tSCLx
tSCLLx
tSCLHx
tsp
2.7 to 3.6
2.5
2
pulse width
High level
pulse width
Period
Tfilt
SM1CK
(PB4)
Specified as interval up to
time when output state starts
changing.
10
Low level
pulse width
High level
pulse width
2.7 to 3.6
2.7 to 3.6
1/2
1/2
tSCL
SM1CK (PB4) See Fig. 8.
SM0CK and SM0DA
pins input spike
SM1DA (PB5)
1
Tfilt
Tfilt
suppression time
tBUF
SM1CK (PB4) See Fig. 8.
2.5
5.5
SM1DA (PB5)
tBUFx
SM1CK (PB4) Standard clock mode
SM1DA (PB5) Specified as interval up to
time when output state starts
changing.
Bus release time
between start and
stop
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
μsec
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
1.6
2.0
2.5
4.1
tHD;STA
SM1CK (PB4) When SMIIC register
SM1DA (PB5) control bit,
I2CSHDS=0
See Fig. 8.
Tfilt
When SMIIC register
control bit
I2CSHDS=1
Start/restart
condition hold
time
See Fig. 8.
tHD;STAx SM1CK (PB4) Standard clock mode
SM1DA (PB5) Specified as interval up to
time when output state starts
changing.
μsec
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
1.0
1.0
tSU;STA
SM1CK (PB4) See Fig. 8.
Tfilt
SM1DA (PB5)
tSU;STAx SM1CK (PB4) Standard clock mode
SM1DA (PB5) Specified as interval up to
time when output state starts
5.5
1.6
Restart condition
setup time
changing.
μsec
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
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31
LC88FC3K0A
Specification
typ max
Applicable
Pin/Remarks
Parameter
Symbol
Conditions
V
DD
[V]
Min
1.0
unit
tSU;STO
SM1CK (PB4) See Fig. 8.
SM1DA (PB5)
Tfilt
tSU;STOx SM1CK (PB4) Standard clock mode
SM1DA (PB5) Specified as interval up to
time when output state starts
Stop condition
setup time
4.9
1.1
2.7 to 3.6
changing.
sec
High-speed clock mode
Specified as interval up to
time when output state starts
changing.
tHD;DAT SM1CK (PB4) See Fig. 8.
SM1DA (PB5)
0
1
Data hold time
2.7 to 3.6
Tfilt
Tfilt
tHD;DATx SM1CK (PB4) Specified as interval up to
time when output state starts
changing.
SM1DA (PB5)
1.5
tSU;DAT
SM1CK (PB4) See Fig. 8.
SM1DA (PB5)
1
Data setup time
2.7 to 3.6
2.7 to 3.6
tSU;DATx SM1CK (PB4) Specified as interval up to
time when output state starts
changing.
SM1DA (PB5)
1tSCL-1.5Tfilt
tF
tF
SM1CK (PB4) See Fig. 8.
SM1DA (PB5)
300
SM1CK (PB4) When SMIIC register
SM0CK and
SM0DA pins fall
time
20+0.1Cb
control bits
SM1DA (PB5)
ns
3
250
100
(Note 4-10-3)
PSLW=1, PHV=1
SM0CK, SM0DA port
output FAST mode
Cb ≤ 100pF
3 to 3.6
Note 4-10-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-10-2 : The value of Tfilt is determined by the values of the register SMIC1BRG, bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
tCYC1
tCYC2
tCYC3
tCYC4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range :
250 ns ≥ Tfilt > 140 ns
Note 4-10-3 : Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF
Note 4-10-4 : The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as
follows :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100 kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC1BRG as follows :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400 kHz
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32
LC88FC3K0A
SLIIC0 Simple SIO Mode Input/Output Characteristics (Note 4-11-1)
Specification
typ max
Applicable
Parameter
Period
Symbol
Conditions
See Fig. 6.
Pin/Remarks
V
DD
[V]
min
4
unit
tSCK (13)
SL0CK
(PA4)
Low level
pulse width
tSCKL (13)
tSCKH (13)
tsDI (9)
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
2
tCYC
High level
2
pulse width
Data setup time
SL0DA
(PA5),
Specified with respect to
rising edge of SIOCLK
See Fig. 6.
0.03
0.03
Data hold time
thDI (9)
Output delay time tdD0 (13)
SL0DO
(PA6),
SL0DA
(PA5)
Specified with respect to
falling edge of SIOCLK
Specified as interval up to
time when output state starts
changing.
s
1tCYC
+0.05
See Fig. 6.
Note 4-11-1 : These specifications are theoretical values. Add margin depending on its use.
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33
LC88FC3K0A
SLIIC1 I2C Mode Input/Output Characteristics (Note 4-12-1) (Note 4-12-2)
Specification
typ max
Applicable
Parameter
Period
Symbol
tSCL
Conditions
See Fig. 8.
Pin/Remarks
V
DD
[V]
Min
5
unit
SL0CK
(PA4)
Low level
tSCLL
tSCLH
tsp
2.7 to 3.6
2.5
2
Tfilt
pulse width
High level
pulse width
SL0CK (PA4) See Fig. 8.
SL0CK and SL0DA
pins input spike
SL0DA (PA5)
2.7 to 3.6
2.7 to 3.6
1
Tfilt
Tfilt
suppression time
tBUF
SL0CK (PA4) See Fig. 8.
Bus release time
between start and
stop
SL0DA (PA5)
2.5
2.0
tHD;STA
SL0CK (PA4) When SMIIC register
SL0DA (PA5)
control bit,
I2CSHDS=0
See Fig. 8.
Start/restart
condition hold
time
2.7 to 3.6
2.7 to 3.6
Tfilt
Tfilt
When SMIIC register
control bit
2.5
1.0
I2CSHDS=1
See Fig. 8.
tSU;STA
tSU;STO
SL0CK (PA4) See Fig. 8.
Restart condition
setup time
SL0DA (PA5)
SL0CK (PA4) See Fig. 8.
SL0DA (PA5)
Stop condition
setup time
2.7 to 3.6
1.0
Tfilt
tHD;DAT SL0CK (PA4) See Fig. 8.
SL0DA (PA5)
0
1
Data hold time
2.7 to 3.6
Tfilt
Tfilt
tHD;DATx SL0CK (PA4) Specified as interval up to
time when output state starts
changing.
SL0DA (PA5)
1.5
tSU;DAT
SL0CK (PA4) See Fig. 8.
SL0DA (PA5)
1
Data setup time
2.7 to 3.6
tSU;DATx SL0CK (PA4) Specified as interval up to
1tSCL-
1.5Tfilt
time when output state starts
changing.
SL0DA (PA5)
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LC88FC3K0A
Specification
typ max
Applicable
Pin/Remarks
Parameter
Symbol
tF
Conditions
V
DD
[V]
Min
Unit
SL0CK (PA4) See Fig. 8.
SL0DA (PA5)
2.7 to 3.6
300
tF
SL0CK (PA4) When SLIIC0 register
SL0CK and
SL0DA pins fall
time
20+0.1Cb
control bits
SL0DA (PA5)
ns
3
250
100
(Note 4-12-3)
PSLW=1, PHV=1
SL0CK, SL0DA port output
FAST mode
3.0 to 3.6
Cb ≤ 100pF
Note 4-12-1 : These specifications are theoretical values. Add margin depending on its use.
Note 4-12-2 : The value of Tfilt is determined by the values of the register SLIC0PCNT, bits 5 and 4 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
tCYC1
tCYC2
tCYC3
tCYC4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range :
250 ns ≥ Tfilt > 140 ns
Note 4-12-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF
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35
LC88FC3K0A
UART0 Operating Conditions at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Applicable
Pin/Remarks
Parameter
Symbol
UBR0
Conditions
V
[V]
min
4
typ
max
unit
DD
Transfer rate
U0RX (P13),
U0TX (P14),
U0BRG
2.7 to 3.6
8
tBGCYC
(P07)
Note 4-9 : tBGCYC denotes one cycle of the baudrate clock source.
UART2 Operating Conditions at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Applicable
Pin/Remarks
Parameter
Symbol
UBR2
Conditions
V
[V]
min
8
typ
max
unit
DD
Transfer rate
U2RX (P16),
U2TX (P17),
2.7 to 3.6
4096
tBGCYC
Note 4-10: tBGCYC denotes one cycle of the baudrate clock source.
UART3 Operating Conditions at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Applicable
Pin/Remarks
Parameter
Symbol
UBR3
Conditions
V
[V]
min
8
typ
max
unit
DD
Transfer rate
U3RX (P34),
U3TX (P35),
2.7 to 3.6
4096
tBGCYC
Note 4-10 : tBGCYC denotes one cycle of the baudrate clock source.
■ Pulse Input Conditions at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Parameter
Symbol Applicable Pin/Remarks
Conditions
V
DD
[V]
min
typ
max
unit
tCYC
s
High/low level tPIH (1)
pulse width tPIL (1)
INT0 (P30),
INT1 (P31),
INT2 (P32),
INT3 (P33),
INT4 (P20),
INT5 (P21),
INT6 (P40),
INT7 (P41)
Interrupt source flag can be
set.
Event inputs for timers 2 and
3 are enabled.
2.7 to 3.6
2.7 to 3.6
2
tPIL (2)
RESB
Resetting is enabled.
10
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36
LC88FC3K0A
■ AD Converter Characteristics at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
12-bit AD Conversion Mode
Specification
Applicable Pin
/Remarks
Parameter
Resolution
Symbol
Conditions
V
[V]
min
typ
12
max
unit
bit
DD
NAD
AN0 (P60)
to AN7 (P67),
AN8 (P70)
2.7 to 3.6
2.7 to 3.6
Absolute accuracy
Conversion time
ETAD
TCAD12
(Note 6-1)
Conversion time calculated
LSB
16
to AN15 (P77)
3.0 to 3.6
2.7 to 3.6
64
128
115
230
s
Analog input
voltage range
Analog port
input current
VAIN
V
V
2.7 to 3.6
V
SS
DD
1
IAINH
IAINL
VAIN=V
VAIN=V
DD
SS
2.7 to 3.6
2.7 to 3.6
A
1
52
Conversion time calculation formula : TCAD12 = ( AD division ratio +2) tCYC
8-bit AD Conversion Mode
Specification
Applicable Pin
/Remarks
Parameter
Resolution
Symbol
Conditions
V
[V]
min
typ
8
max
unit
bit
DD
NAD
AN0 (P60)
to AN7 (P67),
AN8 (P70)
2.7 to 3.6
2.7 to 3.6
Absolute accuracy
Conversion time
ETAD
TCAD8
(Note 6-1)
LSB
1.5
to AN15 (P77)
Conversion time calculated
3.0 to 3.6
2.7 to 3.6
39
79
71
140
s
Analog input
voltage range
Analog port
input current
VAIN
V
V
2.7 to 3.6
V
SS
DD
1
IAINH
IAINL
VAIN=V
VAIN=V
DD
SS
2.7 to 3.6
2.7 to 3.6
A
1
52
Conversion time calculation formula : TCAD8 = ( AD division ratio +2) tCYC
Note 6-1 : The quantization error (±1/2LSB) is excluded from the absolute accuracy.
Note 6-2 : The conversion time refers to the interval from the time a conversion starting instruction is issued
till the time the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
- The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
- The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD
conversion mode.
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37
LC88FC3K0A
■ Consumption Current Characteristics at Ta=–40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
typ : 3.3V
Specification
Applicable
Pin/Remarks
Parameter
Symbol
Conditions
V
[V]
min
typ
5.0
max
12.0
unit
DD
Normal mode
consumption
current
IDDOP (1)
V
1
DD
FmCF=10 MHz ceramic oscillator
mode
FmX'tal=32.768 kHz crystal oscillator
mode
System clock set to 10 MHz
Internal RC oscillation stopped
1/1 frequency division mode
=V
=V
=V
2
3
4
DD
DD
DD
(Note 7-1)
2.7 to 3.6
mA
IDDOP (2)
IDDOP (3)
FmCF=0Hz (oscillation stopped)
FmX'tal=32.768 kHz crystal oscillator
mode
System clock set to internal RC
oscillation
2.7 to 3.6
2.7 to 3.6
0.8
30
2.1
1/1 frequency division mode
FmCF=0Hz (oscillation stopped)
FmX'tal=32.768 kHz crystal oscillator
mode
System clock set to 32.768 kHz
Internal RC oscillation stopped
1/1 frequency division mode
136
A
Continued on next page.
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38
LC88FC3K0A
Continued from preceding page.
Applicable
Pin/Remarks
Specification
Parameter
Symbol
Conditions
V
DD
[V]
min
typ
max
unit
HALT mode IDDHALT (1)
consumption
current
V
1
HALT mode
FmCF=10 MHz ceramic oscillator
mode
FmX'tal=32.768 kHz crystal oscillator
mode
DD
=V
=V
=V
2
3
4
DD
DD
DD
(Note 7-1)
2.7 to 3.6
1.5
3.2
System clock set to 10 MHz
Internal RC oscillation stopped
1/1 frequency division mode
mA
IDDHALT (2)
HALT mode
FmCF=0Hz (oscillation stopped)
FmX'tal=32.768 kHz crystal oscillator
mode
System clock set to internal RC
oscillation
2.7 to 3.6
0.2
0.8
1/1 frequency division mode
IDDHALT (3)
HALT mode
FmCF=0Hz (oscillation stopped)
FmX'tal=32.768 kHz crystal oscillator
mode
System clock set to 32.768 kHz
Internal RC oscillation stopped
1/1 frequency division mode
2.7 to 3.6
8.5
78
A
Continued on next page.
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39
LC88FC3K0A
Continued from preceding page.
Applicable
Pin/Remarks
Specification
Parameter
Symbol
Conditions
V
[V]
min
typ
0.2
max
50
unit
DD
HOLD mode IDDHOLD (1)
consumption
current
V
1
DD
HOLD mode
CF1=VDD or open
(external clock mode)
HOLD mode
CF1=VDD or open
(external clock mode)
LVD option selected
HOLDX mode
CF1=VDD or open
(external clock mode)
FmX'tal=32.768 kHz crystal
oscillator mode
2.7 to 3.6
2.7 to 3.6
IDDHOLD (2)
1.2
4.6
53
71
HOLDX mode IDDHOLD (3)
consumption
current
A
2.7 to 3.6
2.7 to 3.6
IDDHOLD (4)
HOLDX mode
CF1=VDD or open
(external clock mode)
FmX'tal=32.768 kHz crystal
oscillator mode
5.6
74
LVD option selected
Note 7-1 : The consumption current value includes none of the currents that flow into the output transistor and
internal pull-up resistors.
■ F-ROM Programming Characteristics at Ta=+10 to +55C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Applicable
Pin/Remarks
Parameter
Onboard
programming
current
Onboard
programming
time
Symbol
Conditions
V
[V]
min
typ
max
10
unit
mA
DD
IDDFW (1)
V
1
DD
Microcontroller erase current
current is excluded.
2.7 to 3.6
2.7 to 3.6
2.7 to 3.6
tFW (1)
tFW (2)
2K-byte erase operation
25
45
ms
2-byte programming operation
μs
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40
LC88FC3K0A
■ Power-on Reset (POR) Characteristics at Ta=40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Parameter
Symbol
PORRL
Pin/Remarks
Conditions
Option selected
voltage
min
typ
max
unit
V
Por release
voltage
Select from option.
(Note 8-1)
2.57V
2.87V
2.47
2.77
2.57
2.87
2.72
3.02
Detction voltage POUKS
unknown state
See Fig 10.
(Note 8-2)
0.7
0.95
100
Power supply
rise time
PORIS
Power supply rise time
from 0V to 1.6V.
ms
Note8-1 : The POR release level can be selected out of 2 levels only when the LVD reset function is disabled.
Note8-2 : POR is in an unknown state before transistors start operation.
■ Low Voltage Detection Reset (LVD) Characteristics
at Ta=40 to +85C, V 1=V 2=V 3=V 4=0V
SS
SS
SS
SS
Specification
Parameter
Symbol
LVDET
Pin/Remarks
Conditions
Option selected
voltage
min
typ
max
unit
V
LVD reset
voltage
(Note 9-1)
Select from option.
(Note 9-2)
See Fig 11.
2.81V
2.81V
2.71
2.81
2.96
LVD hysteresis LVHYS
width
60
mV
V
Detection
voltage unknown
state
Low voltage
detection
LVUKS
TLVDW
See Fig 11.
(Note 9-3)
0.7
0.95
LVDET-0.5V
See Fig 12.
minimum width
(Replay
0.2
ms
sensitivity)
Note9-1 : LVD reset voltage specification values do not include hysteresis voltage.
Note9-2 : LVD reset voltage may exceed its specification values when port output state changes and/or when a
large current flows through port.
Note9-3 : LVD is in an unknown state before transistors start operation.
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41
LC88FC3K0A
■ Power Pin Treatment Conditions 1 (V 1, V 1)
DD SS
Connect capacitors that meet the following conditions between the V 1 and V 1 pins :
DD SS
- Connect among the V 1 and V 1 pins and the capacitors C1 and C2 with the shortest possible lead wires,
DD SS
of the same length (L1=L1', L2=L2') wherever possible.
- Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1F or larger.
- The V 1 and V 1 traces must be thicker than the other traces.
DD SS
L2
L1
V
1
SS
C1
C2
V
1
DD
L1’
L2’
■ Power Pin Treatment Conditions 2 (V 2, 3, 4 and V 2, 3, 4)
DD SS
Connect capacitors that meet the following condition between the V 2, 3, 4 and V 2, 3, 4 pins :
DD SS
- Connect among the V 2, 3, 4 and V 2, 3, 4 pins and the capacitor C3 with the shortest possible lead
DD SS
wires, of the same length (L3=L3') wherever possible.
- The capacitance of C3 should be approximately 0.1F or larger.
- The V 2, 3, 4 and V 2, 3, 4 traces must be thicker than the other traces.
DD
SS
L3
V
2,3, 4
SS
C3
V
2,3, 4
DD
L3’
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42
LC88FC3K0A
■ Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
Our Company -designated oscillation characteristics evaluation board and external components with circuit
constant values with which the oscillator vendor confirmed normal and stable oscillation.
■ Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator
Oscillation
Stabilization Time
Operating
Voltage
Range
[V]
Circuit Constant
Nominal
Frequency
Vendor Name
MURATA
Resonator
Remarks
Rf
Rd2
[]
C3
[pF]
C4
typ
[ms]
max
[ms]
[pF]
[]
C1, C2
integrated type
CSTCE10M0G52-R0
CSTLS10M0G53-B0
(10)
(10) OPEN
680
2.2 to 2.6
0.02
0.2
10 MHz
C1, C2
integrated type
(15)
(15) OPEN
680
2.2 to 3.6
0.02
0.2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized
after V goes above the lower limit level of the operating voltage range (see Figure 4)
DD
■ Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a
Our Company -designated oscillation characteristics evaluation board and external components with circuit
constant values with which the oscillator vendor confirmed normal and stable oscillation.
■ Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator
Oscillation
Stabilization Time
Circuit Constant
Operating Voltage
Nominal
Frequency
Vendor Name Resonator
Range
[V]
Remarks
Rf2
Rd2
[]
C3
C4
typ
[s]
max
[s]
[pF] [pF]
[]
EPSON
MC-306
32.768 kHz
10 10
Open 330K
2.2 to 3.6
1.0
3.0
CL=7.0pF
TOYOCOM
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized
after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required
for the oscillation to get stabilized after the HOLD mode is released (see Figure 4).
Note : The traces to and from the components that are involved in oscillation should be kept as short as possible
as the oscillation characteristics are affected by their trace pattern.
CF1
CF2
XT1
XT2
Rf1
CF
Rf2
Rd1
C2
Rd2
C4
C1
C3
X’tal
Figure 1. CF oscillator circuit
Figure 2. XT Oscillator Circuit
0.5V
DD
Figure 3. AC Timing Measurement Point
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43
LC88FC3K0A
V
DD
Operating V
DD
Power
RESB
lower limit
0V
Reset time
Internal RC
oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX'tal
Initialization
instruction execution
Reset
User instruction execution
Operating Unpredictable
mode
Reset Time and Oscillation Stabilization Time
HOLD
release
No HOLD release signal
HOLD release signal valid
Interrupt operation
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX'tal
XT1, XT2
State
HOLD
HALT
Instruction execution
HOLD Release and Oscillation Stabilization Time
Figure 4. Oscillation Stabilization Time Timing Charts
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44
LC88FC3K0A
V
DD
Note :
R
C
RES
Reset signal must be present when power
supply rises.
Determine the value of C
that the reset signal is present for 10 s after
the supply voltage gets stabilized.
RES
and R so
RES
RES
RES
Figure 5. Reset Circuit
tSCKHBSY
tSCKHBSY
RUN:
SIOCLK:
DATAIN:
DI0
DI1
DI6
DI7
DI8
DIx
DATAOUT:
DO0
DO1
DO6
DO7
DO8
DOx
Data transfer period
(SIO0 and SIO1 only)
tSCK
SIOCLK:
tSCKL
tSCKH
thDI
tsDI
DATAIN:
DATAOUT:
Data transfer period
(SIO0 and SIO1 only)
SIOCLK:
DATAIN:
tSCKL
tSCKHA
thDI
tsDI
tdDO
DATAOUT:
* Remarks: DIx and DOx denote the last bits communicated; x=0 to 32768
Figure 6. Serial I/O Waveforms
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45
LC88FC3K0A
tPIL
tPIH
Figure 7. Pulse Input Timing Signal Waveform
P
S
Sr
P
SDA
SCK
tBUF
tHD;STA tR
tF
tHD;STA
tsp
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S : Start condition
P : Stop condition
Sir : Restart condition
Figure 8. I2C Timing
1k
PC2/FILT
+
-
2.2F
Cfs
V
1
SS
Cfs=OPEN
Figure 9. Recommended FILT Circuit
* Take at least 50ms to oscillation to stabilize after PLL is started.
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46
LC88FC3K0A
POR release voltage
(PORRL)
(a)
(b)
V
DD
Reset period
Reset period
100μs or longer
Unknown-state
(POUKS)
RES#
Figure 10. Waveform observed when only POR is used (LVD not used)
(RESET pin : Pull-up resistor R only)
RES
• The POR function generates a reset only when power is turned on starting at the V level.
SS
• No stable reset will be generated if power is turned on again when the power level does not go
down to the V
level as shown in (a). If such a case is anticipated, use the LVD function
SS
together with the POR function or implement an external reset circuit.
• A reset is generated only when the power level goes down to the V level as shown in (b) and
SS
power is turned on again after this condition continues for 100μs or longer.
LVD hysteresis width
LVD release voltage
(LVDET+LVHYS)
(LVHYS)
V
DD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES#
Figure 11. Waveform observed when both POR and LVD functions are used
(RESET pin : Pull-up resistor R only)
RES
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry
cycles near the detection level.
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47
LC88FC3K0A
V
DD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
V
SS
Figure 12. Low voltage detection minimum width
(Example of momentary power loss / Voltage variation waveform)
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
900 / Tray JEDEC
TQFP 100, 14x14
(Pb-Free / Halogen Free)
LC88FC3K0AUTJ-2H
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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