LC898249XHTBG [ONSEMI]
闭环 AF 控制 LSI;
| 型号： | LC898249XHTBG |
| 厂家： | 
ONSEMI |
| 描述： | 闭环 AF 控制 LSI |
| 文件： | 总9页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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AF Control LSI
LC898249XH
Overview
This LSI is Closed−Auto Focus control LSI equipped with hall
sensor. It consists of 1 system of feedback circuit and constant current
driver. It has also a built−in EEPROM and temperature sensor.
WLCSP6, 0.86x1.75x0.265
CASE 567XD
Features
MARKING DIAGRAM
• Built−in Equalizer Circuit Using Digital Operation
♦ AF Control Equalizer Circuit
8249XH
ALYWW
♦ Any Coefficient can be Specified by 2−wire Serial I/F (TWIF)
• 2−wire Serial Interface
2
8249XH = Specific Device Code
(The Communication Protocol is Compatible with I C)
A
L
Y
= Assembly Location
= Wafer Lot
= Year
♦ 4 Selectable Slave Addresses
− 50h(W)/51h(R), 53h(R)
− 74h(W)/75h(R), 77h(R)
− E8h(W)/E9h(R), EBh(R)
WW
= Work Week
− E4h(W)/E5h(R), E7h(R) factory−configured
Right Side Addresses are Used at the Access of Built−in EEPROM
• Built−in A/D Converter
ORDERING INFORMATION
†
Device
LC898249XHTBG
Package
Shipping
4000 /
Tape & Reel
• Built−in D/A Converter
WLCSP6
♦ Hall Offset
♦ Constant Current Bias
• Built−in Hall Sensor
♦ Si Hall Sensor
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Built−in EEPROM
♦ 64 Byte (16 Byte / Page)
• Built−in OSC
• Built−in Constant Current Driver
♦ 150 mA
• Package
♦ WLCSP 6−pin (2 x 3 Pin), Thickness Max 0.29 mm,
with Backside Coat
• Supply Voltage
♦ VDD (2.6 V to 3.3 V)
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
May, 2022 − Rev. 1
LC898249XH/D
LC898249XH
PIN DESCRIPTION
Table 1. PIN DESCRIPTION
Pin Name
Description
I
P
Input
Power Supply, GND
NC
O
Not Connect
Output
B
Bidirection
*Process when pins are not used
• 2−wire serial interface
PIN TYPE “O” – Ensure that it is set to OPEN.
PIN TYPE “I” – OPEN is inhibited. Ensure that it is
connected to the VDD or VSS even when it is unused.
(Please contact onsemi for more information about
selection of VDD or VSS.)
SCL
SDA
I
2−wire serial interface clock pin
2−wire serial interface data pin
B
• Driver interface
OUT1
OUT2
O
O
Driver output (to Actuator)
Driver output (to Actuator)
PIN TYPE “B” – If you are unsure about processing
method on the pin description of pin layout table, please
contact us.
Note that incorrect processing of unused pins may result in
defects.
• Power supply pin
VDD
VSS
P
P
Power Supply
GND
PIN LAYOUT
Table 2. PIN LAYOUT
Circuit Name
Driver
Number of PINs
2
2
2
Power
Logic
B
A
A
B
3
2
1
SDA
SCL
OUT1
VDD
3
2
1
SCL
SDA
OUT2
VSS
OUT1
VDD
OUT2
VSS
BOTTOM VIEW
TOP VIEW
Figure 1. Pin Layout
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2
LC898249XH
BLOCK DIAGRAM
SDA
SCL
2−Wire
Serial I/F
EEPROM
Hall
Offset
/ Bias
Control
logic
OUT1
OUT2
Constant
Current
Driver
AD
EQ
Hall
VGA
OUT1
OUT2
VDD
VSS
more than or
equal to 0.1 mF *
OSC
POR
LDO
*Consider capacitance of capacitor between VDD and VSS. According to power source environment, attach an additional capacitor in
camera module.
Figure 2. Block Diagram
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3
LC898249XH
HALL ELEMENT POSITION
Figure 3. Hall Element Position
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4
LC898249XH
ELECTRICAL CHARACTERISTICS
Table 3. ABSOLUTE MAXIMUM RATINGS (VSS = 0 V)
Symbol Item
33 max
Condition
Rating
Unit
V
V
DD
Supply voltage
Ta ≤ 25°C
Ta ≤ 25°C
−0.3~4.6
V 33,V 33
Input/output voltage
−0.3~V 33 + 0.3
V
I
O
DD
Tstg
Topr
Storage ambient temperature
Operating ambient temperature
−55~125
−30~70
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. ACCEPTABLE OPERATION RANGE (Ta = −30~70°C, VSS = 0 V, 3 V power supply (VDD))
Symbol
33
Item
Min
2.6
0
Typ
2.8
−
Max
Unit
V
V
Supply voltage
3.3
DD
V
IN
Input voltage range
V
DD
33
V
Table 5. DC CHARACTERISTICS (Input / output level at VSS = 0 V, VDD = 2.6 V~3.3V, Ta = −30~70°C)
Symbol
VIH
Item
Condition
Min
1.4
−
Typ
−
Max
−
Unit
V
Applicable Pins
High−level input voltage
Low−level input voltage
Low−level output voltage
CMOS compliant schmitt
SCL, SDA
VIL
−
0.4
0.2
V
VOL
IOL = 2 mA
−
−
V
SDA
Table 6. DRIVER OUTPUT (OUT1, OUT2) (VSS = 0 V, VDD = 2.8 V, Ta = 25°C)
Symbol
Item
Condition
Min
Typ
Max
Unit
Applicable Pins
Ifull
Maximum current
142.5
150
157.5
mA
OUT1, OUT2
Table 7. NON−VOLATILE MEMORY CHARACTERISTICS
Symbol
EN
Item
Condition
Min
Typ
Max
Unit
Applicable Circuit
Endurance
Data retention
Write time
−
10
−
−
−
−
1000
−
Cycles
Years
ms
EEPROM
RT
tWT
20
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5
LC898249XH
AC CHARACTERISTICS
VDD Supply Timing
t2
t3
VDD
VSS
Vbot
t1
SCL / SDA
Figure 4. VDD Supply Timing
It is available to use 2−wire serial interface 5 ms later for Power On Reset of VDD.
Table 8. VDD SUPPLY TIMING
Symbol
Item
Min
−
Typ
−
Max
3
Unit
ms
ms
ms
V
t1
t2
VDD turn on time
2−wire serial interface start time from VDD on
VDD off time
5
−
−
t3
100
−
−
−
Vbot
Bottom Voltage
−
0.1
AC Specification
Figure 5 shows interface timing definition and Table 9 shows electric characteristics.
VIHmin
SDA
VILmax
tBUF
tHD,DAT tSU,DAT
tSU,STA tHD,STA
tf
tLOW
tr
VIHmin
SCL
VILmax
tHD,STA
tr
tf
tSU,STO
Stop
Start
Condition
Repeated
Condition
Start
Condition Condition
Figure 5. 2−wire Serial Interface Timing Definition
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6
LC898249XH
Table 9. ELECTRICAL CHARACTERISTICS FOR 2−WIRE SERIAL INTERFACE (AC CHARACTERISTICS)
Fast−mode
Fast−mode Plus
Pin
Symbol
Item
SCL clock frequency
Name
Min
−
Typ
−
Max
400
−
Min
−
Typ
Max
Unit
kHz
ms
FSCL
SCL
−
−
1000
tHD,STA START condition hold time
SCL
SDA
0.6
−
0.26
−
tLOW
tHIGH
SCL clock Low period
SCL clock High period
SCL
SCL
1.3
0.6
0.6
−
−
−
−
−
−
0.5
−
−
−
−
−
−
ms
ms
ms
0.26
0.26
tSU,STA Setup time for repetition START condition
SCL
SDA
tHD,DAT Data hold time
SCL
0
−
−
−
−
−
−
0.9
−
0
−
−
−
−
−
−
−
−
ms
ns
ns
ns
ms
ms
SDA (Note 1)
(Note 1)
tSU,DAT Data setup time
SCL
SDA
100
50
tr
tf
SDA, SCL rising time
SDA, SCL falling time
SCL
SDA
−
300
300
−
−
120
120
−
SCL
SDA
−
−
tSU,STO STOP condition setup time
tBUF Bus free time between STOP and START
SCL
SDA
0.6
1.3
0.26
0.5
SCL
SDA
−
−
1. This LSI is designed for a condition with typ. 20 ns of hold time. If SDA signal is unstable around falling point of SCL signal, please implement
an appropriate treatment on board, such as inserting a resistor.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6, 0.86x1.75x0.265
CASE 567XD
ISSUE O
DATE 23 OCT 2018
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
L
= Assembly Location
= Wafer Lot
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXX
ALYWW
Y
= Year
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON99381G
WLCSP6, 0.86x1.75x0.265
PAGE 1 OF 1
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