LE25S40FD [ONSEMI]
Serial Flash Memory;
ONSEMI 
LE25S40FD
Advance Information
CMOS LSI
www.onsemi.com
4M-bit (512K x 8)
Serial Flash Memory
Overview
The LE25S40FD is a SPI bus flash memory device with a 4M bit (512K 8-
bit) configuration. It uses a single 1.8V power supply. While making the
most of the features inherent to a serial flash memory device, the
LE25S40FD is housed in an 8-pin ultra-miniature package. All these features
make this device ideally suited to storing program in applications such as
portable information devices, which are required to have increasingly more
compact dimensions. The LE25S40FD also has a small sector erase
capability which makes the device ideal for storing parameters or data that
have fewer rewrite cycles and conventional EEPROMs cannot handle due to
insufficient capacity.
VSOIC8 NB
Features
Read/write operations enabled by single 1.8V power supply: 1.65 to 1.95V supply voltage range
Operating frequency
Temperature range
Serial interface
Sector size
: 40MHz
: 40 to 85C
: SPI mode 0, mode 3 supported
: 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes / page)
Block protect function
Highly reliable read/write
Number of rewrite times: 100,000 times
Small sector erase time : 40ms (typ), 150ms (max)
Sector erase time
Chip erase time
: 80ms (typ), 250ms (max)
: 300ms (typ), 3.0s (max)
Page program time
Status functions
Data retention period
Package
: 6.0ms/256 bytes (typ), 8.0ms/256 bytes (max)
: Ready/busy information, protect information
: 20 years
: VSOIC8 NB
* This product is licensed from Silicon Storage Technology, Inc. (USA).
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 22 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. P0
1
Publication Order Number :
LE25S40FD/D
LE25S40FD
Package Dimensions
unit : mm
VSOIC8 NB
CASE 753AA
ISSUE O
D
NOTES:
NOTE 5
A
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2X
8
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL
CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15mm PER SIDE. DIMENSION E DOES
NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25mm PER
SIDE. DIMENSIONS D AND E ARE DETERMINED AT
DATUM F.
F
0.10 C D
5
NOTE 6
A1
NOTE 4
E
E1
2X 4 TIPS
L2
L
SEATING
PLANE
0.20
C
C
4
DETAIL A
1
8X
b
B
NOTE 5
M
0.25
C
A-B D
TOP VIEW
5. DATUMS A AND B ARE TO BE DETERMINED AT
DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
2X
0.10
C
A-B
NOTE 4
MILLIMETERS
DETAIL A
DIM MIN
MAX
0.85
0.05
0.51
0.25
D
8X
A
A1
b
0.65
0.10
C
0.10
C
0.31
0.17
c
D
E
E1
e
4.90 BSC
A
e
6.00 BSC
3.90 BSC
1.27 BSC
SEATING
PLANE
END VIEW
C
SIDE VIEW
L
0.40
1.27
L2
0.25 BSC
GENERIC
MARKING DIAGRAM*
Figure 1 Pin Assignments
8
RECOMMENDED
SOLDERING FOOTPRINT*
XXXXXXXXX
ALYWX
1
8X
1.52
7.00
XXXXX = Specific Device Code
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
1
8X
0.60
1.27
PITCH
(Note: Microdot may be in either location)
DIMENSION: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
or not be present.
Figure 1 Pin Assignments
CS
1
2
3
4
8
7
6
5
V
DD
HOLD
SCK
SI
SO
WP
V
SS
Top view
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2
LE25S40FD
Figure 2 Block Diagram
4M Bit
X-
Flash EEPROM
Cell Array
DECODER
ADDRESS
BUFFERS
&
LATCHES
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
SCK
SI
SO
CS
WP
HOLD
Table 1 Pin Description
Symbol
SCK
Pin Name
Serial clock
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
SI
Serial data input
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock.
SO
CS
Serial data output
Chip select
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby
status when the logic level of the pin is high.
WP
Write protect
Hold
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
HOLD
Serial communication is suspended when the logic level of this pin is low.
This pin supplies the 1.65 to 1.95V supply voltage.
This pin supplies the 0V supply voltage.
V
Power supply
Ground
DD
V
SS
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LE25S40FD
Device Operation
The read, erase, program and other required functions of the device are executed through the command registers.
The serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the
device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit
units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to
execute operation according to the command that is input.
The LE25S40FD supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Figure 3 I/O waveforms
CS
Mode3
SCK
Mode0
8CLK
SI
Nth bus
1st bus
2nd bus
LSB
(Bit0)
MSB
(Bit7)
High Impedance
DATA
DATA
SO
Table 2 Command Settings
Command
1st bus cycle
2nd bus cycle
A23-A16
3rd bus cycle
4th bus cycle
A7-A0
5th bus cycle
6th bus cycle
RD *1
Nth bus cycle
RD *1
Read
03h
0Bh
A15-A8
A15-A8
A15-A8
A15-A8
RD *1
X
A23-A16
A7-A0
RD *1
RD *1
Small sector erase
Sector erase
20h / D7h
D8h
A23-A16
A7-A0
A23-A16
A7-A0
Chip erase
60h / C7h
02h
Page program
Write enable
A23-A16
A15-A8
A7-A0
PD *2
PD *2
PD *2
06h
Write disable
04h
Power down
B9h
Status register read
Status register write
JEDEC ID read
ID read
05h
01h
DATA
X
9Fh
ABh
X
X
power down
B9h
Exit power down mode
ABh
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input).
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A19 for all commands are "Don't care".
*1: "RD" stands for read data. *2: "PD" stands for page program data.
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LE25S40FD
Table 3 Memory Organization
4M Bit
sector(64KB)
small sector
address space(A23 to A0)
127
to
112
111
to
96
95
to
80
79
to
64
63
to
48
47
to
32
31
to
07F000h
07FFFFh
7
6
5
4
3
2
1
070000h
06F000h
070FFFh
06FFFFh
060000h
05F000h
060FFFh
05FFFFh
050000h
04F000h
050FFFh
04FFFFh
040000h
03F000h
040FFFh
03FFFFh
030000h
02F000h
030FFFh
02FFFFh
020000h
01F000h
020FFFh
01FFFFh
16
15
to
010000h
00F000h
010FFFh
00FFFFh
0
2
1
0
002000h
001000h
000000h
002FFFh
001FFFh
000FFFh
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LE25S40FD
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses
following (03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference.
"Figure 4-a Read" shows the timing waveforms.
Figure 4-a Read
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SCK
SI
Mode0
8CLK
03h
Add.
Add.
Add.
N
N+1
DATA DATA DATA
MSB MSB MSB
N+2
High Impedance
SO
1-2. High-speed Read command
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8
dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55
SCK
SI
Mode0
8CLK
0Bh
Add.
Add.
Add.
X
MSB
N
N+1
N+2
High Impedance
SO
DATA DATA DATA
MSB
MSB
MSB
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
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LE25S40FD
2. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table
4 Status registers" gives the significance of each bit.
Table 4 Status Registers
Bit
Name
Logic
Function
Ready
Power-on Time Information
0
0
1
0
1
0
1
0
1
0
1
0
1
RDY
Bit0
Erase/Program
Write disabled
Write enabled
Bit1
Bit2
Bit3
Bit4
WEN
BP0
BP1
BP2
TB
0
Nonvolatile information
Nonvolatile information
Nonvolatile information
Block protect information
Protecting area switch
Block protect
Bit5
Bit6
Bit7
Nonvolatile information
Upper side/Lower side switch
Reserved bits
0
0
1
Status register write enabled
Status register write disabled
SRWP
Nonvolatile information
2-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be
executed even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 5 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the
first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence,
synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is
output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock
input is continued. The data can be read by the status register read command at any time (even during a program or
erase cycle).
Figure 5 Status Register Read
CS
Mode 3
0
1
2
3
4
5
6
7
8
15 16
23
SCK
Mode 0
8CLK
05h
SI
MSB
High Impedance
SO
DATA DATA DATA
MSB MSB MSB
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LE25S40FD
2-2. Status register write
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write
command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2,
TB and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained
even at power-down. "Figure 6 Status Register Write" shows the timing waveforms of status register write, and
Figure 19 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register
write command initiates the internal write operation at the rising CS edge after the data has been input following
(01h). Erase and program are performed automatically inside the device by status register write so that erasing or
other processing is unnecessary before executing the command. By the operation of this command, the information
in bits BP0, BP1, BP2, TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status
register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the
status register. Status register write ends can be detected by RDY of status register read. To initiate status register
write, the logic level of the WP pin must be set high and status register WEN must be set to "1".
Figure 6 Status Register Write
Self-timed
Write Cycle
t
SRW
CS
WP
SCK
SI
t
t
WPH
WPS
Mode3
Mode0
0
1
2
3
4
5
6
7
8
15
8CLK
01h
DATA
MSB
High Impedance
SO
2-3. Contents of each status register
RDY (Bit 0)
The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is
in a busy state, and when it is "0", it means that write is completed.
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will
not perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following
states, WEN is automatically set to "0" in order to protect against unintentional writing.
At power-on
Upon completion of small sector erase, sector erase or chip erase
Upon completion of page program
Upon completion of status register write
* If a write operation has not been performed inside the LE25S40FD because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior
to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
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LE25S40FD
BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)
Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be
protected can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting
conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order
address area or lower-order address area.
Table 5 Protect Level Setting Conditions
Status Register Bits
Protect Level
Protected Area
TB
X
0
BP2
0
BP1
0
BP0
0
0 (Whole area unprotected)
T1 (Upper side 1/8 protected)
T2 (Upper side 1/4 protected)
T3 (Upper side 1/2 protected)
B1 (Lower side 1/8 protected)
B2 (Lower side 1/4 protected)
B3 (Lower side 1/2 protected)
4 (Whole area protected)
None
0
0
1
07FFFFh to 070000h
07FFFFh to 060000h
07FFFFh to 040000h
00FFFFh to 000000h
01FFFFh to 000000h
03FFFFh to 000000h
07FFFFh to 000000h
0
0
1
0
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
X
1
X
X
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status
registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP
setting conditions".
Table 6 SRWP Setting Conditions
WP
Pin
SRWP
Status Register Protect State
Unprotected
0
1
0
1
0
Protected
Unprotected
1
Unprotected
Bit 6 are reserved bits, and have no significance.
3. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation
is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 7 Write Enable" shows the timing waveforms when the write enable operation is performed. The write
enable command consists only of the first bus cycle, and it is initiated by inputting (06h).
Small sector erase, sector erase, chip erase
Page program
Status register write
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LE25S40FD
4. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 8 Write
Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is
initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write
enable command (06h).
Figure 7 Write Enable
Figure 8 Write Disable
CS
SCK
SI
CS
SCK
SI
Mode3
Mode0
Mode3
Mode0
0
1
2
3
4
5
6
7
0
1 2 3
4 5 6 7
8CLK
06h
8CLK
04h
MSB
MSB
High Impedance
High Impedance
SO
SO
5. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 9 Power-down"
shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by
inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The
power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or
more of the silicon ID read command (ABh) has been input). "Figure 10 Exiting from Power-down" shows the
timing waveforms of the power-down exit command.
Figure 9 Power-down
Figure 10 Exiting from Power-down
Power down
mode
Power down
mode
CS
SCK
SI
CS
SCK
SI
t
PRB
t
DP
Mode3
Mode0
Mode3
Mode0
0
1
2
3
4
5
6
7
0
1 2 3
4 5 6 7
8CLK
B9h
8CLK
ABh
MSB
MSB
High Impedance
High Impedance
SO
SO
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LE25S40FD
6. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes. "Figure 11 Small Sector Erase" shows the timing waveforms, and Figure 20 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by
inputting the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19
are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it
ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register
RDY.
Figure 11 Small Sector Erase
Self-timed
Erase Cycle
t
SSE
CS
SCK
SI
Mode3
Mode0
0
1
2
3
4
5
6
7
8
15 16
23 24
31
8CLK
20h / D7h
Add.
Add.
Add.
MSB
High Impedance
SO
7. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes.
"Figure 12 Sector Erase" shows the timing waveforms, and Figure 20 shows a sector erase flowchart. The sector
erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses
following (D8h). Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command
has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control
exercised by the internal timer. Erase end can also be detected using status register RDY.
Figure 12 Sector Erase
Self-timed
Erase Cycle
t
SE
CS
SCK
SI
Mode3
Mode0
0
1
2
3
4
5
6
7
8
15 16
23 24
31
8CLK
D8h
Add.
Add.
Add.
MSB
High Impedance
SO
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LE25S40FD
8. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 13 Chip Erase" shows the
timing waveforms, and Figure 20 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase
operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer.
Erase end can also be detected using status register RDY.
Figure 13 Chip Erase
Self-timed
Erase Cycle
t
CHE
CS
Mode3
Mode0
0
1 2 3
4 5 6 7
SCK
8CLK
60h / C7h
SI
MSB
High Impedance
SO
9. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 14 Page Program" shows the page program timing waveforms,
and Figure 21 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by
the 24-bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until
the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes,
the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS edge occurring at any other timing.
Figure 14 Page Program
Self-timed
Program Cycle
t
PP
CS
Mode3
Mode0
2079
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SCK
8CLK
02h
SI
Add.
Add.
Add.
PD
PD
PD
MSB
High Impedance
SO
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LE25S40FD
10. Silicon ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is
not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID.
In the first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the
subsequent bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory
type, memory capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as
clock inputs are present, "Table 7-1 JEDEC ID code " lists the silicon ID codes and "Figure 15-a JEDEC ID read"
shows the JEDEC ID read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID code " lists
the silicon ID codes and "Figure 15-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence
is finished by setting CS high.
Table 7-1 JEDEC ID code
Table 7-2 ID code
Output code
62h
Output Code
Manufacturer code
3E
1 byte device ID
(LE25S40FD)
16h
Memory type
2 byte device ID
13h(4M Bit)
00h
Memory capacity code
Device code
1
Figure 15-a JEDEC ID Read
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
SCK
SI
Mode0
8CL
9Fh
High Impedance
SO
00h
MSB
62h
MSB
62h
16h
MSB
13h
MSB
MSB
Figure 15-b ID Read
CS
Mode3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
SCK
Mode0
8CL
ABh
SI
X
X
X
High Impedance
SO
3Eh
MSB
3Eh
MSB
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13
LE25S40FD
11. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure16
HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is
high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-
impedance state, and SI and SCK are "don't care".
Figure 16 HOLD
Active
HOLD
Active
CS
t
t
HS
HS
SCK
t
t
HH
HH
HOLD
t
t
HLZ
HHZ
High Impedance
SO
12. Power-on
In order to protect against unintentional writing, CS must be within at V -0.3 to V +0.3 on power-on. After
DD
DD
power-on, the supply voltage has stabilized at VDD min. or higher, waits for t
before inputting the command to
PU
start a device operation. The device is in the standby state and not in the power-down state after power is turned on.
To put the device into the power-down state, it is necessary to enter a power-down command.
Figure 17 Power-on Timing
CS
= V
level
DD
Full Access Allowed
V
DD
V
V
(Max)
(Min)
DD
DD
t
PU
0V
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14
LE25S40FD
13. Hardware Data Protection
LE25S40FD incorporates a power-on reset function. The following conditions must be met in order to ensure that
the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 18 Power-down Timing
V
DD
V
V
(Max)
DD
DD
(Min)
t
PD
0V
vBOT
Power-on timing
spec
Parameter
Symbol
unit
min
100
10
max
0.2
power-on to operation time
power-down time
t
µs
ms
V
PU
t
t
PD
power-down voltage
BOT
14. Software Data Protection
The LE25S40FD eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1F ceramic capacitor must be provided to each device and connected between V
ensure that the device will operate stably.
and V in order to
SS
DD
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15
LE25S40FD
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Ratings
-0.5 to +2.4
unit
V
Maximum supply voltage
DC voltage (all pins)
Storage temperature
VDDmax
With respect to V
SS
VIN/VOUT
Tstg
With respect to V
-0.5 to V +0.5
DD
V
SS
-55 to +150
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Operating Conditions
Parameter
Symbol
VDD
Topr
Conditions
Ratings
1.65 to 1.95
-40 to +85
unit
V
Operating supply voltage
Operating ambient temperature
C
Allowable DC Operating Conditions
Ratings
typ
Parameter
Symbol
Conditions
unit
mA
min
max
Read mode operating current
I
SCK=0.1V /0.9V
DD
,
CCR
DD
,
=
=0.9V
6
8
HOLD WP
DD
SO=open,25MHz
SCK=0.1V /0.9V
DD
,
DD
,
=
=0.9V
mA
HOLD WP
DD
SO=open,40MHz
Write mode operating current
(erase+page program)
I
I
I
t
= t = t
=typ.,t =max
PP
CCW
SSE SE CHE
15
50
10
mA
A
A
CMOS standby current
=V
,
=
=V
,
CS
HOLD WP
SB
DD
DD
SO=open,
SI=V /V
SS DD,
=V
CS
Power-down standby current
,
=
=V
,
HOLD WP
DSB
DD
DD
SO=open,
SI=V /V
SS DD,
Input leakage current
Output leakage current
Input low voltage
I
I
2
2
A
A
V
LI
LO
V
V
V
-0.3
0.7V
0.3V
DD
IL
Input high voltage
Output low voltage
V
+0.3
V
IH
OL
DD
DD
I
I
I
=100A, V =V
DD DD
min
min
0.2
OL
OL
OH
V
V
=1.6mA, V =V
0.4
DD DD
Output high voltage
V
=-100A, V =V
min
V
-0.2
OH
DD DD
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Data hold, Rewriting frequency
Parameter
condition
Program/Erase
Status resister write
min
100,000
max
unit
times/
Sector
Rewriting frequency
Data hold
1,000
20
year
Pin Capacitance at Ta=25C, f=1MHz
Ratings
max
Parameter
Symbol
Conditions
unit
Output pin capacitance
Input pin Capacitance
C
C
V
=0V
SO
12
6
pF
pF
SO
V =0V
IN
IN
Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values
for some of the sampled devices.
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16
LE25S40FD
AC Characteristics
Ratings
typ
Parameter
Symbol
unit
min
max
Read instruction(03h)
25
40
MHz
MHz
V/ns
Clock frequency
f
CLK
All instructions except for read(03h)
Input signal rising/falling time
t
0.1
RF
SCK logic high level pulse width
25MHz
40MHz
25MHz
40MHz
t
14
11.5
14
CLHI
ns
ns
SCK logic low level pulse width
t
CLLO
11.5
10
CS
CS
setup time
hold time
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
ms
ms
ms
CSS
t
10
5
CSH
Data setup time
Data hold time
t
DS
t
5
DH
CS
wait pulse width
t
25
CPH
CS
Output high impedance time from
Output data time from SCK
Output data hold time
t
15
11
CHZ
t
8
V
t
1
0
HO
Output low impedance time from SCK
t
CLZ
WP
WP
setup time
hold time
t
20
20
5
WPS
t
WPH
HOLD
HOLD
setup time
hold time
t
HS
t
5
HH
HOLD
HOLD
Output low impedance time from
Output high impedance time from
Power-down time
t
12
9
HLZ
t
HHZ
t
t
t
5
DP
Power-down recovery time
Write status register time
5
PRB
SRW
8
6
10
8
256Byte
nByte
Page programming cycle time
t
0.15+
n*5.85/256
0.04
0.20+
n*7.80/256
0.15
PP
Small sector erase cycle time
Sector erase cycle time
Chip erase cycle time
t
t
t
s
s
s
SSE
0.08
0.3
0.25
3.0
SE
CHE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
AC Test Conditions
Input pulse level··········· 0.2V
Input rising/falling time ·· 5ns
to 0.8V
DD
DD
Input timing level ········· 0.3V , 0.7V
DD DD
Output timing level ······· 1/2V
Output load ················ 15pF
DD
Note: As the test conditions for "typ", the measurements are conducted using 1.8V for V
DD
at room temperature.
input / output timing level
0.7V
input level
0.8V
DD
DD
DD
DD
DD
1/2V
0.3V
0.2V
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17
LE25S40FD
Timing waveforms
Serial Input Timing
t
CPH
CS
t
t
t
t
t
t
CSS
CSH
CSS
CLHI
CLLO CSH
SCK
t
t
DH
DS
SI
DATA VALID
High Impedance
High Impedance
SO
Serial Output Timing
CS
SCK
SO
t
t
t
CHZ
CLZ
HO
DATA VALID
t
V
SI
Hold Timing
CS
t
t
t
t
HS
HH
HS
HH
SCK
HOLD
SI
t
t
HLZ
HHZ
High Impedance
Status register write Timing
CS
t
t
WPH
WPS
WP
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18
LE25S40FD
Figure 19 Status Register Write Flowchart
Status register write
Start
06h
Write enable
01h
Set status register write
command
Data
status register write start
on rising edge of CS
Set status register read
command
05h
NO
Bit 0= “0” ?
YES
End of status register
write
* Automatically placed in write disabled state
at the end of the status register write
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19
LE25S40FD
Figure 20 Erase Flowcharts
Sector erase
Start
Small sector erase
Start
Write enable
06h
Write enable
06h
D8h
20h / D7h
Address 1
Address 2
Address 3
Set sector erase
command
Address 1
Address 2
Address 3
Set small sector erase
command
Start erase on rising
edge of CS
Start erase on rising
edge of CS
Set status register read
command
Set status register read
command
05h
05h
NO
Bit 0 = “0” ?
YES
NO
Bit 0 = “0” ?
YES
End of erase
End of erase
* Automatically placed in write disabled
state at the end of the erase
* Automatically placed in write disabled
state at the end of the erase
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20
LE25S40FD
Figure 21 Page Program Flowchart
Page program
Start
Chip erase
Start
06h
Write enable
Write enable
06h
02h
Set chip erase
command
60h / C7h
Set page program
command
Address 1
Address 2
Address 3
Data 0
Start erase on rising edge
of CS
Set status register read
command
05h
Bit 0 = “0” ?
YES
Data n
Start program on rising
edge of CS
NO
End of erase
Set status register read
command
* Automatically placed in write disabled state at
the end of the erase
05h
NO
Bit 0= “0” ?
YES
End of
programming
* Automatically placed in write disabled state at
the end of the programming operation.
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21
LE25S40FD
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
3000 / Tape & Reel
VSOIC8 NB
(Pb-Free / Halogen Free)
LE25S40FD-AH
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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22
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