LE25U40CMC-AH_技术文档

LE25U40CMC

CMOS LSI

Serial Flash Memory, 4 Mb (512K8)

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Overview

The LE25U40CMC is a SPI bus flash memory device with a 4M bit (512K

 8-bit) configuration that adds a high performance Dual output and Dual

I/O function. It uses a single 2.5v power supply. While making the most of

the features inherent to a serial flash memory device, the LE25U40CMC is

housed in an 8-pin ultra-miniature package. All these features make this

device ideally suited to storing program in applications such as portable

information devices, which are required to have increasingly more compact

dimensions. The LE25U40CMC also has a small sector erase capability

which makes the device ideal for storing parameters or data that have fewer

rewrite cycles and conventional EEPROMs cannot handle due to

insufficient capacity.

SOIC-8 / SOP8J (200mil)

Features

 Read/write operations enabled by single 2.5v power supply: 2.3 to 3.6V supply voltage range

 Operating frequency

 Temperature range

 Serial interface

 Sector size

: 40MHz

: 40 to 85C

: SPI mode 0, mode 3 supported / Dual Output, Dual I/O supported

: 4K bytes/small sector, 64K bytes/sector

 Small sector erase, sector erase, chip erase functions

 Page program function (256 bytes / page)

 Block protect function

 Highly reliable read/write

Number of rewrite times: 100,000 times

Small sector erase time : 40ms (typ.), 150ms (max.)

Sector erase time

Chip erase time

: 80ms (typ.), 250ms (max.)

: 250ms (typ.), 2.0s (max.)

Page program time

 Status functions

 Data retention period

 Package

: 4.0ms/256 bytes (typ.), 5.0ms/256 bytes (max.)

: Ready/busy information, protect information

: 20 years

: SOP8J (200mil)

* This product is licensed from Silicon Storage Technology, Inc. (USA).

ORDERING INFORMATION

See detailed ordering and shipping information on page 24 of this data sheet.

February 2016 - Rev. 1

1

Publication Order Number :

LE25U40CMC/D

LE25U40CMC

Package Dimensions

unit : mm

SOIC-8 / SOP8J (200 mil)

CASE 751CU

ISSUE O

Figure 1 Pin Assignments

CS

1

2

3

4

8

7

6

5

V

DD

HOLD

SCK

SO/SIO1

WP

V

SI/SIO0

SS

Top view

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LE25U40CMC

Figure 2 Block Diagram

4M Bit

X-

Flash EEPROM

Cell Array

DECODER

ADDRESS

BUFFERS

&

LATCHES

Y-DECODER

I/O BUFFERS

&

DATA LATCHES

CONTROL

LOGIC

SERIAL INTERFACE

CS

SI/SIO0

SO/SIO1 WP

HOLD

SCK

Table 1 Pin Description

Symbol

SCK

Pin Name

Serial clock

Description

This pin controls the data input/output timing.

The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is

output synchronized to the falling edge of the serial clock.

SI/SIO0

Serial data input

The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the

serial clock. It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.

The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.

It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.

The device becomes active when the logic level of this pin is low; it is deselected and placed in standby

status when the logic level of the pin is high.

/ Serial data input output

Serial data input

SO/SIO1

CS

/ Serial data input output

Chip select

WP

Write protect

Hold

The status register write protect (SRWP) takes effect when the logic level of this pin is low.

HOLD

Serial communication is suspended when the logic level of this pin is low.

This pin supplies the 2.3 to 3.6V supply voltage.

V

Power supply

Ground

DD

V

This pin supplies the 0V supply voltage.

SS

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LE25U40CMC

Device Operation

The read, erase, program and other required functions of the device are executed through the command registers.

The serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the

device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit

units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to

execute operation according to the command that is input.

The LE25U40CMC supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0

is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level

of SCK is high.

Figure 3 I/O waveforms

CS

Mode3

SCK

Mode0

8CLK

SI

Nth bus

1st bus

2nd bus

LSB

(Bit0)

MSB

(Bit7)

High Impedance

DATA

SO

Table 2 Command Settings

Command

1st bus cycle

2nd bus cycle

A23-A16

A23-A8

3rd bus cycle

4th bus cycle

A7-A0

5th bus cycle

6th bus cycle

RD *1

Nth bus cycle

RD *1

Read

03h

0Bh

A15-A8

RD *1

X

High Speed Read

Dual Read

A7-A0

RD *1

3Bh

A15-A8

A7-A0

Z

RD *1

Dual I/O Read

Small sector erase

Sector erase

BBh

A7-A0,X, Z

A15-A8

RD *1

20h / D7h

D8h

A23-A16

A7-A0

A15-A8

A7-A0

Chip erase

60h / C7h

02h

Page program

Write enable

A23-A16

A15-A8

A7-A0

PD *2

06h

Write disable

04h

Power down

B9h

Status register read

Status register write

JEDEC ID read

ID read

05h

01h

DATA

X

9Fh

ABh

X

power down

B9h

Exit power down mode

ABh

Explanatory notes for Table 2

"X" signifies "don't care" (that is to say, any value may be input)., "Z” signifies " High Impedance ".

The "h" following each code indicates that the number given is in hexadecimal notation.

Addresses A23 to A19 for all commands are "Don't care".

*1: "RD" stands for read data. *2: "PD" stands for page program data.

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LE25U40CMC

Table 3 Command Settings

4M Bit

sector(64KB)

small sector

address space(A23 to A0)

127

to

112

111

to

96

95

to

80

79

to

64

63

to

48

47

to

32

31

to

07F000h

07FFFFh

7

6

5

4

3

2

1

070000h

06F000h

070FFFh

06FFFFh

060000h

05F000h

060FFFh

05FFFFh

050000h

04F000h

050FFFh

04FFFFh

040000h

03F000h

040FFFh

03FFFFh

030000h

02F000h

030FFFh

02FFFFh

020000h

01F000h

020FFFh

01FFFFh

16

15

to

010000h

00F000h

010FFFh

00FFFFh

0

2

1

0

002000h

001000h

000000h

002FFFh

001FFFh

000FFFh

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LE25U40CMC

Description of Commands and Their Operations

A detailed description of the functions and operations corresponding to each command is presented below.

1. Standard SPI read

There are two read commands, the standard SPI read command and High-speed read command.

1-1. Read command

Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following

(03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 4-a Read"

shows the timing waveforms.

Figure 4-a Read

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

SCK

SI

Mode0

8CLK

03h

Add.

N

N+1

DATA DATA DATA

MSB MSB MSB

N+2

High Impedance

SO

1-2. High-speed Read command

Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8 dummy

bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.

"Figure 4-b High-speed Read" shows the timing waveforms.

Figure 4-b High-speed Read

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47 48

55

SCK

SI

Mode0

8CLK

0Bh

Add.

X

MSB

N

N+1

N+2

High Impedance

SO

DATA DATA DATA

MSB

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LE25U40CMC

2. Dual read

There are two Dual read commands, the Dual read command and the Dual I/O read command. They achieve the twice

speed-up from a High-speed read command.

2-1. Dual Read command

The Dual read command changes SI/SIO0 into the output pin function in addition to SO/SIO1, makes the data output x2

bit and has achieved a high-speed output. Consisting of the first through fifth bus cycles, the Dual read command inputs

the 24-bit addresses and 8 dummy bits following (3Bh). DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0 and

DATA0 (Bit6, Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of fifth bus cycle bit 0 as a

reference. "Figure 5-a Dual Read" shows the timing waveforms.

Figure 5-a Dual Read

CS

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

43 44

47

Mode3

Mode0

SCK

8CL

3Bh

N

N+1

N+2

dummy

bit

DATA0

b6,b4,b2,b0

Add.

DATA0 DATA0 DATA0

SI/SIO0

MSB

4CL

DATA1 DATA1 DATA1

MSB MSB

4CL

High Impedance

DATA1

b7,b5,b3,b1

SO/SIO1

MSB

2-2. Dual I/O Read command

The Dual I/O read command changes SI/SIO0 and SO/SIO1 into the input output pin function, makes the data input and

output x2 bit and has achieved a high-speed output. Consisting of the first through third bus cycles, the Dual I/O read

command inputs the 24-bit addresses and 4 dummy clocks following (BBh). The format of the address input and the

dummy bit input is the x2 bit input. Add1 (A23, A21, -, A3 and A1) is input from S0/SIO1 and Add0 (A22, A20, -, A2

and A0) is input from SI/SIO0. 2CLK of the latter half of the dummy clock is in the state of high impedance, the

controller can switch I/O for this period. DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0 and DATA0 (Bit6,

Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of third bus cycle bit 0 as a reference. "Figure 5-b

Dual I/O Read" shows the timing waveforms.

Figure 5-b Dual I/O Read

CS

0

1

2

3

4

5

6

7

8

22 23 24

27 28

31

20 21

19

Mode3

Mode0

SCK

dummy

bit

8CL

BBh

N

N+1

N+2

DATA0

b6,b4,b2,b0

Add1:A22,A20-A2,A0

X

DATA0 DATA0 DATA0

SI/SIO0

MSB

4CLK

12CLK

2CLK

X

High Impedance

DATA1

b7,b5,b3,b1

SO/SIO1

DATA1 DATA1 DATA1

Add2:A23,A21-A3,A1

MSB

When SCK is input continuously after the read command has been input and the data in the designated addresses has

been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding

data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address

(7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic

level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO

is in a high-impedance state.

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LE25U40CMC

3. Status Registers

The status registers hold the operating and setting statuses inside the device, and this information can be read (status

register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 4

Status registers" gives the significance of each bit.

Table 4 Status Registers

Bit

Name

Logic

Function

Ready

Power-on Time Information

0

1

0

1

0

1

0

1

0

1

0

1

RDY

Bit0

Erase/Program

Write disabled

Write enabled

Bit1

Bit2

Bit3

Bit4

WEN

BP0

BP1

BP2

TB

0

Nonvolatile information

Block protect information

Protecting area switch

Block protect

Bit5

Bit6

Bit7

Nonvolatile information

Upper side/Lower side switch

Reserved bits

0

1

Status register write enabled

Status register write disabled

SRWP

Nonvolatile information

3-1. Status register read

The contents of the status registers can be read using the status register read command. This command can be executed

even during the following operations.

 Small sector erase, sector erase, chip erase

 Page program

 Status register write

"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus

cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the

clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first

to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized

to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by

returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is

continued. The data can be read by the status register read command at any time (even during a program or erase cycle).

Figure 6 Status Register Read

CS

Mode 3

0

1

2

3

4

5

6

7

8

15 16

23

SCK

SI

Mode 0

8CLK

05h

MSB

High Impedance

SO

DATA DATA DATA

MSB MSB MSB

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LE25U40CMC

3-2. Status register write

The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write

command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB

and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at

power-down. "Figure 6 Status Register Write" shows the timing waveforms of status register write, and Figure 20

shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command

initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and

program are performed automatically inside the device by status register write so that erasing or other processing is

unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, BP2,

TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status register cannot be written,

no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register

write ends can be detected by RDY of status register read. To initiate status register write, the logic level of the WP pin

must be set high and status register WEN must be set to "1".

Figure 6 Status Register Write

Self-timed

Write Cycle

t

SRW

CS

WP

SCK

SI

t

WPH

WPS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15

8CLK

01h

DATA

MSB

High Impedance

SO

3-3. Contents of each status register

RDY (Bit 0)

The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is

in a busy state, and when it is "0", it means that write is completed.

WEN (bit 1)

The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not

perform the write operation even if the write command is input. If it is set to "1", the device can perform write

operations in any area that is not block-protected.

WEN can be controlled using the write enable and write disable commands. By inputting the write enable command

(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states,

WEN is automatically set to "0" in order to protect against unintentional writing.

 At power-on

 Upon completion of small sector erase, sector erase or chip erase

 Upon completion of page program

 Upon completion of status register write

* If a write operation has not been performed inside the LE25U40CMC because, for instance, the command input for

any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has

failed or a write operation has been performed for a protected address, WEN will retain the status established prior to

the issue of the command concerned. Furthermore, its state will not be changed by a read operation.

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LE25U40CMC

BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)

Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected

can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions".

BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order

address area or lower-order address area.

Table 5 Protect Level Setting Conditions

Status Register Bits

Protect Level

Protected Area

TB

X

0

BP2

0

BP1

0

BP0

0

0 (Whole area unprotected)

T1 (Upper side 1/8 protected)

T2 (Upper side 1/4 protected)

T3 (Upper side 1/2 protected)

B1 (Lower side 1/8 protected)

B2 (Lower side 1/4 protected)

B3 (Lower side 1/2 protected)

4 (Whole area protected)

None

0

1

07FFFFh to 070000h

07FFFFh to 060000h

07FFFFh to 040000h

00FFFFh to 000000h

01FFFFh to 000000h

03FFFFh to 000000h

07FFFFh to 000000h

0

1

0

1

0

1

0

1

X

1

X

* Chip erase is enabled only when the protect level is 0.

SRWP (bit 7)

Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.

When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status

registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers

are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP setting

conditions".

Table 6 SRWP Setting Conditions

WP

SRWP

Status Register Protect State

Unprotected

0

1

0

1

0

Protected

Unprotected

1

Unprotected

Bit 6 are reserved bits, and have no significance.

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LE25U40CMC

4. Write Enable

Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is

the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.

"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable

command consists only of the first bus cycle, and it is initiated by inputting (06h).

 Small sector erase, sector erase, chip erase

 Page program

 Status register write

5. Write Disable

The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable"

shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by

inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command

(06h).

Figure 8 Write Enable

Figure 9 Write Disable

CS

SCK

SI

CS

SCK

SI

Mode3

Mode0

Mode3

Mode0

0

1

2

3

4

5

6

7

0

1 2 3

4 5 6 7

8CLK

06h

8CLK

04h

MSB

High Impedance

SO

6. Power-down

The power-down command sets all the commands, with the exception of the silicon ID read command and the

command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows

the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting

(B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down

state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the

silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of

the power-down exit command.

Figure 10 Power-down

Figure 11 Exiting from Power-down

Power down

mode

Power down

mode

CS

SCK

SI

CS

SCK

SI

t

PDR

t

DP

Mode3

Mode0

Mode3

Mode0

0

1

2

3

4

5

6

7

0

1 2 3 4 5 6 7

8CLK

B9h

8CLK

ABh

MSB

High Impedance

SO

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LE25U40CMC

7. Small Sector Erase

Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of

4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase

flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting

the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19 are "don't

care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends

automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY.

Figure 12 Small Sector Erase

Self-timed

Erase Cycle

t

SSE

CS

SCK

SI

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31

8CLK

20h / D7h

Add.

MSB

High Impedance

SO

8. Sector Erase

Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure

13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command

consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h).

Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the

internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal

timer. Erase end can also be detected using status register RDY.

Figure 13 Sector Erase

Self-timed

Erase Cycle

t

SE

CS

SCK

SI

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31

8CLK

D8h

Add.

MSB

High Impedance

SO

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LE25U40CMC

9. Chip Erase

Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the

timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus

cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase operation

starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can

also be detected using status register RDY.

Figure 14 Chip Erase

Self-timed

Erase Cycle

t

CHE

CS

Mode3

Mode0

0

1 2 3

4 5 6 7

SCK

8CLK

60h / C7h

SI

MSB

High Impedance

SO

10. Page Program

Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page

addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using small

sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and

Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the 24-

bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until the rising

CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the 256

bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program operation is

not performed at the rising CS edge occurring at any other timing.

Figure 15 Page Program

Self-timed

Program Cycle

t

PP

CS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

2079

SCK

8CLK

02h

SI

Add.

PD

MSB

High Impedance

SO

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LE25U40CMC

11. Silicon ID Read

ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is not

accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID. In the

first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the subsequent

bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory type, memory

capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as clock inputs are

present, "Table 7-1 JEDEC ID code " lists the silicon ID codes and "Figure 16-a JEDEC ID read" shows the JEDEC ID

read timing waveforms.

The second method involves inputting the ID read command. This command consists of the first through fourth bus

cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID code " lists the

silicon ID codes and "Figure 16-b ID read" shows the ID read timing waveforms.

If the SCK input persists after a device code is read, that device code continues to be output. The data output is

transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence is

finished by setting CS high.

Table 7-1 JEDEC ID code

Table 7-2 ID code

Output code

62h

Output Code

Manufacturer code

6E

1 byte device ID

(LE25U40CMC)

06h

Memory type

2 byte device ID

13h(4M Bit)

00h

Memory capacity code

Device code

1

Figure 16-a JEDEC ID Read

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39

SCK

SI

Mode0

8CL

9Fh

High Impedance

SO

00h

MSB

62h

MSB

62h

06h

MSB

13h

MSB

Figure 16-b ID Read

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39

SCK

Mode0

8CL

ABh

SI

X

High Impedance

SO

6Eh

MSB

6Eh

MSB

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14

LE25U40CMC

12. Hold Function

Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure17

HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic

level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high,

HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited

and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state,

and SI and SCK are "don't care".

Figure 17 HOLD

Active

HOLD

Active

CS

t

HS

SCK

t

HH

HOLD

t

HLZ

HHZ

High Impedance

SO

13. Power-on

In order to protect against unintentional writing, CS must be within at V -0.3 to V +0.3 on power-on. After power-

DD

on, the supply voltage has stabilized at VDD min. or higher, waits for t

DD

before inputting the command to start a

PU

device operation. The device is in the standby state and not in the power-down state after power is turned on. To put the

device into the power-down state, it is necessary to enter a power-down command.

Figure 18 Power-on Timing

CS

= V

level

DD

Full Access Allowed

V

DD

V

(Max)

(Min)

DD

t

PU

0V

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15

LE25U40CMC

14. Hardware Data Protection

LE25U40CMC incorporates a power-on reset function. The following conditions must be met in order to ensure that

the power reset circuit will operate stably.

No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.

Figure 19 Power-down Timing

V

DD

V

(Max)

DD

(Min)

t

PD

0V

vBOT

Power-on timing

spec

Parameter

Symbol

unit

min

100

10

max

0.2

power-on to operation time

power-down time

t

µs

ms

V

PU

t

PD

power-down voltage

BOT

14. Software Data Protection

The LE25U40CMC eliminates the possibility of unintentional operations by not recognizing commands under the

following conditions.

 When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)

 When the page program data is not in 1-byte increments

 When the status register write command is input for 2 bus cycles or more

15. Decoupling Capacitor

A 0.1F ceramic capacitor must be provided to each device and connected between V

that the device will operate stably.

and V in order to ensure

SS

DD

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16

LE25U40CMC

Specifications

Absolute Maximum Ratings

Parameter

Symbol

max

Conditions

Ratings

0.5 to +4.6

unit

V

Maximum supply voltage

DC voltage (all pins)

Storage temperature

V

With respect to V

DD

SS

VIN/VOUT

Tstg

With respect to V

0.5 to V +0.5

V

SS

DD

55 to +150

C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,

damage may occur and reliability may be affected.

Operating Conditions

Parameter

Symbol

Conditions

Ratings

2.3 to 3.6

unit

V

Operating supply voltage

Operating ambient temperature

V

DD

Topr

40 to 85

C

Allowable DC Operating Conditions

Ratings

typ

Parameter

Symbol

Conditions

unit

min

max

Read mode operating current

I

SCK=0.1V /0.9V

DD

,

CCR

DD

,

25MHz

6

10

12

15

mA

=

=0.9V

HOLD WP

Single

Dual

DD

40MHz

Output = open

mA

Write mode operating current

(erase + page program)

CMOS standby current

I

t

= t = t

=typ.,t =max

PP

CCW

SSE SE CHE

SB

=V

,

=

=V

,

CS

HOLD WP

DD

SO=open,

50

10

A

SI=V /V

SS DD,

Power-down standby current

I

DSB

=V

CS

,

=

=V

,

HOLD WP

DD

SO=open,

SI=V /V

SS DD,

Input leakage current

Output leakage current

Input low voltage

I

LI

2

A

V

LO

V

IL

0.3V

0.3

0.7V

DD

Input high voltage

Output low voltage

IH

OL

V

+0.3

V

DD

I

=100A, V =V

DD DD

min

OL

OH

0.2

0.4

V

=1.6mA, V =V

DD DD

Output high voltage

V

=100A, V =V

min

OH

V

0.2

DD DD

DD

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended

Operating Ranges limits may affect device reliability.

Data hold, Rewriting frequency

Parameter

condition

min

max

unit

times/ Sector

times

Program/Erase

Status resister write

100,000

1,000

20

Rewriting frequency

Data hold

year

Pin Capacitance at Ta=25C, f=1MHz

Ratings

max

Parameter

Symbol

Conditions

unit

Output pin capacitance

Input pin Capacitance

C

V

=0V

SO

12

6

pF

SO

V =0V

IN

Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values

for some of the sampled devices.

www.onsemi.com

17

LE25U40CMC

AC Characteristics

Ratings

typ

Parameter

Symbol

unit

min

max

Read instruction(03h)

25

40

MHz

V/ns

Clock frequency

f

CLK

All instructions except for read(03h)

Input signal rising/falling time

t

0.1

RF

25MHz

40MHz

25MHz

40MHz

16

11.5

16

ns

SCK logic high level pulse width

t

CLHI

SCK logic low level pulse width

t

CLLO

11.5

8

CS

setup time

hold time

t

CSS

t

8

2

ns

s

ms

s

CSH

Data setup time

Data hold time

t

DS

t

5

DH

CS

wait pulse width

t

25

CPH

CS

Output high impedance time from

Output data time from SCK

Output data hold time

t

8

CHZ

t

8

11

V

t

1

0

5

3

HO

Output low impedance time from SCK

t

CLZ

HOLD

setup time

hold time

t

HS

t

HH

HOLD

Output low impedance time from

t

9

HLZ

Output high impedance time from

t

HHZ

WP

setup time

hold time

t

20

WPS

t

WPH

Power-down time

t

3

DP

Power-down recovery time

Write status register time

PDR

SRW

5

4

15

5

Page programming cycle time

Small sector erase cycle time

Sector erase cycle time

t

PP

40

80

150

250

2.0

SSE

SE

Chip erase cycle time

t

0.25

CHE

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.

AC Test Condtions

Input pulse level··········· 0.2V

Input rising/falling time ·· 5ns

to 0.8V

DD

Input timing level ········· 0.3V , 0.7V

DD DD

Output timing level ······· 1/2V

Output load ················ 30pF

DD

Note: As the test conditions for "typ", the measurements are conducted using 2.5v for V

DD

at room temperature.

input / output timing level

0.7V

input level

0.8V

DD

1/2V

0.3V

0.2V

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18

LE25U40CMC

Timing waveforms

Serial Input Timing

t

CPH

CS

t

CSS

CSH

CSS

CLHI

CLLO CSH

SCK

t

DH

DS

SI

DATA VALID

High Impedance

SO

Serial Output Timing

CS

SCK

SO

t

CHZ

CLZ

HO

DATA VALID

t

V

SI

Hold Timing

CS

t

HS

t

HS

HH

SCK

HOLD

SI

t

HLZ

HHZ

High Impedance

Status resistor write Timing

CS

t

WPH

WPS

WP

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19

LE25U40CMC

Figure 20 Status Register Write Flowchart

Status register write

Start

06h

Write enable

01h

Set status register write

command

Data

status register write start

on rising edge of CS

Set status register read

command

05h

NO

Bit 0= “0” ?

YES

End of status register

write

* Automatically placed in write disabled state

at the end of the status register write

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20

LE25U40CMC

Figure 21 Erase Flowcharts

Sector erase

Start

Small sector erase

Start

Write enable

06h

Write enable

06h

D8h

20h / D7h

Address 1

Address 2

Address 3

Set sector erase

command

Address 1

Address 2

Address 3

Set small sector erase

command

Start erase on rising

edge of CS

Start erase on rising

edge of CS

Set status register read

command

Set status register read

command

05h

NO

Bit 0 = “0” ?

YES

NO

Bit 0 = “0” ?

YES

End of erase

* Automatically placed in write disabled

state at the end of the erase

* Automatically placed in write disabled

state at the end of the erase

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21

LE25U40CMC

Figure 22 Page Program Flowchart

Page program

Start

Chip erase

Start

06h

Write enable

06h

02h

Set chip erase

command

60h / C7h

Set page program

command

Address 1

Start erase on rising edge

of CS

Address 2

Address 3

Data 0

Set status register read

command

05h

Bit 0 = “0” ?

YES

Data n

Start program on rising

NO

End of erase

CS

edge of

Set status register read

command

* Automatically placed in write disabled state at

the end of the erase

05h

NO

Bit 0= “0” ?

YES

End of

programming

* Automatically placed in write disabled state at

the end of the programming operation.

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22

LE25U40CMC

PART NAME DESCRIPTION for LE25U40C series

LE 25 U 40 C MC XXX - A H - X

Option (For custom usage)

In this case, Distinction of Assembly site

Environment (Legacy rule)

None

E

: Including Pb

: Lead Free

H

: Lead & Halogen Free

Packing (Legacy rule)

: Tape Reel

A

Option (For custom usage)

None : Standard product

Package type

MC

MD

QE

QH

: SOIC8 (SOP8)

: VSON8 6 x 5

: VSON8 4 x 3

Die Generation

None : 1st generation

A

B

C

: 2nd

: 3rd

: 4th

Density

20

40

: 2M-bit

: 4M-bit

80 or 81 : 8M-bit

161 : 16M-bit

Supply voltage

V : 3.0V~3.6V, W : 2.7V~3.6V

U : 2.3V~ ,

S : 1.65V~

Product Family

25 : SPI Serial Flash Memory

26 : Custom specification product

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23

LE25U40CMC

Figure 23 Making Diagrams

25FU406C

00

25FU406C

=Specific Device Code

00

=Blank Data (entire memory cell data are FFh)

Y

M

=Year

=Month

XXX

=Serial Number

YMxxx

ORDERING INFORMATION

Device

Package

Shipping (Qty / Packing)

2000 / Tape & Reel

SOIC-8 / SOP8J (200mil)

(Pb-Free / Halogen Free)

LE25U40CMC-AH

† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel

Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States

and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of

SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without

further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,

nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including

without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can

and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are

not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or

sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was

negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all

applicable copyright laws and is not for resale in any manner.

www.onsemi.com

24


型号：	LE25U40CMC-AH
厂家：	ONSEMI
描述：	串行闪存，4 Mb (512K x 8) 闪存
文件：	总24页 (文件大小：218K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LE25U40CMC-AH [ONSEMI]

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