LE28BW168T-80 [ONSEMI]
Flash Memory,;
| 型号： | LE28BW168T-80 |
| 厂家： | 
ONSEMI |
| 描述： | Flash Memory, |
| 文件： | 总20页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Megabit FlashBank Memory
1
LE28BW168T
FEATURES:
•
Read Access Time
80/90 nsec
Latched Address and Data
•
•
Single 3.0-Volt Read and Write Operations
–
Separate Memory Banks by Address Space
– Simultaneous Read and Write Capability
SuperiorReliability
– Endurance: 10,000 Cycles
– Data Retention: 10 years
•
•
End of Write Detection
– Toggle Bit
– Data # Polling
Flash Bank: Two Small Erase Element Sizes
– 1K Words per Sector or 32K Words per Block
– Erase either element before Word Program
•
•
•
Low Power Consumption
– Active Current, Read:
– Active Current, Read & Write:
– Standby Current:
10 mA (typical)
30 mA (typical)
5µA (typical)
5µA (typical)
•
•
CMOS I/O Compatibility
– Auto Low Power Mode Current:
Packages Available
– 48-Pin TSOP
Continuous Hardware and Software Data
Protection (SDP)
•
•
Fast Write Operation
•
– Bank Erase + Program:
– Block Erase + Program:
– Sector Erase + Program:
8 sec (typical)
500 ms (typical)
30 ms (typical)
Fixed Erase, Program, Write Times
– Does not change after cycling
Product Description
with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated erase/program
cycles.
The LE28BW168T consists of two memory banks, 2 each
512K x 16 bits sector mode flash EEPROM manufactured
with SANYO's proprietary, high performance FlashTechnol-
ogy. The LE28BW168T writes with a 3.0-volt-only power
supply.
Device Operation
The LE28BW168T operates as two independent 8 Megabit
Word Pogram, Sector Erase flash EEPROMs.
The LE28BW168T is divided into two separate memory
banks, 2 each 512K x 16 Flash banks. Each Flash bank is
typically used for program code storage and contains 512
sectors, each of 1K words or 16 blocks, each of 32K words.
The Flash banks may also be used to store data.
All memory banks share common address lines, I/O lines,
WE#, and OE#. Memory bank selection is by bank select
address. WE# is used with SDP to control the Erase and
Program operation in each memory bank.
Any bank may be used for executing code while writing data
to a different bank. Each memory bank is controlled by
separate Bank selection address (A19) lines.
The LE28BW168T provides the added functionality of
being able to simultaneously read from one memory bank
while erasing, or programming to one other memory bank.
Once the internally controlled Erase or Program cycle in a
memory bank has commenced, a different memory bank can
be accessed for read. Also, once WE# and CE# are high
during the SDP load sequence, a different bank may be
accessed to read. LE28BW168T which selectes a bank by
a address. It can be used as a normal conventinal flash
memory when operats erase or program operation to only a
bank at non-concurrent operation.
The LE28BW168T inherently uses less energy during Erase,
and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage range, the
Flash technology uses less current to program and has a
shorter Erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
technologies. The Auto Low Power mode automatically
reduces the active read current to approximately the same as
standby; thus, providing an average read current of approxi-
mately 1 mA/MHz of Read cycle time.
The device ID cannot be accessed while any bank is writing,
erasing, or programming.
The Auto Low Power Mode automatically puts the
LE28BW168T in a near standby mode after data has been
accessed with a valid Read operation. This reduces the IDD
active read current from typically 10mA to typically 5µA.
The Flash technology provides fixed Erase and Program
times, independent of the number of erase/program cycles
that have occurred. Therefore the system software or hard-
ware does not have to be modified or de-rated as is necessary
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
The Flash Bank product family was jointly developed by SANYO and Sillicon Storage Technology,Inc.(SST),under SST's technology license. This preliminary specification is subject to change without notice.
R.1.10(12/22/99)No.xxxx-1/20
16 Megabit FlashBank Memory
2
LE28BW168T
The Auto Low Power mode reduces the typical IDD active
of WE#. ( See Figure 4-1 for WE# or 4-2 for CE# controlled
Word Program cycle timing waveforms, Table 3 for the
command sequence, and Figure 15 for a flowchart. )
read current to the range of 1mA/MHz of Read cycle time.
If a concurrent Read while Write is being performed, the IDD
is reduced to typically 40mA. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no access
time penalty.
During the Erase or Program operation, the only valid reads
from that bank are Data# Polling and Toggle Bit. The other
bank may be read.
The specified Bank, Block, or Sector Erase time is the only
time required to erase. There are no preprogramming or
other commands or cycles required either internally or
externally to erase the bank, block, or sector.
Read
The Read operation of the LE28BW168T Flash banks is
controlled by CE# and OE#, a chip enable and output enable
both have to be low for the system to obtain data from the
outputs. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance state
when OE# is high. Refer to the timing waveforms for further
details (Figure 3).
Erase Operations
The Bank Erase is initiated by a specific six-word load
sequence (See Tables 3). A Bank Erase will typically be less
than 70 ms.
An alternative to the Bank Erase in the Flash bank is the Block
or Sector Erase. The Block Erase will erase an entire Block
(32K words) in typically 15 ms. The Sector Erase will erase
an entire sector (1024 words) in typically 15 ms. The Sector
Erase provides a means to alter a single sector using the
Sector Erase and Word Program modes. The Sector Erase is
initiated by a specific six-word load sequence (see Table 3).
When the read operation is executed without address
change after power switch on, CE# should be changed the
level high to low. If the read operation is executed after
programing , CE# should be changed the level high to low.
Write
All Write operations are initiated by first issuing the Soft-
ware Data Protect (SDP) entry sequence for Bank, Block, or
Sector Erase. Word Program in the selected Flash bank.
Word Program and all Erase commands have a fixed dura-
tion, that will not vary over the life of the device, i.e., are
independent of the number of Erase/Program cycles en-
dured.
During any Sector, Block, or Bank Erase within a bank, any
other bank may be read.
Bank Erase
The LE28BW168T provides a Bank Erase mode, which
allows the user to clear the Flash bank to the "1"state. This is
useful when the entire Flash must be quickly erased.
Either Flash bank may be read to another Flash Bank during
the internally controlled write cycle.
The software Flash Bank Erase mode is initiated by issuing
the specific six-word loading sequence, as in the Software
Data Protection operation. After the loading cycle, the
device enters into an internally timed cycle.( See Table 3 for
specific codes, Figure 5-1 for the timing waveform, and
Figure12 for a flowchart. )
The device is always in the Software Data Protected mode for
all Write operations Write operations are controlled by
toggling WE# or CE#. The falling edge of WE# or CE#,
whichever occurs last, latches the address. The rising edge of
WE# or CE#, whichever occurs first, latches the data and
initiates the Erase or Program cycle.
Block Erase
For the purposes of simplification, the following descrip-
tions will assume WE# is toggled to initiate an Erase or
Program. Toggling the applicable CE# will accomplish the
same function. (Note, there are separate timing diagrams to
illustrate both WE# and CE# controlled Program or Write
commands.)
The LE28BW168T provides a Block Erase mode, which
allows the user to clear any block in the Flash bank to the
"1"state. The software Block Erase mode is initiated by
issuing the specific six-word loading sequence, as in the
Software Data Protect operation. After the loading cycle, the
device enters into an internally timed Erase cycle. (See Table
3 for specific codes, Figure 5-2 for the timing waveform, and
Figure 13 for a flowchart.) During the Erase operation, the
only valid reads are Data# Polling and Toggle Bit from the
selected bank, other banks may perform normal read.
WordProgram
The Word Program operation consists of issuing the SDP
Word Program command, initiated by forcing CE# and WE#
low, and OE# high. The words to be programmed must be in
the erased state, prior to programming. The Word Program
command programs the desired addresses word by word.
During the Word Program cycle, the addresses are latched by
the falling edge of WE#. The data is latched by the rising edge
SectorErase
The LE28BW168T provides a Sector Erase mode, which
allows the user to clear any sector in the Flash bank to the
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-2/20
16 Megabit FlashBank Memory
3
LE28BW168T
"1"state. The software Sector Erase mode is initiated by
the toggling will stop. The device is then ready for the next
operation. (See Figure 7 for Flash bank Toggle Bit timing
waveforms and Figure 16 for a flowchart.)
issuing the specific six-word loading sequence, as in the
Software Data Protect operation. After the loading cycle, the
device enters into an internally timed Erase cycle.( See Table
3 for specific codes, Figure 5-3 for the timing waveform, and
Figure 14 for a flowchart.) During the Erase operation, the
only valid reads are Data# Polling and Toggle Bit from the
selected bank, other banks may perform normal read.
Data Protection
The LE28BW168T provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Write Operation Status Detection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not
initiate a Write cycle.
The LE28BW168T provides two software means to detect the
completion of a Flash bank Program cycle, in order to optimize
the system Write cycle time. The software detection includes
two status bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The
end of Write Detection mode is enabled after the rising edge of
WE#, which initiates the internal Erase or Program cycle.
VDD Power Up/Down Detection: The Write operation is inhib-
ited when VDD is less than 1.5 volts.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
writes during power-up or power-down.
The actual completion of the nonvolatile write is a synchro-
nous with the system; therefore, either a Data# Polling or
ToggleBitreadmaybesimultaneouswiththecompletionofthe
Write cycle. If this occurs, the system will possibly get an
erroneous result, i.e. valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious device rejec-
tion, if an erroneous result occurs, the software routine should
include a loop to read the accessed location an additional two
(2) times. If both reads are valid, then the device has completed
the Write cycle, otherwise the rejection is valid.
Software Data Protection (SDP)
The LE28BW168T provides the JEDEC approved software
data protection scheme as a requirement for initiating a Write,
Erase, or Program operation. With this scheme, any Write
operation requires the inclusion of a series of three word-load
operations to precede the Word Program operation. The three-
word load sequence is used to initiate the Program cycle,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down. The
six-word sequence is required to initiate any Bank, Block, or
Sector Erase operation.
There is no provision to abort an Erase or Program operation,
once initiated. For the SANYO Flash technology, the associ-
ated Erase and Program times are so fast, relative to system
reset times, there is no value in aborting the operation. Note,
reads can always occur from any bank not performing an Erase
or Program operation.
TherequirementsforJEDECcompliantSDPareinbyteformat.
The LE28BW168T is organized by word; therefore, the con-
tents of DQ8 to DQ15 are "Don't Care"during any SDP (3-word
or 6-word) command sequence.
Should the system reset, while a Block or Sector Erase or Word
Program is in progress in the bank where the boot code is
stored, the system must wait for the completion of the operation
before reading that bank. Since the maximum time the system
wouldhavetowaitis25ms(foraBlockErase),thesystemability
to read the boot code would not be affected.
During the SDP load command sequence, the SDP load cycle
is suspended when WE# is high. This means a read may occur
to any other bank during the SDP load sequence.
The bank reserve in SDP load sequence is reserved by the bus
cycle of command materialization. If the command sequence
is aborted, e.g., an incorrect address is loaded, or incorrect data
is loaded, the device will return to the Read mode within TRC
of execution of the load error.
Data# Polling (DQ7)
When the LE28BW168T is in the internal Flash bank Program
cycle, any attempt to read DQ7 of the last word loaded during
the Flash bank Word Load cycle will receive the complement
of the true data. Once the Write cycle is completed, DQ7 will
show true data. The device is then ready for the next operation.
(SeeFigure6 fortheFlashbankDataPollingtimingwaveforms
and Figure 16 for a flowchart.)
Concurrent Read and Write Operations
The LE28BW168T provides the unique benefit of being able
to read any bank, while simultaneously erasing, or program-
ming one other bank. This allows data alteration code to be
executedfromonebank, whilealteringthedatainanotherbank.
The next table lists all valid states.
Toggle Bit (DQ6)
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ6 will produce alternating 0's and 1's, i.e.
toggling between 0 and 1. When the Write cycle is completed,
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-3/20
16 Megabit FlashBank Memory
4
LE28BW168T
Concurrent Read/Write State Table
Product Identification Table
Bank1
Read
Bank2
No Operation
Write
Word
0000H
0001H
0001H
Data
Maker ID
0062H
2595H
2596H
Read
Device Code(Bank1)
Device Code(Bank2)
Write
Read
No Operation
Write
Write
No Operation
Read
Device ID codes are unique to each bank. Should a chip ID
be required, any of the bank IDs may be used as the chip
ID. While in the read software ID mode, no other operation
is allowed until after exiting these modes.
No Operation
Note: For the purposes of this table, write means to Block, Sector, or Bank Erase, or Word
Program as applicable to the appropriate bank.
Thedevicewill ignoreall SDPcommandsand togglingof WE#
when an Erase or Program operation is in progress. Note,
Product Identification entry commands use SDP; therefore,
this command will also be ignored while an Erase or Program,
operation is in progress.
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identificationmodemustbeexited. Exitisaccomplishedby
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be
used to reset the device to the Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g., not read correctly. For
details, (see Table 3 for software operation and Figures 9 for
timingwaveforms.)
Product Identification
The product identification mode identifies the device
manufacturer as SANYO and provides a code to identify
each bank. The manufacturer ID is the same for each bank;
however, each bank has a separate device ID. Each bank is
individually accessed using the applicable Bank Address and
a software command. Users may wish to use the device ID
operation to identify the write algorithm requirements for
each bank.
(For details, see Table 3 for software operation and Figures
8 for timing waveforms. )
A16
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
WE#
NC
A19
NC
NC
BE#3
NC
A18
A17
A7
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
A0
9
10
11
12
13
14
15
16
17
18
19
20
21
TSOP 48
Type - I
Normal Bend
(10mm x 14mm)
A6
A5
A4
A3 22
A2 23
A1
24
CE#
Figure 1 : Pin Description : TSOP-1 (10mm x 14mm)
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-4/20
16 Megabit FlashBank Memory
5
LE28BW168T
Symbol
A19
Pin Name
Bank Select address
Function
To activate the Bank1 when low, to activate the Bank2 when high.
To provide Flash Bank address
A18-A0
A18-A15
A18-A10
Flash Bank addresses
Flash Bank Block addresses
Flash Bank Sector addresses
To select a Flash Bank Block for erase
To select a Flash Bank Sector for erase
To output data during read cycle and receive input data during write
cycle. The outputs are in tristate when OE# is high or CE# is high.
DQ15-DQ0 Data Input/Output
CE#
OE#
WE#
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the Flash Bank when CE# is low.
To gate the data output buffers.
To control the write, erase or program operations.
To provide 3.0 volts supply.(3.0 volts ± 3.3volts)
VDD
GND
NC
Ground
No Connection
Unconnected Pins
Note)BE3# should be connected to VDD signal as usual.
Table1: Pin Description
Y-Decoder
Charge Pump
&
Vref.
512Kx16
Flash Bank1
Address Buffers
&
X-Decoder
512Kx16
Flash Bank2
Latches
A19-A0
CE#
DQ15-DQ0
Control Logic
OE#
WE#
I/O Buffers & Data Latches
Figure2: Functinaly Block Diagram
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-5/20
16 Megabit FlashBank Memory
6
LE28BW168T
Array Operating Mode
CE#
OE#
WE#
DQ
A19
A18-A0
Read
Bank1
V
IL
IL
V
IL
IL
V
IH
IH
D
OUT
V
IL
A
A
IN
IN
Bank2
V
V
V
DOUT
VIH
Block Erase
Bank1
V
IL
IL
V
IH
IH
V
IL
IL
D
IN
V
IL
See Table:3
See Table:3
Bank2
V
V
V
DIN
VIH
Sector Erase
Bank1
V
IL
IL
V
IH
IH
V
IL
IL
D
IN
IN
V
IL
See Table:3
See Table:3
Bank2
V
V
V
D
VIH
Program
Bank1
V
IL
IL
V
IH
IH
V
IL
IL
D
IN
IN
V
IL
See Table:3
Bank2
V
V
V
D
VIH
See Table:3
Standby
Write Inhibit
V
IH
IH
X
X
High Z
X
X
X
X
V
VIL
VIL
X
Bank Erase
Bank1
V
IL
IL
V
IH
IH
V
IL
IL
D
IN
IN
V
IL
See Table:3
See Table:3
Bank2
V
V
V
D
VIH
Status Operating Mode
CE#
OE#
WE#
DQ
A19
A18-A0
Product Identification
Bank1
V
IL
IL
V
IL
IL
V
IH
IH
D
OUT
V
IL
A
18-A1 = VIL
Bank2
V
V
V
DOUT
VIH
A0
= VIL or VIH
Note: Entering illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or
write will continue to normal completion.
Table:2 Operating Modes Selection
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
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16 Megabit FlashBank Memory
7
LE28BW168T
Table:3 Software Command Codes
Command Code
1stBus Cycle
2ndBus Cycle
3rdBus Cycle
4thBus Cycle
5thBus Cycle
6thBus Cycle
Address
Note1,4
Data
Address
Note1,4
Data
Address
Data
Address
Note1,4
Data
Address
Note1,4
Data
Address
Note1,4
Data
Note5
Note5
Note1,4
5555
Note5
Note5
Note5
Note5
5555
AA
2AAA
55
90
Software ID Entry
Note2
Note3
+
BAX
5555
AX
5555
5555
5555
AA
AA
AA
2AAA
2AAA
2AAA
55
55
55
F0
A0
80
Software ID Exit
Word Program
Sector Erase
+
B
Word
Address
Data
In
5555
5555
SAX
5555
5555
5555
AA
AA
AA
2AAA
2AAA
2AAA
55
55
55
30
50
10
+
BAX
LAX
5555
5555
AA
AA
2AAA
2AAA
55
55
5555
5555
80
80
Block Erase
Bank Erase
+
BAX
5555
+
BAX
Notes for Software Product ID Command Code:
1. Command Code Address format : A14 - A0 are in HEX code.
2.With A14 - A0 = 0;
Sanyo Manufacturer Code = 0062H is read with A0 = 0.
Sanyo LE28BW168T Device code 2595H, 2596H is read with A0 = 1.
3.The device does not remain in software Product ID Mode if powered down.
4.Address form A14 to A18 are 'Don't Care' for Command sequences.
A19 is bank selection address has been reserved in last bus cycle of Command sequence.
5.Data format DQ0 to DQ7 are in HEX and DQ8 to DQ15 are "Don't Care".
6.BAX = Bank address: A19, LAX = Block address:A18 to A15, SAX = Sector address: A18 to A10.
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
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16 Megabit FlashBank Memory
8
LE28BW168T
[Absolute Maximum Stress Ratings]
Applied conditions greater than those listed under "absolute maximum Stress Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in
the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.
Storage Temperature
: -65ºC to +150ºC
: -0.5V to VDD + 0.5V
: -1.0V to VDD + 1.0V
: 1.0W
D. C. Voltage on Any Pin to Ground Potential
Transient Voltage (<20 ns) on Any Pin to Ground Potential
Package Power Dissipation Capability (Ta = 25ºC)
[Operating Range]
Ambient Temperature
: -40ºC to +80ºC
: 3.0V ± 0.3V
VDD
[AC condition of Test]
: 5 ns
Input Rise/Fall Time
Output Load
: CL = 30 pF
(See Figures 10 and 11)
[DC Operating Characteristics]
Symbol
Parameter
Min
Max
20
Unit
mA
Test Condition
CE# = VIL, WE# = VIH, I/O's open,
Power Supply current
Read
I
DD
Address Input = IL/VIH, at f =10MHz
DD = VDD(Max)
CE# = WE# = VIL, OE# = VIH, VDD = VDD(Max)
V
,
V
Write
40
60
mA
mA
Read + Erase /
Program
CE# = VIL, OE# = WE# = VIH
Address Input =
,
V
IL/VIH
,
at f =10MHz
,
WE# = VIH,
VDD = VDD(Max)
Standby current
(CMOS input)
40
µA
CE# = VIHC , VDD = VDD(Max)
I
I
SB
I
LI
Input Leak current
Output Leak current
10
10
µA
µA
V
IN = GND to VDD,
OUT = GND to VDD,
V
DD = VDD(Max)
V
VDD = VDD(Max)
OL
V
V
V
V
IL
ILC
IH
IHC
OL
OH
Input Low Voltage
Input Low Voltag (CMOS)
Input High Voltag
V
DD*0.2
0.2
V
V
V
V
V
V
DD*0.8
DD-0.2
Input High Voltge (CMOS)
V
V
I
I
OL = 100 , VDD = VDD(Min)
OH = -100µA, VDD = VDD(Min)
µ
A
Output Low Voltag
Output High Voltag
0.2
V
V
VDD-0.2
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-8/20
16 Megabit FlashBank Memory
9
LE28BW168T
[RecommendSystemPower-upTimings]
Symbol
Parameter
Max
Units
PU-READ(1)
Power-up to Read Operation
Power-up to Write Operation
200
200
µs
µs
T
T
PU-WRITE(1)
Note(1): This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
[Capacitance (Ta = 25ºC, f = 1MHz, other pins open)]
Symbol
Parameter
Test Condition
DQ = 0V
Max
(1)
C
DQ
I/O Pin Capacitance
Input Capacitance
V
12PF
6PF
(1)
VIN = 0V
CIN
Note(1): This parameter is measured only for initial qualirication and after a design or process change that could affect this parameter.
[Reliability Characteristic]
Symbol
Parameter
Min Spec
Units
)
(1
Endurance
Data Retention
10,000
10
Cycle/Sector
Years
N
T
END
(1)
DR
Note(1): This parameter is measured only for initial qualirication and after a design or process change that could affect this parameter.
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-9/20
16 Megabit FlashBank Memory
10
LE28BW168T
[AC Characteristic]
Read Cycle Timing Parameters
Symbol
Parameter
8 0
9 0
Units
Min
80
Max
Min
90
Max
T
T
T
RC
CE
AA
Raed Cycle Time
ns
ns
ns
ns
ns
CE# Access Time
80
80
40
90
90
50
Address Access Time
OE# Access Time
TOE
(1)
(1)
(1)
(1)
BE# Low to Active Output
0
0
0
0
T
CLZ
OE# Low to Active Output
BE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
ns
ns
ns
T
OLZ
CHZ
30
30
30
30
T
T
OHZ
(1)
OH
0
0
T
Write, Erase, Program Cycle, Timing Parameters
Symbol
Parameter
Word Program Time
Min
Max
Units
T
BP
SE
20
25
µs
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
T
Sector Erase Time
Block Erase Time
Bank Erase Time
Address Setup Time
Address Hold Time
CE# Setup Time
CE# Hold Time
TLE
25
TBE
TAS
TAH
100
0
50
0
T
CES
CEH
T
0
T
WES
WEH
WE# Setup Time
WE# Hold Time
0
T
0
T
OES
OEH
OE# High Setup Time
OE# High Hold Time
WE# Puls Low Width
WE# Puls High Time
Data Setup Time
Data Hold Time
0
T
0
T
WP
WPH
50
30
50
0
T
T
DS
DH
T
(1)
VDDR
VDD Rise Time
0.1
150
50
T
TIDA
ID READ / Exit Cycle Time
Note:(1) This parameter is measured only for initial qualification and after a desgin or process change that could affect this parameter.
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-10/20
16 Megabit FlashBank Memory
11
LE28BW168T
T
T
AA
RC
ADDRESS A
A
0
19-
T
CE
CE#
OE#
WE#
T
OE
T
OHZ
T
V
OLZ
IH
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ DQ
15-
0
DATA VALID
DATA VALID
16141\168T\F3_E
Figure 3: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
A
19- 0
T
AH
T
DH
T
WP
WE#
OE#
CE#
T
T
AS
DS
T
WPH
T
CEH
T
CES
DQ DQ
15-
0
AA
55
A0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
16141\168\F4-1_E
Figure 4-1: WE# Controlled Word Program Cycle Timing Diagram
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-11/20
16 Megabit FlashBank Memory
12
LE28BW168T
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
A
19- 0
T
AH
T
DH
T
WP
CE#
OE#
WE#
T
T
AS
DS
T
WPH
T
WEH
DATA
T
WES
DQ DQ
15-
0
AA
55
A0
SW0
SW1
SW2
WORD
(ADDR/DATA)
16141\168\F4-2_E
Figure 4-2: CE# Controlled Word Program Cycle Timing Diagram
T
BE
SIX-BYTE CODE FOR BANK ERASE
5555
2AAA
5555
5555
2AAA
5555+BAX
ADDRESS A
A
19- 0
T
AH
T
AS
CE#
OE#
WE#
T
DS
T
T
WPH
WP
T
DH
DQ DQ
15-
0
AA
55
80
AA
55
10
SW0
SW1
SW2
SW3
SW4
SW5
16141\168T\F5-1_E
Figure 5-1: Bank Erase Cycle Timing Diagram
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-12/20
16 Megabit FlashBank Memory
13
LE28BW168T
T
LE
SIX-BYTE CODE FOR BLOCK ERASE
5555
2AAA
5555
5555
2AAA
L
+B
AX AX
ADDRESS A
A
19- 0
T
AH
T
AS
CE#
OE#
WE#
T
DS
T
T
T
WPH
WP
DH
DQ DQ
15-
0
AA
55
80
AA
55
50
SW0
SW1
SW2
SW3
SW4
SW5
16141\168T\F5-2_E
Figure 5-2: Block Erase C ycle Timing Diagram
T
SE
SIX-BYTE CODE FOR SECTOR ERASE
5555
2AAA
5555
5555
2AAA
S
+B
AX AX
ADDRESS A
A
19- 0
T
AH
T
AS
CE#
OE#
WE#
T
DS
T
T
T
WPH
WP
DH
DQ DQ
15-
0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
16141\168T\F5-3_E
Figure 5-3: Sector Erase Cycle Timing Diagram
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-13/20
16 Megabit FlashBank Memory
14
LE28BW168T
ADDRESS A
A
19- 0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
Data
Data#
Data#
Data
16141\168T\ F6_E
Figure 6: Data Polling Timing Diagram
ADDRESS A
A
19- 0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
16141\168T\F7_E
Figure 7: Toggle Bit Timing Diagram
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-14/20
16 Megabit FlashBank Memory
15
LE28BW168T
Three-Byte Sequence for
Software ID Entry
0000+BAX 0001+BAX
ADDRESS A
A
5555
2AAA
5555+BAX
19- 0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
T
AA
DQ DQ
15-
0
55
SW1
90
0062
2595/2596
SW0
SW2
16141\168T\F8_E
Figure8:SoftwareIDEntryandRead
Three-Byte Sequence for
Software ID Exit
5555
2AAA
5555+BAX
ADDRESS A
A
19- 0
DQ DQ
15-
AA
55
F0
0
T
IDA
CE#
OE#
T
WP
WE#
T
WPH
16141\168T\F9_E
SW0
SW1
SW2
Figure9:SoftwareIDExit
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-15/20
16 Megabit FlashBank Memory
16
LE28BW168T
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
16141\168T\F10_E
AC test inputs are driven at VIHT (VDD*0.9) for a logic "1"and VILT (VDD*0.1) for a logic "0"
Measurement reference points for inputs and outputs are at VHT (VDD*0.7) and VLT (VDD*0.3)
Input rise and fall times (10% « 90%) are <10 ns.
Figure 10: AC I/O ReferenceWaveforms
V
DD
TO TESTER
R
L HIGH
TO DUT
C
L
R
L LOW
16141\168T\F11_E
Figure11:ATestLoadExample
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-16/20
16 Megabit FlashBank Memory
17
LE28BW168T
Bank Erase
Start
Software Data Protect
Bank Erase
Command
Wait for End of Erase
(T , Data #Polling,
BE
or Toggle Bit)
Bank Erase Complete
16141\168T\ F12_E
Figure 12: Bank Erase Flowchart
Block Erase
Start
Software Data Protect
Block Erase
Flash Bank Command
Set Block Address
Wait for End of Erase
(T , Data# Polling,
LE
or Toggle Bit)
Block Erase Complete
16141\168T\F13_E
Figure 13: Block Erase Flowchart
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-17/20
16 Megabit FlashBank Memory
18
LE28BW168T
Sector Erase
Start
Software Data Protect
Sector Erase
Command
Set Sector Address
Wait for End of Erase
(T
Data # Polling,
or Toggle Bit)
SE,
Sector Erase Complete
16141\168T\ F14_E
Figure 14: Sector Erase Flowchart
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-18/20
16 Megabit FlashBank Memory
19
LE28BW168T
Word Program
Start
Software Data Protect
Program Command
Set Word Address
Load Word Data
Wait for End of Program
(T , Data # Polling,
BP
or Toggle Bit)
Word Program Complete
16141\168T\F15_E
Figure15:WordProgramFlowchart
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.10(12/22/99)No.xxxx-19/20
16 Megabit FlashBank Memory
20
LE28BW168T
Internal Timer
Toggle Bit
Data# Polling
Erase or Program
Operation Initiated
Erase or Program
Operation Initiated
Erase or Program
Operation Initiated
Read DQ7 of the last
address set (or any address
within selected bank,
Read a word from a bank,
block, sector, or word
selected
Wait for T , T , T
BP SE LE
,
T
BE
block, sector for erase)
Erase or Program
Completed
Read the same
word again
No
Is DQ7 same
as bit loaded?
Yes
No
Is DQ6 the same?
Yes
Erase or Program
Completed
Erase or Program
Completed
16141\168T\ F16_E
Figure 16: End of Erase or Program Wait Options Flowchart
SANYOElectricCo.,Ltd.SemiconductorCompany 1-1-1SakataOizumiGunmaJapan
R.1.10(12/22/99) No.xxxx-20/20
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