LE28FV4101H-40T [ONSEMI]
Flash, 256KX16, 40ns, PBGA52, 6 X 6 MM, FLGA-52;
| 型号： | LE28FV4101H-40T |
| 厂家： | 
ONSEMI |
| 描述： | Flash, 256KX16, 40ns, PBGA52, 6 X 6 MM, FLGA-52 |
| 文件： | 总28页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Specification
CMOS LSI
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M(512K×8bits, 256K×16bits) Flash EEPROM
Features
Low Power Consumption
CMOS Flash EEPROM Technology
Single Voltage Read and Write Operations
Active Current (Read) : 40 mA (Max.)
LE28FV4101
LE28FW4101
LE28FU4101
: 3.0V~3.6V
: 2.7V~3.6V
: 2.3V~3.6V
µ
: 40 A (Max.)
Standby Current
High Read/Write Reliability
Sector-write Endurance Cycles: 104
10 Years Data Retention
Latched Address and Data
Self-timed Erase and Programming
Word Programming
Sector Erase Capability: 1kWord per sector
: (2kByte per sector)
Block Erase Capability: 32kWord per Block
: (64kByte per Block)
Fast Access Time
µ
: 20 s (Max.)
LE28FV/FW4101
LE28FU4101
End of Write Detection
LE28FV4101T,H-40T :40ns(Max.)
LE28FV4101T,H-50T :50ns(Max.)
LE28FV4101T,H-70T :70ns(Max.)
µ
: 30 s (Max.)
:Toggle Bit , DATA# Polling
:RD/BY#
Hardware/Software Data Protection
Protected cell area
LE28FW4101T,H-45T :45ns(Max.)
LE28FW4101T,H-55T :55ns(Max.)
LE28FW4101T,H-70T :70ns(Max.)
:
Top Block(16K-Bytes from the top address)
Whole chip(512K-Bytes)
Packages Available :
LE28FU4101T,H-70T :70ns(Max.)
LE28FU4101T,H-85T :85ns(Max.)
LE28FU4101T,H-10T :100ns(Max.)
LE28FV,FW,FU4101T :TSOP-48 (12mm x 20mm)
LE28FV,FW,FU4101H :FLGA-52 (6mm x 6mm)
the write cycle. To protect against an inadvertent write, the
LE28FV4101/LE28FW4101/LE28FU4101 has on chip
hardware and software data protection schemes. Designed,
manufactured, and tested for a wide spectrum of applications,
LE28FV4101/LE28FW4101/LE28FU4101 is offered with a
guaranteed sector write endurance of 104 cycles. Data reten-
tion is rated greater than 10 years.
Product Description
The LE28FV4101/LE28FW4101/LE28FU4101 is a 256K
×
×
16 or 512K 8 CMOS sector erase, Word(Byte) program
EEPROM.
The LE28FV4101/LE28FW4101/LE28FU4101 is manu-
factured using SANYO's proprietary, high performance
CMOS Flash EEPROM technology. Breakthroughs in
EEPROM cell design and process architecture attain better
reliability and manufacturability compared with conven-
tional approaches.
Device Operation
The LE28FV4101/LE28FW4101/LE28FU4101 operates
random read, Word(Byte)-program, sector or block or
Chip-erase flash memory.
LE28FV4101/LE28FW4101/LE28FU4101 erases and pro-
grams with single power supply.
LE28FV4101/LE28FW4101/LE28FU4101 is offered in
FLGA52 (6mm x 6mm) packages and TSOP48(12mm x
20mm) package.
The Self-Power Conservation feature automatically puts the
LE28FV4101/LE28FW4101/LE28FU4101 in a low power
mode after data has been accessed with a valid read opera-
tion. This reduces the IDD active read current from
40mA(Max) to 300µA(Typ.). The device exits the Self
Power Conservation mode with any address transition or
control signal transition used to initiate another read cycle,
with no access time penalty.
Featuring high performance programming,
LE28FV4101/LE28FW4101/LE28FU4101 programs in
µ
µ
20 s/30 s(max). The
LE28FV4101/LE28FW4101/LE28FU4101 sector (1k
Words) erases in 25ms(Max.). Both program and erase times
can be optimized using interface feature such as Toggle bit,
DATA# Polling or RD/BY# to indicate the completion of
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 6.0 Mar. 28 2001 -AY/ay -1/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Standby
Chip-Erase
The LE28FV4101/LE28FW4101/LE28FU4101 provides a
chip-erase mode, which allows the user to clear the Flash
array to the “1” state. This is useful when the entire de-
vice must be quickly erased.
Standby mode reduces current consumption greatly with the
Output pins in High-Impedance state. By setting both of
CE# and RESET# to VDD ±0.3V ,otherwise RESET# to
VSS ±0.3V, device enter the standby mode.
The chip erase mode is initiated by issuing the specific six-
Word loading sequence, as in the Software Data Protection
operation. After the loading cycle, the device enters into an
internally timed cycle. See Table 3 for specific codes, Fig-
ure 13~16 for the timing waveform, and Figure 32 for a
flowchart.
Standby mode cannot be set when the device is not in read
mode.( i.e Erase or Program mode)
Read
The read operation is controlled by CE# and OE#, a chip
enable and output enable both have to be low for the system
to obtain data from the outputs. When CE# is high, the chip
is deselected. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when OE# is high. Refer to the timing waveforms
for further details (Figure 3~4).
Block-Erase
The LE28FV4101/LE28FW4101/LE28FU4101 provides a
block-erase mode.
Block-Erase mode is based on uniform Block size of
32KWord(64kByte), which allows the user to clear any
block in the Flash array to the “1” state.
Write
All write operations are initiated by the JEDEC approved
Software Data Protect (SDP) entry sequence, for
Chip_Erase, Block_Erase, Sector_Erase and Program. Pro-
gram and all erase commands have a fixed duration, that
will not vary over the life of the device, i.e., are indepen-
dent of the number of erase/program cycles endured.
The block-erase mode is initiated by issuing the specific
six-Word loading sequence, as in the Software Data Protect
operation. After the loading cycle, the device enters into an
internally timed erase cycle. See Table 3 for specific codes,
Figure 13~16 for the timing waveform, and Figure 31 for a
flowchart.
The device is always in the Software Data Protected mode
for all Write operations. Write operations are controlled by
toggling of WE# or CE#. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first. After SDP sequence, the device
enter the selected mode automatically. When the wrong
address or data are offered, the device interrupt the SDP
mode at once and go back to read mode. See Figure 5~8 for
the timing waveform.
Sector-Erase
The LE28FV4101/LE28FW4101/LE28FU4101 provides a
sector-erase mode
Sector-Erase mode is based on uniform sector size of
1kWord(2kByte), which allows the user to clear any sector
in the Flash array to the “1” state.
The sector-erase mode is initiated by issuing the specific
six-Word loading sequence, as in the Software Data Protect
operation. After the loading cycle, the device enters into an
internally timed erase cycle. See Table 3 for specific codes,
Figure 13~16 for the timing waveform, and Figure 30 for a
flowchart.
Program
The program operation consists of issuing the SDP program
command.
Its command can be to program value to one address in
memory cell array at a time. The command require 4-bus
cycle operation, the final write operation latches the address
and data in the internal state machine. Programming opera-
tion starts with either the rising of WE#, CE#, whichever
occurs first. The Program operation, once initiated, will be
completed within 20µs(30µs).
See Figure 17~20 program cycle timing waveform, Table 3
for the command sequence, and Figure 33 for a Flowchart.
Note that the Program command cannot change a bit set at
“0” back to “1”. One of the Erase command must be used to
the all bit in sector ,Block or in the whole memory from “0”
to “1”.
Chip Protection , Block Protection /
Un-protection
Chip Protection and Block Protection disables both pro-
gram and erase operation.
Chip Protection defends from inadvertent write in the whole
memory, and consists of issuing the SDP command.
Block Protection defends 8kWord(16kByte) Top Block
from inadvertent write, and consists of issuing the SDP
command.
Un-protection can be canceling both Chip Protection and
Block Protection, and consists of issuing the SDP command.
SANYO Electric Co., Ltd.
2/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
See Table 3 for specific codes, Figure 21~22 for the timing
waveform.
Toggle Bit (DQ6)
During the Flash internal write cycle, any consecutive at-
tempts to read DQ6 will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is com-
pleted, the toggling will stop. The device is then ready for
the next operation. See Figure 29 for Flash Toggle Bit
timing waveforms.
Protect Verification
Protect Verification mode indicate Chip Protection or
Block Protection status, consists of issuing the SDP com-
mand. See Table 3 for specific codes.
To verify which protect mode the device is in, read follow-
ing addresses and the data shows the protect mode. i.e.
Address(0004H:Byte mode,0002H Word mode) ,
Data(01H:Byte mode,0001H: Word mode) shows sector
protect.
Address(0004H:Byte mode,0002H: Word mode),
Data(00H:Byte mode,0000H: Word mode) shows unprotect.
Address(0006H:Byte mode,0003H Word mode),
Data(01H:Byte mode,0001H Word mode) shows chip pro-
tect.
RD/BY#
LE28FV4101/LE28FW4101/LE28FU4101 has RD/BY#
pin to be able to detect the completion of a Write cycle.
Output form of RD/BY# pin is internally connected to the
open drained transistor. When the pin is at "L", the device
is busy for a write cycle. When the pin is at "High-Z", the
device is ready for accepting commands. Because of
RD/BY# pin being open drain, User needs to connect a pull
up resistor between RD/BY# pin and VDD. If User use a
number of Flash memories, User may as well connect the
pull up resistor to the memories in parallel.
Address(0006H:Byte mode,0003H: Word mode),
Data(00H:Byte mode,0000H Word mode) shows unprotect.
See Figure 26~27 for RD/BY# timing waveforms.
In order to return to the standard read mode, the Protect
Verification mode must be exited. Exit is accomplished by
issuing the Read/Reset command, which returns the device
to normal operation.
Data Protection
The LE28FV4101/LE28FW4101/LE28FU4101 provides
both hardware and software features to protect nonvolatile
data from inadvertent writes.
Write Operation Status Detection
The LE28FV4101/LE28FW4101/LE28FU4101 provides
two software means to detect the completion of write cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: DATA# Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising edge of WE#, which initi-
ates the internal write, erase, or program cycle.
Hardware Data Protection
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation.
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a write cycle.
VDD Power Up/Down Detection: Immediately after the
power-up, the device is in read mode. The write operation
is inhibited when VDD is less than 1.5 volts. This prevents
inadvertent writes during power-up or power-down.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a DATA# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system will possibly
get an erroneous result, i.e. valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
device rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location
an additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Software Data Protection (SDP)
The LE28FV4101/LE28FW4101/LE28FU4101 provide the
JEDEC approved software data protection scheme as a
requirement for initiating a Write, Erase, or Program op-
eration. With this scheme, any write operation requires the
inclusion of a series of three Cycle-load operations to
precede the Word program operation. The three Cycle-load
sequence is used to initiate the program cycle, providing
optimal protection from inadvertent write operations, e.g.,
during the system power-up or power-down. The six-Cycle
Sequence is required to initiate any chip, block, or sector
erase operation.
DATA# Polling (DQ7)
When the LE28FV4101/LE28FW4101/LE28FU4101 is in
the internal Flash write cycle, any attempt to read DQ7 of
the last Word loaded during the Flash Word-load cycle will
receive the complement of the true data. Once the write
cycle is completed, DQ7 will show true data. The device is
then ready for the next operation. See Figure 28 for Flash
DATA# Polling timing waveforms.
The requirements for JEDEC compliant SDP are in Byte
formats. The LE28FV4101/LE28FW4101/LE28FU4101
are organized by Word; therefore, the contents of DQ8 to
DQ15 are “Don’t care” during any SDP (3-Cycle or 6-
Cycle) command sequence.
SANYO Electric Co., Ltd.
3/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur during the SDP load sequence.
Read/RESET
In order to return to the standard read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Read/Reset command, which returns the device
to normal operation. This command may also be used to
reset the device to the read mode after any inadvertent tran-
sient condition that apparently causes the device to behave
abnormally, e.g., not read correctly.
Hardware RESET
To quit the Erase or Program operation, LE28FV4101/
LE28FW4101/ LE28FU4101 can be reset by forcing RE-
SET# pin into low. After receiving RESET# pulse, the
device begins Reset operation and terminates the Reset
operation 10µs(max) later. After the hardware reset opera-
tion, all output pins are in high-impedance state when
RESET# is “L”, or device is in read mode after the period
of tRST by setting RESET# pin “H”.
Immediately after the power-up, device should be set to read
mode without using READ/RESET command. For details, see
Table 3 for software operation and Figures 9~12 for timing
waveforms.
Decoupling Capacitors
Product Identification
µ
Ceramic capacitor (0.1 F) must be added between VDD
The product identification mode identifies the device manu-
facturer as SANYO. Users may wish to use the device ID
operation to identify the write algorithm requirements. For
details, see Table 3 for software operation and Figures
23~24 for timing waveforms.
and VSS for each device to assure stable flash memory op-
eration.
The attention to the usage of this LSI
For the reasons of using ATD (Address Transition De-
tector) Circuit, the output data of this LSI directly after
supplying voltage, program operation or erase operation are
invalid. The valid data would be offered after the transition
of at least one of CE# or address signals under the stable
voltage.
In case of power on, We recommend to input “RESET#”
signal in order to do initial the internal circuit.
Figure1: Pin Connection
TSOP-48(12mm x 20mm)
A16
A15
A14
A13
A12
A11
A10
A9
A8
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
NC
RD/BY#
NC
(Top View)
A17
DQ9
DQ1
DQ8
DQ0
OE#
Vss
A7
A6
A5
A4
A3
A2
A1
CE#
A0
SANYO Electric Co., Ltd.
4/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
FLGA-52(6mm x 6mm) Top View (Land facing down)
H
G
F
E
D
C
B
A
NC
A7
NC
NC
RESET#
NC
A9
NC
1
2
3
4
5
6
7
8
A5
A3
A6
A4
A17
NC
WP#
A8
A10
A12
A11
A13
A15
A16
VSS
DQ7
NC
RD/BY#
NC
A1
A2
NC
NC
NC
NC
A14
A0
CE#
OE#
DQ8
DQ1
BYTE#
DQ15
DQ14
DQ6
VSS
DQ0
NC
DQ10
DQ3
DQ12
DQ4
DQ9
DQ2
DQ13
DQ5
DQ11
VDD
Figure2: Functional Block Diagram
X-Decoder
A17-A0
Memory Cell Array
Add Buff
&
Latches
Y-Decoder
CE#
I/O Buff &
Data Latches
Control Logic
OE#
WE#
DQ15/A-1
DQ14~DQ0
BYTE# RESET# RD/BY#
SANYO Electric Co., Ltd.
5/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Table1: Pin Description
Symbol
A17-A0
Pin Name
Functions
To provide memory address. Addresses are internally latched during write cycle.
Address Inputs
To output data during read cycle and receive input data during write cycles.
Data is internally latched during a write cycle.
DQ14-DQ0 Data Input/Output
The outputs are in high-Impedance when OE# or CE# is high.
Data Input/Output
DQ15/A-1
When BYTE# is High (WORD mode), This pin is DQ15 Input/Output.
When BYTE# is Low (BYTE mode), This pin behaves as an address input.
To activate the device when CE# is low.
or address Input
CE#
Chip Enable
Deselects and puts the device to standby, when CE# is high.
To activate the data output buffers. OE# is active low.
To activate the write operation. WE# is active low.
OE#
Output Enable
Write Enable
WE#
Device operates in the BYTE mode, When BYTE# is low.
Device operates in the WORD mode, When BYTE# is high.
BYTE#
Select BYTE/WORD
Hardware method to reset the device for reading array data. RESET# is active low.
When output is low, The device is actively erasing or programming.
RESET# Hardware Reset Input
RD/BY#
Ready / Busy
To provide 3.0V~3.6V-Volt supply (LE28FV4101)
To provide 2.7V~3.6V-Volt supply (LE28FW4101)
To provide 2.3V~3.6V-Volt supply (LE28FU4101)
VDD
Power Supply
VSS
NC
Ground
Unconnected Pins
No Connection
Table 2: Operation Modes Selection
Byte Mode (BYTE#=“L”)
Mode
Read
Write
CE#
OE#
WE#
RESET#
VIH
VIH
VIH
VIH
Address
AIN
AIN
X
DQ7-0
DOUT
DIN
DQ14-8
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ15/A-1
VIL VIL VIH
VIL VIH VIL
AIN
AIN
X
X
X
Standby / Write Inhibit VIH
X
VIL
X
X
X
VIH
X
High-Z
X
X
X
X
X
X
High-Z/DOUT
High-Z/DOUT
High-Z
Write Inhibit
VIH
VIL
Reset
X
X
Word Mode (BYTE#=“H”)
Mode
Read
Write
CE#
OE#
WE#
RESET#
VIH
VIH
VIH
VIH
Address
AIN
AIN
X
DQ7-0
DQ14-8
DOUT
DIN
High-Z
DQ15/A-1
VIL VIL VIH
VIL VIH VIL
Standby / Write Inhibit VIH
X
VIL
X
X
X
VIH
X
X
X
X
X
X
X
High-Z/DOUT
High-Z/DOUT
High-Z
Write Inhibit
VIH
VIL
Reset
X
SANYO Electric Co., Ltd.
6/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Table3: Command Summary
Byte Mode (BYTE#=“L”)
Required
Cycle
Bus Write Cycle
3rd 4th
Addr. Data Addr. Data Addr. Data
1st
2nd
5th
6th
Command
Addr.
Data Addr. Data
Addr.
Data
Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2
Read / Reset
1
3
3
4
6
6
6
4
4
4
XXX
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
F0
AA
AA
AA
AA
AA
AA
AA
AA
AA
555
555
555
555
555
555
555
555
555
55
55
55
55
55
55
55
55
55
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
F0
90
A0
80
80
80
E0
D0
E0
RA
RD
Note5
Software ID Entry / Protect Verify
Byte Program
Note3,4 Note3,4
PA
PD
AA
AA
AA
00
Note5
555
Sector Erase
AAA
AAA
AAA
XXX
XXX
XXX
55 Note5 SA 30
55 Note5 BA 50
Block Erase
555
Chip Erase
555
55
AAA
10
Block Protection
Chip Protection
Un-protection
00
01
Word Mode (BYTE#=“H”)
Required
Cycle
Bus Write Cycle
4th
1st
2nd
3rd
5th
Data Addr. Data
6th
Command
Addr. Data Addr. Data Addr. Data Addr.
Addr.
Data
Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2
1
3
3
4
6
6
6
4
4
4
XXX
555
555
555
555
555
555
555
555
555
F0
Read / Reset
AA
AA
AA
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
55
55
55
555
555
555
555
555
555
555
555
555
F0
RA
RD
Note5
Software ID Entry / Protect Verify
Word Program
90 Note3,4 Note3,4
A0
80
80
80
E0
D0
E0
PA
555
PD
AA
AA
AA
00
Note5
2AA
2AA
2AA
Sector Erase
55 Note5 SA 30
55 Note5 BA 50
Block Erase
555
Chip Erase
555
55
555
10
Block Protection
Chip Protection
Un-protection
XXX
XXX
XXX
00
01
Note 1. Address Format:
Note 2. Data Format:
A10~A-1(Byte mode),A11~A0(Word mode). All Value in the table is in hexadecimal.
A17~A11,A-1(Byte mode) and A17~A11(Word mode) are don’t cares for unlock cycle and command cycles
DQ7~DQ0 are in hexadecimal. DQ15~DQ8 are don’t cares for unlock cycle and command cycles
Note 3. When Power supply voltage is down, Device is exit Software ID Read and Protect Verification.
Note 4. Software ID Read and Data Protection status. A10~A2,A-1 are VIL(Byte mode), A11~A2 are VIL(Word mode).
•A1,A0=0,0,
•A1,A0=0,1,
•A1,A0=1,0,
Manufactures code is “62H” in Byte mode, It is “0062H” in Word mode.
Device Code is “02H” in Byte mode, It is “0002H” in Word mode.
Block Protection: Data are “01H” in Byte mode or Data are “0001H” in Word mode
Block Unprotection: Data are “00H” in Byte mode or Data are “0000H” in Word mode
Chip Protection: Data are “01H” in Byte mode or Data are “0001H” in Word mode
•A1,A0=1,1,
Chip Unprotection: Data are “00H” in Byte mode or Data are “0000H” in Word mode
RA:Read Address, RD:Read Data, PA:Program Address, PD:Program Data,
SA:Sector Address(A17~A10), BA:Block Address(A17~A15)
Note 5,
Protected Cell Area
Byte mode Word mode
7FFFFH 3FFFFH
Byte mode Word mode
7FFFFH 3FFFFH
Block Protection
Chip Protection
16KB / 8KW
(8Sectors)
7C000H 3E000H
7BFFFH 3DFFFH
512KB / 256KW
(256Sectors)
Protect Cell Area
496KB / 248KW
(248Sectors)
00000H 00000H
00000H 00000H
SANYO Electric Co., Ltd.
7/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Absolute Maximum Ratings
Parameter
Symbol
VDD
VIN
VDQ
Pdmax
Topr
Ratings
-0.5~+4.6
-0.5~VDD+0.5
-0.5~VDD+0.5
0.7
Unit
V
V
Note
1
1,2
1,2
1,3
1
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Ambient Temperature
Storage Temperature(TSOP48)
Storage Temperature(FLGA52)
V
W
ºC
ºC
ºC
-25~+85
Tstg1
Tstg2
-65~+150
-55~+125
1
1
Note1: Stress above those listed under “Absolute Maximum Rating” may cause permanent damage to the device.
Note2: –1.0V to VDD+2.0V for the pulse less than 20ns.
Note3: Ta=25ºC
DC Operating Range 1 / Ta=-25~+85ºC
Parameter
Symbol
VDD
Min
3.0
max
3.6
Unit
V
LE28FV4101
LE28FW4101
LE28FU4101
Power Supply Voltage
VDD
2.7
3.6
V
VDD
VIL
VIL(CMOS)
VIH
2.3
3.6
V
V
V
V
V
-
-
VDD x0.2
Input Low Voltage
Input High Voltage
0.3
-
-
VDD x0.7
VDD-0.3
VIH(CMOS)
DC Operating Characteristics
Ta=-25~+85ºC, VDD=3.0V~3.6V :LE28FV4101, VDD=2.7V~3.6V :LE28FW4101, VDD=2.3V~3.6V:LE28FU4101
Limit
Symbol
Parameter
Unit
Test Condition
Min.
-
Typ.
Max.
40
CE# = OE# =VIL, WE# = VIH, all DQs open
Address inputs = VIH / VIL, at f=1/tRC
VDD=VDDMax
-
mA
Power Supply Current
(Read)
ICCR
CE# = OE# = VIL, WE# = VIH, all DQs open
Address inputs = VIH / VIL, at f=10MHz
VDD=VDDMax
25
40
mA
mA
Power Supply Current
(Write)
ICCW
ISB1
ISB2
-
-
CE# = WE# = VIL, OE# = VIH, VDD=VDDMax
-
-
-
-
-
-
-
-
-
-
-
3
mA
mA
µA
µA
µA
µA
V
CE# = RESET# = VIH, VDD=VDDMax
RESET# = VIL, VDD=VDDMax
Standby Power Supply
Current (TTL Input)
-
3
-
40
CE# = RESET# = VDD-0.3V, VDD = VDDMax
RESET# = VSS+0.3V, VDD = VDDMax
VIN = VSS ~ VDD, VDD=VDDMax
VIN = VSS ~ VDD, VDD=VDDMax
DQL = 2.0mA, VDD=VDDMin
Standby Power Supply
Current (CMOS Input)
Input Leakage Current
Output Leakage Current
-
40
ILI
-
10
ILO
-
10
-
VDD x 0.15
VOL
VOH
Output Low Voltage
Output High Voltage
µ
-
0.2V
V
DQL = 100 A, VDD=VDDMin
VDD x 0.85
VDD-0.2V
-
-
V
DQH =-2.0mA, VDD=VDDMin
DQH =-100µA, VDD=VDDMin
V
SANYO Electric Co., Ltd.
8/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Capacitance (Ta=25ºC, f=1MHz)
Parameter
Symbol
CIN
CDQ
Test Condition min typ max Unit
Input Capacitance
DQ Pin Capacitance
VIN=0V
VDQ=0V
-
-
-
-
6
12
pF
pF
Note: Sampled only, not 100% tested.
Power-up Timing
Parameter
Symbol
Limit (Min.)
200
Unit
µs
µs
Power-up to Read Operation tPU_READ
Power-up to Write Operation tPU_WRITE
200
AC Characteristics
Read Cycle Timing Parameters 1 / Ta=-25~+85ºC VDD=3.0V~3.6V: LE28FV4101
LE28FV4101
Unit
Symbol
Parameter
-40T
Max.
-50T
Max.
-70T
Min.
Min.
Min.
Max.
-
TRC
Read Cycle Time
CE# Access Time
40
-
-
40
40
30
-
50
-
-
50
50
35
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCE
70
70
35
-
TAA
TOE
Address Access Time
-
-
-
OE# Access Time
-
-
-
TCLZ
TOLZ
CE# Low to Active Output (Note1)
OE# Low to Active Output (Note1)
0
0
-
0
0
-
0
0
-
-
-
-
TCHZ CE# High to High-Z Output (Note1)
TOHZ OE# High to High-Z Output (Note1)
20
20
-
25
25
-
30
30
-
-
-
-
TOH
Output Hold Time
0
0
0
Read Cycle Timing Parameters 2 / Ta=-25~+85ºC VDD=2.7V~3.6V: LE28FW4101
LE28FW4101
Unit
Symbol
Parameter
-45T
Max.
-55T
Max.
-70T
Min.
Min.
Min.
Max.
-
TRC
Read Cycle Time
CE# Access Time
45
-
-
45
45
35
-
55
-
-
55
55
40
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCE
70
70
40
-
TAA
TOE
Address Access Time
-
-
-
OE# Access Time
-
-
-
TCLZ
TOLZ
CE# Low to Active Output (Note1)
OE# Low to Active Output (Note1)
0
0
-
0
0
-
0
0
-
-
-
-
TCHZ CE# High to High-Z Output (Note1)
TOHZ OE# High to High-Z Output (Note1)
20
20
-
25
25
-
30
30
-
-
-
-
TOH
Output Hold Time
0
0
0
Note1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
SANYO Electric Co., Ltd.
9/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Read Cycle Timing Parameters 2 / Ta=-25~+85ºC VDD=2.3~3.6V: LE28FU4101
LE28FU4101
Symbol
Parameter
-70T
Max.
-85T
Max.
-10T
Min.
Unit
Min.
Min.
Max.
-
TRC
Read Cycle Time
CE# Access Time
70
-
-
70
70
40
-
85
-
-
85
85
45
-
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCE
-
-
100
100
50
-
TAA
TOE
Address Access Time
-
-
OE# Access Time
-
-
-
TCLZ
TOLZ
CE# Low to Active Output (Note1)
OE# Low to Active Output (Note1)
0
0
-
0
0
-
0
0
-
-
-
-
TCHZ CE# High to High-Z Output (Note1)
TOHZ OE# High to High-Z Output (Note1)
30
30
-
35
35
-
40
40
-
-
-
TOH
Output Hold Time
0
0
0
-
Note1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Erase/Program Cycle Timing Parameters 1
/Ta=-25~+85ºC,VDD=3.0~3.6V: LE28FV4101 / VDD=2.7~3.6V: LE28FW4101
LE28FV/FW4101
Symbol
Parameter
-40T/-45T
Min. Max.
-50T/-55T
Min. Max.
-70T/-70T
Min. Max.
25
Unit
TSE
Sector Erase Cycle Time
-
-
25
25
100
20
20
-
-
-
25
25
100
20
20
-
-
ms
ms
ms
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
ms
ns
TBKE Block Erase Cycle Time
TCHE Chip Erase Cycle Time
-
-
25
-
-
100
TBP
Byte Program Cycle Time
-
-
-
20
TWDP Word Program Cycle Time
-
-
-
20
TAS
Address Setup Time
Address Hold Time
Chip Enable Setup Time
0
0
0
-
-
TAH
TCES
45
0
-
45
0
-
45
0
-
-
-
TCEH Chip Enable Hold Time
TWES Write Enable Setup Time
TWEH Write Enable Hold Time
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
TOES
Output Enable Setup Time
0
-
0
-
0
-
TOEH Output Enable Hold Time
0
-
0
-
0
-
TCP
CE# Write Pulse Width
WE# Write Pulse Width
Data Setup Time
50
50
30
0
-
50
50
30
0
-
50
50
30
0
-
TWP
TDS
-
-
-
-
-
-
TDH
TCPH
Data Hold Time
-
-
-
CE# High Pulse Width
30
30
500
-
-
30
30
500
-
-
30
30
500
-
-
TWPH WE# High Pulse Width
-
-
-
TRP
RESET# Pulse Width
-
-
-
TRST
TBYE
RESET# Recovery Time
Busy Enable Setup Time
10
100
-
10
100
-
10
100
-
-
-
-
TBYH Busy Enable Hold Time
50
-
50
-
50
-
Block Protection Enable Time
TBPE
TCPE
TPD
20
20
25
-
20
20
25
-
20
20
25
-
Chip Protection Enable Time
Unprotection Enable Time
-
-
-
-
-
-
TRH
Read Enable Time
100
100
100
SANYO Electric Co., Ltd.
10/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Erase/Program Cycle Timing Parameters 2 /Ta=-25~+85ºC,VDD=2.3~3.6V: LE28FU4101
LE28FU4101
Unit
ms
Symbol
Parameter
-70T
Max.
-85T
Max.
-10T
Min.
Min.
-
Min.
-
Max.
25
TSE
Sector Erase Cycle Time
25
25
-
TBKE Block Erase Cycle Time
TCHE Chip Erase Cycle Time
-
-
25
-
-
25
-
-
25
ms
ms
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
ms
ns
100
100
100
TBP
Byte Program Cycle Time
-
30
-
30
-
30
TWDP Word Program Cycle Time
-
30
-
30
-
30
TAS
Address Setup Time
Address Hold Time
Chip Enable Setup Time
0
-
-
0
-
-
0
-
-
TAH
TCES
60
0
60
0
60
0
-
-
-
TCEH Chip Enable Hold Time
TWES Write Enable Setup Time
TWEH Write Enable Hold Time
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
TOES
Output Enable Setup Time
0
-
0
-
0
-
TOEH Output Enable Hold Time
0
-
0
-
0
-
TCP
CE# Write Pulse Width
WE# Write Pulse Width
Data Setup Time
65
65
50
0
-
65
65
50
0
-
65
65
50
0
-
TWP
TDS
-
-
-
-
-
-
TDH
TCPH
Data Hold Time
-
-
-
CE# High Pulse Width
35
35
500
-
-
35
35
500
-
-
35
35
500
-
-
TWPH WE# High Pulse Width
-
-
-
TRP
RESET# Pulse Width
-
-
-
TRST
TBYE
RESET# Recovery Time
Busy Enable Setup Time
10
150
-
10
150
-
10
150
-
-
-
-
TBYH Busy Enable Hold Time
70
-
70
-
70
-
Block Protection Enable Time
TBPE
TCPE
TPD
30
30
25
-
30
30
25
-
30
30
25
-
Chip Protection Enable Time
Unprotection Enable Time
-
-
-
-
-
-
TRH
Read Enable Time
150
150
150
Note) All the effective input levels are should be kept during above setup or hold time.
AC Test Condition
Input Pulse Levels
VIL=VDD x0.1
5ns
/
VIH=VDD x0.9
1/2 x VDD
Input Rise/Fall Time
Input and Output timing Reference Levels
VDD
Output Load
1.25K
Output PIN
0.75K
30pF
SANYO Electric Co., Ltd.
11/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Timing Diagram
Figure 3: Read Cycle (Byte Mode: BYTE#=”L”)
TRC
A17~A-1
TCE
CE#
TAA
TOE
OE#
TOHZ
TOLZ
WE#
TCLZ
TOH
TCHZ
DATA VALID
DATA VALID
DQ7~0
High-Z
DQ14~8
Figure 4: Read Cycle (Word Mode: BYTE#=”H”)
TRC
A17~A0
TCE
CE#
TAA
TOE
OE#
TOHZ
TOLZ
WE#
TCLZ
TCHZ
TOH
DATA VALID
DATA VALID
DQ7~0
DATA VALID
DATA VALID
DQ15~8
SANYO Electric Co., Ltd.
12/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 5: CE# Controlled Write Timing (Byte Mode: BYTE#=”L”)
TAS
TAH
A17~A-1
CE#
TCP
TCPH
TOEH
TOES
OE#
TWEH
TWES
WE#
TDS
TDH
DATA VALID
DQ7~0
High-Z
DQ14~8
Figure 6: CE# Controlled Write Timing (Word Mode: BYTE#=”H”)
TAH
TAS
A17~0
CE#
TCP
TCPH
TOEH
TOES
OE#
TWEH
TWES
WE#
TDS
TDH
DATA VALID
DQ7~0
DATA VALID
DQ15~8
SANYO Electric Co., Ltd.
13/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 7: WE# Controlled Write Timing (Byte Mode: BYTE#=”L”)
TAS
TAH
A17~A-1
CE#
TCEH
TCES
TOES
TOEH
OE#
TWPH
TWP
WE#
TDH
DATA VALID
TDS
DQ7~0
High-Z
DQ14~8
Figure 8: WE# Controlled Write Timing (Word Mode: BYTE#=”H”)
TAH
TAS
A17~A0
CE#
TCES
TCEH
TOEH
TOES
OE#
TWPH
TWP
WE#
TDS
TDH
DATA VALID
DQ7~0
DQ15~8
DATA VALID
SANYO Electric Co., Ltd.
14/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 9: Read / Reset 1 (Byte Mode: BYTE#=”L”)
Read Mode
A17~A-1
CE#
OE#
TRST
TRH
(Recovery Time for Interupt from Erase cycle or Program cycle)
(Recovery Time for Exit from ID Entry or Verify Protect)
WE#
High-Z
High-Z
DQ7~ DQ0
F0
DQ14~8
Figure 10: Read / Reset 1 (Word Mode: BYTE#=”H”)
Read Mode
A17~A0
CE#
TRST
(Recovery Time for Interupt from Erase cycle or Program cycle)
OE#
TRH
(Recovery Time for Exit from ID Entry or Verify Protect)
WE#
High-Z
High-Z
F0
DQ7~ DQ0
DQ15~8
SANYO Electric Co., Ltd.
15/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 11: Read / Reset 2 (Byte Mode: BYTE#=”L”)
Read Mode
AAA
A17~A-1
555
AAA
CE#
OE#
TRST
TRH
(Recovery Time for Interupt from Erase cycle or Program cycle)
(Recovery Time for Exit from ID Entry or Verify Protect)
WE#
DQ7~ DQ0
High-Z
High-Z
AA
F0
55
DQ14~8
Figure 12: Read / Reset 2 (Word Mode: BYTE#=”H”)
Read Mode
2AA
555
555
A17~A0
CE#
OE#
TRST
TRH
(Recovery Time for Interupt from Erase cycle or Program cycle)
(Recovery Time for Exit from ID Entry or Verify Protect)
WE#
High-Z
High-Z
AA
F0
55
DQ7~ DQ0
DQ15~8
SANYO Electric Co., Ltd.
16/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 13: Erase Command Sequence of WE# Control (Byte Mode: BYTE#=”L”)
(Under Erasing)
TSE/TBKE/TCHE
AAA
TAH
AAA
SA/BA/AAA
A17~A-1
555
555
AAA
TAS
CE#
OE#
TWP
TWPH
WE#
TDH
30/50/10
TDS
DQ7~0
AA
80
55
AA
55
High-Z
DQ14~8
Figure 14: Erase Command Sequence of WE# Control (Word Mode: BYTE#=”H”)
(Under Erasing)
TSE,TBKE,TCHE
SA/BA/555
A17~A0
CE#
2AA
555
TAH
555
555
2AA
TAS
OE#
TWPH
TWP
WE#
TDS TDH
30/50/10
DQ7~0
AA
80
55
AA
55
DQ15~8
SANYO Electric Co., Ltd.
17/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 15: Erase Command Sequence of CE# Control (Byte Mode: BYTE#=”L”)
(Under Erasing)
TSE,TBKE,TCHE
AAA
TAH
AAA
SA/BA/AAA
A17~A-1
555
555
AAA
TAS
WE#
OE#
TCPH
TCP
CE#
TDH
30/50/10
TDS
DQ7~0
AA
80
55
AA
55
High-Z
DQ14~8
Figure 16: Erase Command Sequence of CE# Control (Word Mode: BYTE#=”H”)
(Under Erasing)
TSE,TBKE,TCHE
SA/BA/555
A17~A0
2AA
555
TAH
555
555
2AA
TAS
WE#
OE#
TCP
TCPH
CE#
TDS TDH
30/50/10
DQ7~0
AA
80
55
AA
55
DQ15~8
SANYO Electric Co., Ltd.
18/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 17: Program Command Sequence of CE# Control (Byte Mode: BYTE#=”L”)
(Under Programing)
TBP
555
ADDR.
A17~A-1
AAA
TAH
AAA
TAS
TCPH
TCP
CE#
OE#
WE#
TDH
TDS
DQ7~0
AA
A0
55
DATA
High-Z
DQ14~8
Figure 18: Program Command Sequence of CE# Control (Word Mode: BYTE#=”H”)
(Under Programing)
TWDP
ADDR.
A17~A0
555
2AA
555
TAS
TAH
TCP
TCPH
CE#
OE#
WE#
TDS TDH
DATA
DQ7~0
AA
A0
55
DQ15~8
DATA
SANYO Electric Co., Ltd.
19/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 19: Program Command Sequence of WE# Control (Byte Mode: BYTE#=”L”)
(Under Programming)
TBP
ADDR.
A17~A-1
AAA
TAH
555
AAA
TAS
TWPH
TWP
WE#
OE#
CE#
TDH
DATA
High-Z
TDS
DQ7~0
AA
A0
55
DQ14~8
Figure 20: Program Command Sequence of WE# Control (Word Mode: BYTE#=”H”)
(Under Programming)
TWDP
ADDR.
A17~A0
555
2AA
555
TAH
TAS
TWPH
TWP
WE#
OE#
CE#
TDH
DATA
TDS
DQ7~0
AA
A0
55
DQ15~8
DATA
SANYO Electric Co., Ltd.
20/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 21: Write Protect / Unprotect Sequence (Byte Mode: BYTE#=”L”)
(Under Protct / Unprotect)
TBPE,TCPE,TPD
AAA
555
A17~A-1
AAA
CE#
OE#
WE#
DQ7~0
AA
E0/D0/E0
00/00/01
High-Z
55
DQ14~8
Figure 22: Write Protect / Unprotect Sequence (Word Mode: BYTE#=”H”)
(Under Protect / Unprotect)
TBPE,TCPE,TPD
A17~A0
555
2AA
555
CE#
OE#
WE#
DQ7~0
AA
E0/D0/E0
00/00/01
55
DQ15~8
SANYO Electric Co., Ltd.
21/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 23: Software ID / Protect Verify Sequence (Byte Mode: BYTE#=”L”)
AAA
555
002
004
006
A17~A-1
000
AAA
CE#
OE#
TRH
WE#
(Device code)
02
(Chip Unprotect/Protect)
00/01
00/01
TAA
DQ7~0
High-Z
High-Z
62
AA
90
55
(Manufacture code)
(Block Unprotect/Protect)
DQ14~8
Figure 24: Software ID / Protect Verify Sequence (Word Mode: BYTE#=”H”)
001
002
003
555
2AA
000
555
A17~A0
CE#
OE#
TRH
WE#
(Device code)
02
(Chip Unprotect/Protect)
00/01
00/01
TAA
62
AA
90
55
DQ7~0
(Manufacture code)
00
(Block Unprotect/Protect)
High-Z
DQ15~8
00
00/00
00/00
SANYO Electric Co., Ltd.
22/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 25: Hardware Reset Timing
Read mode or Standby
A17~A-1
(A17~A0)
TRST
RESET#
TRP
TRH
Note: Device is in standby mode when RESET# is “L”
Figure 26: RD/BY# Timing(Write to Read)
A17~A-1
(A17~A0)
Under Erasing or
Programming
WE#
TBYE
TBYH
RD/BY#
Figure 27: RD/BY# Timing(Write to Write)
CE#
Under Erasing
Programming
WE#
TBYH
TBYE
RD/BY#
SANYO Electric Co., Ltd.
23/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Figure 28: DATA# Polling Timing(DQ7)
Note
A17~A-1
(A17~0)
TCE
CE#
OE#
TOE
WE#
DATA
DATA#
DATA#
DATA
DQ7
Figure 29: Toggle Bit Timing(DQ6)
Note
A17~A-1
(A17~0)
TCE
CE#
OE#
TOE
WE#
Two Read Cycle With Same Outpurt Data
DQ6
DATA
DATA
DATA
DATA#
Note: This time interval signal can be TBP, TWDP, TSE, TBKE, TCPE depending upon the selected operation mode.
SANYO Electric Co., Ltd.
24/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Flowchart
Start
Start
Sector Erase Command
(1st ~ 5th)
Block Erase Command
(1st ~ 5th)
Sector Erase Command(6th)
(Load Sector Address)
Block Erase Command(6th)
(Load Block Address)
Erase End Detection
Erase End Detection
Sector Erase Complete
Block Erase Complete
Figure 30: Sector Erase Flowchart
Figure 31: Block Erase Flowchart
Start
Start
Chip Erase Command
(1st ~ 6th)
Program Command
(1st ~ 3rd)
Program Command(4th)
(Load Add. and Data)
Erase End Detection
Program End Detection
Chip Erase Complete
Figure 32: Chip Erase Flowchart
Program Complete
Figure 33: Byte/Word Program Flowchart
SANYO Electric Co., Ltd.
25/26
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Preliminary Specification
Internal Timer
Toggle Bit
DATA# Polling
Erase/Program
Start
Erase/Program
Start
Erase/Program
Start
Wait time
(TBP,TWDP,TSE,
TBKE,TCPE)
Read Word
Read DQ7
Erase/Program
End
NO
Is DQ7=
True Data?
Read Same Word
YES
NO
Does DQ6
Much?
Erase/Program
End
YES
Erase/Program
End
Figure 34: Erase/Program End Detection Flowchart
1. No products described or contained herein are intended for use in surgical implants, life-support systems aerospace equipment ,
nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, then failure of which may directly or indirectly cause
injury, death or property loss.
2. Anyone purchasing any products described or contained herein for an above-mentioned use shall:
a) Accept full responsibility and indemnify and defend SANYO ELECTRIC CO.,LTD., its affiliates, subsidiaries and distributors and all their
officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with
such use:
b) Not impose any responsibility for any fault or negligence, which may be cited in any such claim or litigation on SANYO
ELECTRIC CO., LTD., its affiliates, subsidiaries and distributor or any of their officers and employees jointly or sever ally.
3. Information (including circuit diagrams and circuit parameter) herein in for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or
any infringement of intellectual property rights or other rights of third parties.
SANYO Electric Co., Ltd.
26/26
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