LM555CM [ONSEMI]
单计时器;
| 型号： | LM555CM |
| 厂家： | 
ONSEMI |
| 描述： | 单计时器 PC 光电二极管 |
| 文件： | 总15页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2013
LM555
Single Timer
Description
Features
The LM555 is a highly stable controller capable of pro-
ducing accurate timing pulses. With a monostable opera-
tion, the delay is controlled by one external resistor and
one capacitor. With astable operation, the frequency and
duty cycle are accurately controlled by two external
resistors and one capacitor.
• High-Current Drive Capability: 200 mA
• Adjustable Duty Cycle
• Temperature Stability of 0.005%/°C
• Timing From μs to Hours
• Turn off Time Less Than 2 μs
8-DIP
Applications
• Precision Timing
• Pulse Generation
• Delay Generation
• Sequential Timing
1
8-SOIC
1
Ordering Information
Part Number Operating Temperature Range
Top Mark
LM555CN
LM555CM
LM555CM
Package
DIP 8L
Packing Method
LM555CN
Rail
Rail
LM555CM
0 ~ +70°C
SOIC 8L
SOIC 8L
LM555CMX
Tape & Reel
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
1
Block Diagram
R
R
R
1
2
3
4
8
7
6
5
V
CC
GND
Comp.
Discharging Transistor
Trigger
Discharge
OutPut
Stage
Output
Threshold
F/F
Comp.
Controld
Reset
Voltage
VREF
Figure 1. Block Diagram
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.
Symbol
VCC
Parameter
Value
16
Unit
V
Supply Voltage
TLEAD
PD
Lead Temperature (Soldering 10s)
Power Dissipation
300
°C
600
mW
°C
TOPR
TSTG
Operating Temperature Range
Storage Temperature Range
0 ~ +70
-65 ~ +150
°C
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
2
Electrical Characteristics
Values are at TA = 25°C, VCC = 5 ~ 15 V unless otherwise specified.
Parameter
Symbol
Conditions
Min.
Typ. Max.
Unit
V
Supply Voltage
VCC
4.5
16.0
VCC = 5 V, RL = ∞
3
6
mA
mA
Supply Current (Low Stable) (1)
ICC
VCC = 15 V, RL = ∞
7.5
15.0
Timing Error (Monostable)
Initial Accuracy (2)
Drift with Temperature (3)
Drift with Supply Voltage (3)
ACCUR
1.0
3.0
%
RA = 1 kΩ to100 kΩ
C = 0.1 μF
Δt / ΔT
50
ppm / °C
% / V
Δt / ΔVCC
0.1
0.5
Timing Error (Astable)
InItial Accuracy (2)
Drift with Temperature (3)
Drift with Supply Voltage (3)
ACCUR
2.25
%
RA = 1 kΩ to 100kΩ
C = 0.1 μF
Δt / ΔT
150
0.3
ppm / °C
Δt / ΔVCC
% / V
V
VCC = 15 V
VCC = 5 V
VCC = 15 V
VCC = 5V
9.0
10.0
3.33
10.0
3.33
0.10
1.67
5.0
11.0
4.00
Control Voltage
VC
2.60
V
V
Threshold Voltage
Threshold Current (4)
Trigger Voltage
VTH
ITH
V
0.25
2.20
5.6
μA
V
VCC = 5 V
VCC = 15 V
VTR = 0 V
1.10
4.5
VTR
V
Trigger Current
Reset Voltage
Reset Current
ITR
0.01
0.7
2.00
1.0
μA
V
VRST
IRST
0.4
0.1
0.4
mA
V
ISINK = 10 mA
0.06
0.30
0.05
12.5
0.25
0.75
0.35
VCC = 15 V
Low Output Voltage
VOL
ISINK = 50 mA
VCC = 5 V, ISINK = 5 mA
ISOURCE = 200 mA
V
V
V
VCC = 15 V
High Output Voltage
VOH
ISOURCE = 100 mA 12.75 13.30
V
VCC = 5 V, ISOURCE = 100 mA
2.75
3.30
100
100
20
V
Rise Time of Output(3)
Fall Time of Output(3)
Discharge Leakage Current
Notes:
tR
tF
ns
ns
nA
ILKG
100
1. When the output is high, the supply current is typically 1 mA less than at VCC = 5 V.
2. Tested at VCC = 5.0 V and VCC = 15 V.
3. These parameters, although guaranteed, are not 100% tested in production.
4. This determines the maximum value of RA + RB for 15 V operation, the maximum total R = 20 MΩ, and for 5 V
operation, the maximum total R = 6.7 MΩ.
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
3
Application Information
Table 1 below is the basic operating table of 555 timer.
Table 1. Basic Operating Table
Discharging
Transistor
(PIN 7)
Reset
(PIN 4)
VTR
(PIN 2)
VTH
(PIN 6)
Output
(PIN 3)
Low
High
High
High
X
X
Low
High
Low
ON
OFF
ON
< 1/3 VCC
> 1/3 VCC
> 1/3 VCC
X
> 2/3 VCC
< 2/3 VCC
Previous State
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold volt-
age or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes accord-
ing to threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal dis-
charge transistor turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer
output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply volt-
age, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output
again at high.
1. Monostable Operation
102
+Vcc
RA
4
101
100
8
RESET
Vcc
Trigger
7
6
DISCH
TRIG
OUT
2
3
10-1
10-2
10-3
THRES
CONT
C1
5
GND
RL
C2
1
10-5
10-4
10-3
10-2
10-1
100
101
102
Time Delay(s)
Figure2. Monostable Circuit
Figure 3. Resistance and Capacitance vs.
Time Delay (tD)
Figure 4. Waveforms of Monostable Operation
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
4
1. Monostable Operation
Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage
falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low,
the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging
the external capacitor C1 and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t = RA*C and
reaches 2 VCC/3 at tD = 1.1 RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant
RAC, the longer it takes for the VC1 to reach 2 VCC/3. In other words, the time constant RAC controls the output pulse
width.
When the applied voltage to the capacitor C1 reaches 2 VCC/3, the comparator on the trigger terminal resets the flip-
flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela-
tionship based on RA and C. Figure 4 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of VCC/3 before
the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied
while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at
the end of the output pulse remains at below VCC/3. Figure 5 shows such a timer output abnormality.
Figure 5. Waveforms of Monostable Operation
(abnormal)
2. Astable Operation
+Vcc
100
(RA+2RB)
RA
4
8
10
1
RESET
Vcc
7
6
DISCH
TRIG
OUT
2
3
RB
THRES
CONT
0.1
C1
0.01
5
GND
RL
C2
1
1E-3
100m
1
10
100
1k
10k
100k
Frequency(Hz)
Figure 6. A Stable Circuit
Figure 7. Capacitance and Resistance vs. Frequency
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
5
Figure 8. Waveforms of Astable Operation
An astable timer operation is achieved by adding resistor RB to Figure 2 and configuring as shown on Figure 6. In the
astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operat-
ing as a multi-vibrator. When the timer output is high, its internal discharging transistor. turns off and the VC1 increases
by exponential function with the time constant (RA+RB)*C.
When the VC1, or the threshold voltage, reaches 2 VCC/3; the comparator output on the trigger terminal becomes
high, resetting the F/F and causing the timer output to become low. This turns on the discharging transistor and the C1
discharges through the discharging channel formed by RB and the discharging transistor. When the VC1 falls below
VCC/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The dis-
charging transistor turns off and the VC1 rises again.
In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from VCC/3 to 2
VCC/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2 VCC/3 to VCC/3.
When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:
RA
RB
Vcc
C1
Vc1(0-)=Vcc/3
dv
V
– V(0-)
cc
c1
C ------------- = -------------------------------
(1)
(2)
1
dt
R
+ R
A
B
V
(0+) = V
⁄ 3
C1
CC
t
------------------------------------
- –
(R + R )C1
A
B
2
3
V
(t) = V
1 – --e
(3)
C1
CC
Since the duration of the timer output high state (tL) is the amount of time it takes for the VC1(t) to reach 2 VCC/3,
t
H
------------------------------------
- –
(R + R )C1
A
B
2
3
2
3
V
(t) = --V
= V
1 – --e
(4)
C1
CC
CC
t
= C (R + R )In2 = 0.693(R + R )C
1
(5)
H
1
A
B
A
B
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
6
The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:
RB
C1
VC1(0-)=2Vcc/3
RD
dv
C1
1
C -------------- + ----------------------- V
= 0
(6)
1
C1
t
dt
R + R
A
B
-------------------------------------
(R + R )C1
A
D
2
3
V
(t) = --V
(7)
C1
e
CC
Since the duration of the timer output low state (tL) is the amount of time it takes for the VC1(t) to reach VCC/3,
t
L
------------------------------------
-
(R + R )C 1
A
D
1
3
2
3
-- V
= --- V
(8 )
C C
e
C C
t
= C (R + R )In2 = 0.693 (R + R )C
1
(9 )
L
1
B
D
B
D
Since RD is normally RB>>RD although related to the size of discharging transistor,
tL = 0.693RBC1 (10)
Consquently, if the timer operates in astable, the period is the same with
't = tH+tL = 0.693(RA+RB)C1+0.693RBC1 = 0.693(RA+2RB)C1'
because the period is the sum of the charge time and discharge time. Since frequency is the reciprocal of the period,
the following applies:
1
1.44
f = -- = ---------------------------------------
(R + 2R )C
frequency,
(11)
t
A
B
1
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
7
3. Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider.
Figure 9. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing
cycle.
Figure 9. Waveforms of Frequency Divider Operation
4. Pulse Width Modulation
The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and chang-
ing the reference of the timer's internal comparators. Figure 10 illustrates the pulse width modulation circuit.
When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated accord-
ing to the signal applied to the control terminal. Sine wave, as well as other waveforms, may be applied as a signal to
the control terminal. Figure 11 shows the example of pulse width modulation waveform.
+Vcc
R
A
4
8
RESET
Vcc
7
6
5
Trigger
Output
DISCH
TRIG
2
3
THRES
CONT
OUT
Input
C
GND
1
Figure 10. Circuit for Pulse Width Modulation
Figure 11. Waveforms of Pulse Width Modulation
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
8
5. Pulse Position Modulation
If the modulating signal is applied to the control terminal while the timer is connected for the astable operation, as in
Figure 12, the timer becomes a pulse position modulator.
In the pulse position modulator, the reference of the timer's internal comparators is modulated, which modulates the
timer output according to the modulation signal applied to the control terminal.
Figure 13 illustrates a sine wave for modulation signal and the resulting output pulse position modulation; however, any
wave shape be used.
+Vcc
R
A
4
8
RESET
Vcc
7
6
5
DISCH
TRIG
2
3
R
C
B
THRES
CONT
Output
OUT
Modulation
GND
1
Figure 13. Wafeforms of pulse position modulation
Figure 12. Circuit for Pulse Position Modluation
6. Linear Ramp
When the pull-up resistor RA in the monostable circuit shown in Figure 2 is replaced with constant current source, the
C1 increases linearly, generating a linear ramp. Figure 14 shows the linear ramp generating circuit and Figure 15 illus-
trates the generated linear ramp waveforms.
V
+Vcc
R1
RE
4
8
RESET
Vcc
7
6
DISCH
Q1
TRIG
OUT
2
3
R2
THRES
CONT
Output
C1
5
GND
C2
1
Figure 15. Waveforms of Linear Ramp
Figure 14. Circuit for Linear Ramp
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
9
In Figure 14, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.
V
– V
CC
E
I
= --------------------------
(12)
C
R
E
Here, V
E is
R
2
V
= V
+ ---------------------V
(13)
E
BE
CC
R + R
1
2
For example, if VCC = 15 V, RE = 20 kΩ, R1 = 5 kΩ, R2 = 10 kΩ, and VBE = 0.7 V,
VE=0.7 V+10 V=10.7 V, and
IC=(15-10.7) / 20 k=0.215 mA.
When the trigger starts in a timer configured as shown in Figure 14, the current flowing through capacitor C1 becomes
a constant current generated by PNP transistor and resistors.
Hence, the VC is a linear ramp function as shown in Figure 15. The gradient S of the linear ramp function is defined as
follows:
V
p – p
S = ----------------
(14)
t
Here the Vp-p is the peak-to-peak voltage.
If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:
V = Q/C
(15)
The above equation divided on both sides by t gives:
Q § t
C
V
--- = -------------
(16)
t
and may be simplified into the following equation:
S = I/C (17)
In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the
constant current flowing through the capacitor.
If the constant current flow through the capacitor is 0.215 mA and the capacitance is 0.02 μF, the gradient of the ramp
function at both ends of the capacitor is S = 0.215 m / 0.022 μ = 9.77 V/ms.
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
10
Physical Dimensions
8-DIP
.400 10.15
A
.373 9.46
[ ]
.036 [0.9 TYP]
(.092) [Ø2.337]
PIN #1
(.032) [R0.813]
.250 .005 [6.35 0.13]
PIN #1
B
TOP VIEW
OPTION 1
TOP VIEW
OPTION 2
.070 1.78
.310 .010 [7.87 0.25]
.045
[ ]
1.14
.130 .005 [3.3 0.13]
.210 MAX
[5.33]
7° TYP
7° TYP
C
.015 MIN
[0.38]
.021 0.53
.300
.015 0.37
[ ]
.140 3.55
[7.62]
.125 [3.17]
.001[.025]
C
.100
[2.54]
.430 MAX
[10.92]
.060 MAX
[1.52]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
+.005
+0.127
0.254
-0.000
.010
-.000
[
]
B. CONTROLING DIMENSIONS ARE IN INCHES
REFERENCE DIMENSIONS ARE IN MILLIMETERS
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
N08EREVG
Figure 16. 8-Lead, DIP, JEDEC MS-001, 300" WIDE
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/products/discrete/pdf/8dip_tr.pdf.
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
11
Physical Dimensions (continued)
8-SOIC
Figure 17. 8-Lead, SOIC,JEDEC MS-012, 150" NARROW BODY
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/dwg/M0/M08A.pdf.
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
12
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intended to be an exhaustive list of all such trademarks.
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Saving our world, 1mW/W/kW at a time™
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and Better™
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TranSiC¥
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®
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®
*
®
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accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,
under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors
are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical
and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise.
Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global
problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Preliminary
No Identification Needed
Obsolete
First Production
Full Production
Not In Production
Rev. I63
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