LMV358AM8X [ONSEMI]
超低成本和功耗，轨对轨输出，双路运算放大器;
| 型号： | LMV358AM8X |
| 厂家： | 
ONSEMI |
| 描述： | 超低成本和功耗，轨对轨输出，双路运算放大器 放大器 PC 光电二极管 运算放大器 |
| 文件： | 总20页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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LMV321 / LMV358 / LMV324
General-Purpose, Low Voltage, Rail-to-Rail Output
Amplifiers
Description
Features at +2.7V
The LMV321 (single), LMV358 (dual), and LMV324
(quad) are a low cost, voltage feedback amplifiers that
consume only 80 μA of supply current per amplifier. The
LMV3XX family is designed to operate from 2.7 V (±1.35
V) to 5.5 V (±2.75 V) supplies. The common mode volt-
age range extends below the negative rail and the output
provides rail-to-rail performance.
• 80 μA Supply Current per Channel
• 1.2 MHz Gain Bandwidth Product
• Output Voltage Range: 0.01 V to 2.69 V
• Input Voltage Range: -0.25 V to +1.5 V
• 1.5 V/μs Slew Rate
• LMV321 Directly Replaces Other Industry Standard
LMV321 Amplifiers: Available in SC70-5 and
SOT23-5 Packages
The LMV3XX family is designed on a CMOS process
and provides 1.2 MHz of bandwidth and 1.5 V/μs of slew
rate at a low supply voltage of 2.7 V. The combination of
low power, rail-to-rail performance, low voltage opera-
tion, and tiny pack-age options make the LMV3XX family
well suited for use in personal electronics equipment
such as cellular handsets, pagers, PDAs, and other bat-
tery powered applications.
• LMV358 Directly Replaces Other Industry Standard
LMV358 Amplifiers: Available in MSOP-8 and
SOIC-8 Packages
• LMV324 Directly Replaces Other Industry Standard
LMV324 Amplifiers: Available in SOIC-14 Packages
• Fully Specified at +2.7 V and +5 V Supplies
• Operating Temperature Range: -40°C to +125°C
Frequency Response vs. C
L
C
= 200pF
C
R
= 200pF
= 225Ω
L
L
s
R
= 0
s
Applications
C
R
= 100pF
= 0
• Low Cost General-Purpose Applications
• Cellular Phones
L
s
C
= 50pF
L
R
= 0
s
C
R
= 10pF
= 0
L
s
C
= 20pF
L
• Personal Data Assistants
• A/D Buffer
R
= 0
s
C
R
= 2pF
L
+
-
Rs
= 0
s
• DSP Interface
CL 2kΩ
10kΩ
10kΩ
• Smart Card Readers
• Portable Test Instruments
• Keyless Entry
0.01
0.1
1
10
Frequency (MHz)
• Infrared Receivers for Remote Controls
• Telephone Systems
• Audio Applications
Typical Application
+Vs
6.8μF
• Digital Still Cameras
• Hard Disk Drives
+
• MP3 Players
0.01μF
+In
+
Out
LMV3XX
-
Rf
Rg
© 2002 Semiconductor Components Industries, LLC.
Publication Order Number:
LMV358/D
November-2017, Rev. 3
Ordering Information
Product Number
LMV321AP5X
Package
SC70 5L
Packing Method
Tape and Reel, 3000pcs
Tape and Reel, 3000pcs
Tape and Reel, 2500pcs
Tape and Reel, 3000pcs
Tape and Reel, 2500pcs
Operating Temperature
LMV321AS5X
SOT-23 5L
SOIC 8L (Narrow)
MSOP 8L
LMV358AM8X
LMV358AMU8X
LMV324AM14X
-40 to +125°C
SOIC 14L
Pin Assignments
LMV321
SOT23-5
SC70-5
+In
-Vs
-In
1
2
3
5
4
+Vs
+In
-Vs
-In
1
2
3
5
4
+Vs
Out
+
–
+
–
Out
LMV358
SOIC-8
MSOP-8
Out1
-In1
+In1
-Vs
1
8
+Vs
Out1
-In1
+In1
-Vs
1
2
3
4
8
7
6
5
+Vs
Out2
-In2
+In2
2
3
4
7
6
5
Out2
-In2
+In2
-
-
+
+
-
-
+
+
LMV324
SOIC-14
Out1
-In1
1
2
3
4
5
6
7
14 Out4
-In4
-
13
-
+
+
+In1
+Vs
12 +In4
11
10
9
-Vs
+
-
+
+In2
-In2
+In3
-In3
Out3
-
8
Out2
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2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Parameter
Min.
Max.
+6
Unit
V
Supply Voltage
0
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature, 10 Seconds
Input Voltage Range
-
-65
+175
°C
°C
°C
V
+150
-
+260
-VS -0.5
+VS +0.5
Recommended Operating Conditions
Parameter
Operating Temperature Range
Min.
-40
Max.
+125
5.5
Unit
°C
Power Supply Operating Range
2.5
V
Package Thermal Resistance
Package
5 Lead SC70
θJA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
331.4
256
152
206
88
5 Lead SOT23
8 Lead SOIC
8 Lead MSOP
14 Lead SOIC
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3
Electrical Specifications
TC = 25°C, VS = +2.7 V, G = 2, RL = 10 kΩ to VS/2, Rf = 10 kΩ, VO(DC) = VCC/2, unless otherwise noted.
Parameter
AC Performance
Conditions
Min.
Typ.
Max.
Unit
Gain Bandwidth Product
Phase Margin
CL= 50 pF, RL= 2 kΩ to VS/2
1.2
52
17
1.5
36
91
80
MHz
deg
Gain Margin
dB
Slew Rate
VO = 1VPP
>50 kHz
V/μs
nV/√Hz
Input Voltage Noise
LMV358 100 kHz
LMV324 100 kHz
Crosstalk
dB
DC Performance
Input Offset Voltage(1)
Average Drift
Input Bias Current(2)
Input Offset Current(2)
Power Supply Rejection Ratio(1)
Supply Current (Per Channel)(1)
Input Characteristics
1.7
8
7.0
mV
μV/°C
nA
<1
<1
65
80
nA
DC
50
dB
120
1.3
μA
LO
HI
0
-0.25
1.5
Input Common Mode Voltage Range(1)
V
Common Mode Rejection Ratio(1)
50
70
dB
Output Characteristics
RL= 10 kΩ to VS/2; LO(1)
RL= 10 kΩ to VS/2; HI(1)
0.01
2.69
0.10
Output Voltage Swing
V
2.60
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality
levels are determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25°C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1 nA. CMOS leakage is too small to
practically measure.
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Electrical Specifications (Continued)
TC = 25°C, VS = +5 V, G = 2, RL = 10 kΩ to VS/2, Rf = 10 kΩ, VO(DC) = VCC/2, unless otherwise noted.
Parameter
AC Performance
Conditions
Min.
Typ.
Max.
Unit
Gain Bandwidth Product
Phase Margin
CL= 50 pF, RL= 2 kΩ to VS/2
1.4
73
12
1.5
33
91
80
MHz
deg
Gain Margin
dB
Slew Rate
V/μs
nV/√Hz
dB
Input Voltage Noise
>50 kHz
LMV358 100 kHz
LMV324 100 kHz
Crosstalk
dB
DC Performance
Input Offset Voltage(3)
Average Drift
Input Bias Current(4)
Input Offset Current(4)
Power Supply Rejection Ratio(3)
Open Loop Gain(3)
Supply Current (Per Channel)(3)
1
6
7
mV
μV/°C
nA
<1
<1
65
70
100
nA
DC
50
50
dB
dB
150
3.6
μA
Input Characteristics
LO
HI
0
-0.4
3.8
75
V
V
Input Common Mode Voltage Range(3)
Common Mode Rejection Ratio(3)
50
dB
Output Characteristics
0.036 to
4.950
RL= 2 kΩ to VS/2; LO/HI
V
Output Voltage Swing
RL= 10 kΩ to VS/2; LO(3)
RL= 10 kΩ to VS/2; HI(3)
Sourcing; VO = 0 V
0.013
4.98
+34
0.100
V
V
4.90
5
mA
mA
Short Circuit Output Current(3)
Sinking; VO = 5 V
10
-23
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality
levels are determined from tested parameters.
Notes:
3. Guaranteed by testing or statistical analysis at +25°C.
4. +IN and -IN are gates to CMOS transistors with typical input bias current of <1 nA. CMOS leakage is too small to
practically measure.
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5
Typical Operating Characteristics
TC = 25°C, VS = +5 V, G = 2, RL = 10 kΩ to VS/2, Rf = 10 kΩ, VO(DC) = VCC/2, unless otherwise noted.
Non-Inverting Freq. Response V = +5V
Inverting Frequency Response V = +5V
s
s
G = 2
G = 1
G = -2
G = -1
G = 10
G = -10
G = -5
G = 5
0.01
0.1
1
10
0.01
0.1
1
10
10
10
Frequency (MHz)
Frequency (MHz)
Non-Inverting Freq. Response V = +2.7V
s
Inverting Freq. Response V = +2.7V
s
G = 1
G = 2
G = -1
G = -2
G = 10
G = -10
G = 5
G = -5
0.01
0.1
1
10
0.01
0.1
1
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
C
= 200pF
R
C
R
= 200pF
= 225Ω
L
L
s
= 0
s
C
R
= 100pF
= 0
L
s
R
= 100kΩ
R
= 1kΩ
L
L
C
= 50pF
= 0
L
R
s
C
R
= 10pF
= 0
L
s
C
= 20pF
R
L
R
= 10kΩ
= 0
L
s
C
R
= 2pF
L
+
-
Rs
= 0
s
R
= 2kΩ
L
CL 2kΩ
10kΩ
10kΩ
0.01
0.1
1
10
0.01
0.1
1
Frequency (MHz)
Frequency (MHz)
Small Signal Pulse Response
Large Signal Pulse Response
0.25
0.2
2.5
2
0.15
0.1
1.5
0.1
0.5
0
0.05
0
-0.05
-0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
Time (μs)
Time (μs)
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6
Typical Operating Characteristics (Continued)
TC = 25°C, VS = +5 V, G = 2, RL = 10 kΩ to VS/2, Rf = 10 kΩ, VO(DC) = VCC/2, unless otherwise noted.
Input Voltage Noise
Total Harmonic Distortion
100
80
70
60
50
40
30
20
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 1V
pp
o
1
10
100
0.1
1000
1
10
100
Frequency (kHz)
Frequency (kHz)
Open Loop Gain & Phase vs. Frequency
0
100
80
60
40
20
0
R
L
= 2kΩ
L
C
= 50pF
-45
-90
Phase
-135
-180
-225
-270
|Gain|
-20
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
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7
Application Information
General Description
+
The LMV3XX family are single supply, general-purpose,
voltage-feedback amplifiers that are pin-for-pin compati-
ble and drop in replacements with other industry standard
LMV321, LMV358, and LMV324 amplifiers. The LMV3XX
family is fabricated on a CMOS process, features a rail-
to-rail output, and is unity gain stable.
Rs
LMV3XX
-
CL 2kΩ
10kΩ
10kΩ
The typical non-inverting circuit schematic is shown in
Figure1.
Figure 2. Typical Topology for driving a capacitive
load
+Vs
6.8μF
+
3
2
1
0
0.01μF
+In
C
= 50pF
s
L
-1
-2
-3
-4
-5
-6
-7
-8
-9
+
R
= 0
Out
LMV3XX
C
= 100pF
s
L
R
= 400Ω
-
C
= 200pF
s
L
Rf
R
= 450Ω
Rg
0.01
0.1
1
10
Frequency (MHz)
Figure 1. Typical Non-inverting configuration
Power Dissipation
Figure 3. Frequency Response vs. CL for unity gain
configuration
The maximum internal power dissipation allowed is di-
rectly related to the maximum junction temperature. If the
maximum junction temperature exceeds 150°C, some
performance degradation will occur. If the maximum junc-
tion temperature exceeds 175°C for an extended time,
device failure may occur.
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. ON Semiconductor has
evaluation boards to use as a guide for high frequency
layout and as aid in device testing and characterization.
Follow the steps below as a basis for high frequency
layout:
Driving Capacitive Loads
The Frequency Response vs. CL plot on page 4, illus-
• Include 6.8 μF and 0.01 μF ceramic capacitors
• Place the 6.8 μF capacitor within 0.75 inches of the
power pin
trates the response of the LMV3XX family. A small series
resistance (RS) at the output of the amplifier, illustrated in
Figure 2, will improve stability and settling performance.
Rs values in the Frequency Response vs. CL plot were
• Place the 0.01 μF capacitor within 0.1 inches of the
power pin
chosen to achieve maximum bandwidth with less than
1dB of peaking. For maximum flatness, use a larger RS.
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
• Minimize all trace lengths to reduce series
inductances
As the plot indicates, the LMV3XX family can easily drive
a 200 pF capacitive load without a series resistance. For
comparison, the plot also shows the LMV321 driving a
200 pF load with a 225 Ω series resistance.
Refer to the evaluation board layouts shown in Figure 5
on page 8 for more information.
Driving a capacitive load introduces phase-lag into the
output signal, which reduces phase margin in the amplifi-
er. The unity gain follower is the most sensitive configura-
tion. In a unity gain follower configuration, the LMV3XX
family requires a 450 Ω series resistor to drive a 200 pF
load. The response is illustrated in Figure 3.
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8
Evaluation Board Information
Evaluation board schematics and layouts are shown in
Figures 4 and 5.
The following evaluation boards are NOT available any
more but their Schematic & Layout information will be
useful for references to aid in the testing and layout of this
device.
Eval Bd
Description
Products
Single Channel, Dual
KEB013 Supply, SOT23-5 for
Buffer-Style Pinout
LMV321AS5X
Single Channel, Dual
KEB014 Supply, SC70-5 for
Buffer-Style Pinout
LMV321AP5X
Dual Channel, Dual
KEB006
LMV358AM8X
LMV358AMU8X
LMV324AM14X
Supply, 8 Lead SOIC
Dual Channel, Dual
KEB010
Supply, 8 Lead MSOP
Quad Channel, Dual
KEB018
Supply, 14 Lead SOIC
Evaluation Board Schematic Diagrams
Figure 4a. LMV321 KEB013 schematic
Figure 4b. LMV321 KEB014 schematic
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9
Evaluation Board Schematic Diagrams (Continued)
Figure 4c. LMV358 KEB006/KEB010 schematic
Figure 4d. LMV324 KEB018 schematic
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10
LMV321 Evaluation Board Layout
Figure 5a. KEB013 (top side)
Figure 5b. KEB013 (bottom side)
Figure 5c. KEB014 (top side)
Figure 5d. KEB014 (bottom side)
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11
LMV358 Evaluation Board Layout
Figure 5e. KEB006 (top side)
Figure 5f. KEB006 (bottom side)
Figure 5g. KEB010 (top side)
Figure 5h. KEB010 (bottom side)
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12
LMV324 Evaluation Board Layout
Figure 5i. KEB018 (top side)
Figure 5j. KEB018 (bottom side)
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13
Physical Dimensions
SYMM
C
L
3.00
2.80
0.95
0.95
A
5
4
B
3.00
2.60
1.70
1.50
2.60
1
2
3
(0.30)
1.00
0.50
0.30
0.95
0.20
C A B
1.90
0.70
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.30
0.90
1.45 MAX
0.15
0.22
0.08
C
0.05
0.10
C
NOTES: UNLESS OTHEWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MO-178, ISSUE B, VARIATION AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) MA05Brev5
GAGE PLANE
0.25
8°
0°
0.55
0.35
0.60 REF
SEATING PLANE
Figure 6. 5-LEAD, SOT-23, JEDEC MO-178, 1.6MM
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Physical Dimensions (Continued)
Figure 7. 5-LEAD, SC70, EIAJ SC-88A, 1.25MM WIDE
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15
Physical Dimensions (Continued)
Figure 8. 8-LEAD, SOIC, JEDEC MS-012, 0.150 INCH NARROW BODY
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15
Physical Dimensions (Continued)
3.00 0.10
A
B
5.50
4.90 0.15
3.00 0.10
4.20
1.30 MIN
0.65
PIN #1 ID
QUADRANT
1
4
0.45
0.34
0.65
TOP VIEW
LAND PATTERN RECOMMENDATION
A
1.10 MAX
0.15
0.05
0.65
0.23
0.13
C
END VIEW
0.38
0.27
12°
M
0.10
A
B
C
SIDE VIEW
TOP & BOTTOM
GAUGE
PLANE
SEATING
PLANE
0°-8
NOTES: UNLESS OTHERWISE SPECIFIED
0.70
0.40
0.25
A. THIS PACKAGE CONFORMS TO JEDEC MO-187.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
0.95
DETAIL A
SCALE 20 : 1
D. DIMENSIONS AND TOLERANCES AS PER ASME
Y14.5-1994.
E. LAND PATTERN AS PER IPC7351#TSOP65P490X110-8BL
F. FILE NAME: MKT-MUA08AREV4
Figure 9. 8-LEAD, MSOP, JEDEC MO-187, 3.0MM WIDE
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Physical Dimensions (Continued)
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
1.27
LAND PATTERN RECOMMENDATION
0.35
M
0.25
C B A
(0.33)
1.75 MAX
SEE DETAIL A
1.50
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.50
0.25
X 45°
R0.10
R0.10
8°
0°
GAGE PLANE
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 10. 14-LEAD, SOIC, JEDEC MS-012, 0.150 INCH NARROW BODY
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18
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
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