LV25500PQA-NH [ONSEMI]

调频 (FM) 多路复用广播接收调谐器;


型号：	LV25500PQA-NH
厂家：	ONSEMI
描述：	调频 (FM) 多路复用广播接收调谐器
文件：	总13页 (文件大小：489K)
中文：	中文翻译
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LV25500PQA

Bi-CMOS LSI

http://onsemi.com

FM Multiplex Broadcasting

Receive Tuner

Overview

LV25500PQA is in-vehicle FM multiplex broadcasting receive only tuner

IC that makes FM tuner, PLL, and the RDS demodulator single-chip.

ON Semiconductor’s unique technology enables to reduce a large number

of external components for high frequency like coils, ceramic filters and

varicaps which were required for conventional tuner IC.

Small FM multiple tuner that can be installed also in PND etc. including

AVN can be composed.

WQFN56 7x7, 0.4P

Features

 No need for adjustment work.

 The AF search processing on the main tuner side is unnecessary according to using with the main tuner together.

 The high sensitivity reception and the high strong input tolerance are united by LNA built into equipped with the

WIDE-AGC function.

 The third and fifth high harmonic rejection type mixers of a local oscillation are adopted.

 The switch of UPPER/LOWER of a local oscillation and IF-BPF of injection is possible when the image signal is

detected.

 The complex BPF of the image attenuation type is built into.

 IF-BPF is made built-in by LOW-IF frequency (IF = 575 kHz) adoption.

 Dynamic range of S meter is wide.

 S meter tuning-system is adopted.

 The DLL demodulation method is adopted for FM demodulation circuit.

 LPF for the carrier removal is built into.

 S meter level, the adjacent obstruction level, and the multipath can be detected and read by way of I²C BUS.

 BPF (57 kHz) for the BPSK detection is built into.

 It becomes easy to miniaturize the tuner set with built-in the RDS demodulator.

 36.8MHz is adopted for the crystal oscillation frequency.

 The number of external parts is little.

Functions

 FM tuner function

 Antenna dumping control function

 Local oscillation of PLL control type

 WIDE/NARROW/IF-AGC function

 DLL demodulator

 57kHz carrier recovery and re-clock regeneration

 BPSK decode / differential decode

 ID reset function

 I²C BUS control

 I²C reset function

 Standby function

* I²C Bus is a trademark of Philips Corporation.

ORDERING INFORMATION

See detailed ordering and shipping information on page 13 of this data sheet.

September 2014 - Rev. 2

Publication Order Number :

LV25500PQA/D

LV25500PQA

Specification

Absolute Maximum Ratings at Ta = 25ºC

Parameter

Symbol

max

Conditions

Ratings

6.0

unit

Maximum supply voltage

Maximum input voltage

Ta = 25ºC

VIN1max

VIN2max

VIN3max

VO1max

VO2max

VO3max

Pd max

Topr

LNA_P, LNA_N

0.3 to 6.0

0.3 to 3.45

0.3 to 6.0

0.3 to 3.45

1.38

TEST, RST, XSTBY, XRST

SDA, SCL

Maximum output voltage

LPFO, BPSK, SMETER

RDS-ID, RDDA, RDCL, INT, SD

SDA

Allowable power dissipation

Operating temperature

Storage temperature

Ta≤85ºC (*)Specified board

ºC

40 to +85

50 to +150

Tstg

(*) Specified board is attached：80.0mm×80.0mm×1.0mm, glass epoxy board

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,

damage may occur and reliability may be affected.

Note : Machine model ESD voltage level of the pin 18 is less than 200V, because their high frequency characteristics are

extremely important. Handle pins 18 with care to prevent electrostatic breakdown.

Operating Conditions at Ta = 25ºC

Parameter

Symbol

Conditions

Ratings

5.0V

Recommended supply voltage

Operating supply voltage range

Input High level voltage

4.5 to 5.5V

3 to 3.45V

2.3 to 3.45V

0.5V or less

0.9V or less

400kHz or less

VINH1

VINH2

VINL1

VINL2

fSCL

TEST, RST, XSTBY, XRST

SDA, SCL

Input Low level voltage

SCL clock frequency

TEST, RST, XSTBY, XRST

SDA, SCL

SCL

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended

Operating Ranges limits may affect device reliability.

Range of Reception Frequency

Parameter

FM input frequency1

FM input frequency2

FM input frequency3

Symbol

FM_EU

Conditions

Ratings

87.5 to 108.0

87.9 to 108.1

76 to 90

unit

MHz

FM EU

FM US

FM JP

FM_US

FM_JP

The constant in application circuit is different in FM_EU, FM_US and FM_JP.

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LV25500PQA

Electric Characteristics at Ta = 25ºC, V

= 5.0V

fc = 98.1MHz, Vin = 60dBuVEMF, fm = 1kHz, Audio filter: HPF = 100Hz, LPF = 15kHz

Parameter

Symbol

SN30

Conditions

min

typ

max

unit

Usable sensitivity 1

(S/N30dB)

Usable sensitivity 2

(S/N10dB)

22.5kHz dev, fm = 1kHz,

S/N = 30dB input level

7.5kHz dev, fm = 76kHz,

S/N = 10dB input level [1]

dBuVEMF

SN10

dBuVEMF

SN ratio 1

SN1

22.5kHz dev, fm = 1kHz

7.5kHz dev, fm = 76kHz [1]

AM 30% mod

SN ratio 2

SN2

AM suppression ratio

Image removal ratio

Audio output level 1

Audio output level 2

AMR

IMR

22.5kHz dev, fm = 1kHz

7.5kHz dev, fm = 1kHz [1]

7.5kHz dev, fm = 76kHz [1]

ADO1

ADO2

mVrms

LNA input level when SD terminal

is on.

SD sensitivity

SDS

dBuVEMF

Center frequency

57kHz BPF peak frequency

kHz

RDDA, RDCL, INT, SD

IOL=0.5mA

VOL1

0.5

Output (L) level voltage

Output (H) level voltage

VOL2

VOL3

RDS-ID,IOL=0.5mA

0.5

SDA (when V

pull up)

RDDA, RDCL, INT, SD

IOH=0.5mA

VOH1

VOH2

ICC1

ICC2

2.3

0.7*V

[2]

SDA (when V

pull up)

When no signal input

RDS mode

When no signal input

VICS mode

Current consumption 1

Current consumption 2

125

120

165

155

205

190

[1] Audio filter : HPF = 100Hz, LPF = OFF

[2] V : μ-COM Supply Voltage

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.

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LV25500PQA

RDS input/output Format

RST Pin

RST= 0

RST= 1

Normal operation

Reset of RDS-ID and demodulator circuit

RDS-ID

RDS-IDoutput

Active-Low

RDCL/RDDA Output timing

421μs 421μs

RDCL output

RDDA Output

17μs

RDS-ID Output timing

High/Low High/Low High/Low High/Low High/Low High/Low High/Low

RDS-ID

RDCL

RDDA

Note : RDS-ID is High : data with Low RDS reliability, Low: data with High RDS reliability

RST operation

Tp3  250ns

RST

RDS detection

circuit output

RDCL

RDDA

Note : RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is detected.

Note : When the reception channel is changed, a memory reset must be applied using RST input.

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LV25500PQA

Package Dimensions

WQFN56 (7.0mm x 7.0mm)

unit : mm

WQFN56 7x7, 0.4P

CASE 510BD

ISSUE O

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO THE PLATED

TERMINAL AND IS MEASURED ABETWEEN

0.15 AND 0.25MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN 1

INDICATOR

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

MILLIMETERS

DIM MIN

A1 0.00

MAX

0.80

0.05

EXPOSED Cu

MOLD CMPD

0.20 REF

0.15

0.25

7.00 BSC

D2 5.10

5.30

0.15

7.00 BSC

TOP VIEW

DETAIL B

E2 5.10

5.30

ALTERNATE

0.40 BSC

0.30

CONSTRUCTION

(A3)

DETAIL B

0.50

0.15

0.10

0.08

L1 0.00

GENERIC

MARKING DIAGRAM*

NOTE 4

SEATING

PLANE

SIDE VIEW

XXXXXXXXX

AWLYYWWG

0.10

C A B

0.10

DETAIL A

C A B

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

= Pb-Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

56X

e/2

0.10

0.05

C A B

NOTE 3

RECOMMENDED

BOTTOM VIEW

SOLDERING FOOTPRINT*

5.40

7.30

56X

0.63

0.40 PITCH

56X

0.26

DIMENSIONS: MILLIMETERS

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

MountingTechniques Reference Manual, SOLDERRM/D.

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LV25500PQA

Block Diagram

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LV25500PQA

Example of application circuit (FM_US) [1] [2] [3] [4] [5]

Used Components(FM_US)

Component

Parameter

RF BPF coil

Local OSC coil

Crystal

Value

270nH

220nH

2.7nH

Supplier

SAGAMI

KDS

Type

L3/L4

C2012C-R27G-RC

C2012C-R22G-RC

C2012H-2N7D-RD

DSX321G

36.8MHz

[1] The external parts for crystal oscillation circuit terminal (pin42 and pin43) need to match the quartz vibrator. R3, R4,

C24, C25 are the tentative arrangement parts.

[2] Caution is required for layout of the board because the parasitic capacitance between pin42, pin43 and Power, GND,

etc causes the decrease of the margin of the crystal oscillation and the deviation of the crystal frequency, etc.

[3] This IC uses the signal of FM band frequency (VCO divided into 1/4) which leaks into ANT pin. If the VCO leakage

affects the performance of the system, make sure to connect an isolator on ANT pin path.

[4] REG (pin27, pin44, pin46) is only used for LV25500.

[5] This example of application circuit, the power-supply voltage becomes the circuit using 3.3V μ-COM.

The bi-directional level shifter circuit is connecting two different voltage sections in I2C-Bus system.

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LV25500PQA

Example of level shift circuit

VDD2=5V

VDD1=3.3V

SDA1

SDA2

SCL2

SCL1

RDS-ID1

RST1

RDS-ID2

RST2

XRST1

XSTBY1

XRST2

XSTBY2

3.3V

DEVICE

LV25500

DEVICE

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LV25500PQA

Pin description

Name

XSTBY

XRST

I/O

Explanation

Standby pin(0:stanby, 1:standby release)

Tuner reset pin (0:reset, 1:reset release)

RDS–ID reset pin(Positive polarity)

Test pin

RST

TEST3

GND_IFBPF

VCC_IFBPF

VCC_MIX

WAGC

GND_MIX

LNA_P

GND_FE

LNA_N

ANTD

VCC_FE

VEE

VCC_LO

LO_1

GND_LO

LO_2

GND pin for IF BPF

VCC pin for IF BPF

VCC pin for MIXER

Capacity pin for WAGC

No connection

GND pin for MIXER

Input pin for LNA+

GND pin for LNA

Input pin for LNA-

ANT dumping control pin

Power-supply pin for LNA

GND pin for ESD

VCC pin for local oscillation

Inductor connection pin for local oscillation

GND pin for local oscillation

Inductor connection pin for local oscillation

No connection

GND_PLL

VDDA

No connection

Capacity pin for PLL charge pump

GND pin for PLL logic

Power-supply pin for logic

Power-supply pin for PLL logic

Regulator capacity pin for PLL logic

Power-supply pin for Regulator

Capacity pin for IFAGC

Capacity pin for demodulation/detection

Capacity pin for LPF DC cancel

S-meter output pin

VDD_PLL

REG_PLL

VCC_PLL

IFAGC

DEMOC

LPFDCC

SMETER

LPFO

VCC_IF

BPFC

GND_IF

BPSK

FM demodulation output pin (After band limitation)

VCC pin IF

Capacity pin for BPF

GND pin for IF

Bi-phase data career output pin

Data slicer input pin

SLC

DEVAR

VCC_LOG

XTALO

XTALI

Device address setting pin

VCC pin for Regulator

No connection

Crystal resonance element connection pin

Regulator pin for crystal

REG_XO

Ｏ

GND_LOG

REG_LOG

VDD_LOG

CPRDS

GND pin for control logic

Regulator pin for control logic

Power-supply pin for control logic

PLL charge pump pin for RDS clock generation

No connection

Station detector pin/Test pin

Interrupt flag pin/Test pin

RDS reliability data output pin

(0:high reliability, 1:low reliability)

RDS clock output pin

SD/TEST1

INT/TEST2

RDS-ID

RDCL

RDDA

SCL

RDS data output pin

Serial data clock input pin

Serial data input/output pin

SDA

I/O

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LV25500PQA

I²C Bus Communication Format

Device address (in case of 39pin, DEVAR, pull down) Normal

MSB

LSB

Function

WRITE mode (C0h)

READ mode (C1h)

Device address (in case of 39pin, DEVAR, pull up)

MSB

LSB

Function

WRITE mode (C2h)

READ mode (C3h)

MSB

LSB

Function

Reg0 : 00h

Reg1 : 01h

Reg2 : 02h

Reg29 : 2Dh

Reg30 : 2Eh

Reg31 : 2Fh

 Bus transmission format description

Format conforms to the I²C standard (see below).

 Start condition

 Repeated start condition

 Stop condition

 Write byte

 Read byte

Start, Repeated start, and stop conditions are defined under the conditions shown below.

Start

Repeated Start

Stop

SCL

SDA

SCL

SDA

SCL

SDA

The I²C start, repeated start and stop conditions.

For detailed information such as timing, refer to the I²C specifications.

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LV25500PQA

 8Bit Write

8Bit data is sent from the master microcomputer to LV25500.

For data bit, MSB first, LSB last.

Data transmission is synchronized with the SCL clock generated by the master IC. It is latched on the rising edge of SCL.

Data should not be changed while SCL is HIGH.

LV25500 outputs an ACK bit during the 8^thand 9^thof the falling edge of SCL.

SCL

Ack

SDA

Signal pattern of the I²C byte write

 8Bit Read

Read is similar with Write format but data direction is opposite.

8Bit data is sent from LV25500 to the master, and ACK is sent from the master to the LV25500.

SCL

Ack

SDA

Signal pattern of the I²C byte read

Serial clock SCL will be provided by the master side.

Data bits which are out from the LV25500 are synchronized with the falling edge. And the master side should latch the

data bits on the rising edge.

LV25500 latches the ACK on the rising edge.

The following is the sequence that writes data D to the LV25500 register A. (In case of PULL DOWN)

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LV25500PQA

 Write Sequence

 Start condition confirmation

 Write device address(C0h)

 Write address information A

 Write Data D

 Stop condition

write device address

start

SCL

SDA

Ack

DA7

DA6 ... 1

write register address

write data byte

stop

Ack

A6 ... 0

D6 ... 0

If more than one data was written, only the first data will be written.

 Read Sequence

 Start condition confirmation

 Write device address (C0h)

 Write address information A

 Repeated start condition (Or, stop + start sequence by the master)

 Write device address +1 (C1h)

 Read Register information D and send NACK (no more data to be read)

 Stop condition

start

write device address

write register address

rep.

SCL

SDA

Ack

DA7

DA6 ... 1

A6 ... 1

start

write device address + 1

read data byte with NACK

stop

Ack

DA7

DA6 ... 1

D6 ... 0

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LV25500PQA

ORDERING INFORMATION

Device

Package

Shipping (Qty / Packing)

2500 / Tape & Reel

WQFN56 7x7, 0.4P

(Pb-Free / Halogen Free)

LV25500PQA-NH

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiariesin the United States

and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of

SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without

further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose,

nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including

without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can

and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are

not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or

sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was

negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all

applicable copyright laws and is not for resale in any manner.

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LV25500PQA-NH [ONSEMI]

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