LV5232VH [ONSEMI]
16ch LED Driver;
| 型号： | LV5232VH |
| 厂家： | 
ONSEMI |
| 描述： | 16ch LED Driver 驱动 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总9页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1628D
LV5232VH
Bi-CMOS IC
http://onsemi.com
16ch LED Driver
Overview
The LV5232VH is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output
16-stage shift register that features a CMOS structure based on Bi-CMOS process technology. The LV5232VH also
contains an n-channel CMOS construction high-withstand-voltage, large-current drive 16-stage parallel output driver.
The protection circuit of the output malfunction is built into.
Function
• Serial input and serial or parallel output
• Enable input for output control
• Serial output enables cascade connection
• Low supply current (30μA typ. during standby ICC≤40μA)
• Serial input/output levels compatible with typical CMOS devices
• High-withstand-voltage LED driver with open drain output
High withstand voltage (VDS < 42V)
High-current drive (I max = 100mA)
O
• Operating temperature range Ta = -25 to 75°C
• Output malfunction protection circuit
Reset input pin , V
decrease voltage confirmation
CC
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Output voltage
Symbol
Conditions
Ratings
Unit
V
V
V
I
max
SV
CC
6
42
CC
max
LEDO1 to LEDO16 off
V
O
Output current
max
100
mA
mW
°C
°C
O
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta ≤ 25°C *
1100
-25 to +75
-40 to +125
Tstg
* Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Operating supply voltage range
Output applied voltage
Output current
Symbol
Conditions
Ratings
Unit
V
V
V
V
I
SV
SV
5.0
3.0 to 5.5
42
CC
CC
op
V
CC
CC
V
O
Duty = 45% to 55%
100
mA
O
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of this data sheet.
Semiconductor Components Industries, LLC, 2013
September, 2013
90413NK 20130821-S00001/52913NK 20130514-S00002 No.A1628-1/9
LV5232VH
Electrical Characteristics at Ta = 25°C, V
= 5.0V
CC
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Quiescent current drain
LEDO output on resistance
OFF leak current
I
1
LEDO driver off (standby)
= 30mA
30
40
10
μA
Ω
CC
Ron
Ileak
Vt
I
5
0
O
V
= 42V
μA
V
O
Driver output malfunction
prevention voltage
2.58
2.70
2.82
Control circuit block
H level 1
L level 1
H level 2
L level 2
V
V
V
V
H1
L1
Input H level
Input L level
V
× 0.8
0
V
V
V
V
IN
CC
V
× 0.2
IN
CC
UTH1
UTL1
SOUT I = -1mA
O
V
-0.3
CC
O
SOUT I = 1mA
O
0
0.3
O
Package Dimensions
unit : mm (typ)
3222A
15.0
28
15
14
1
2.0
0.8
0.2
0.3
(0.7)
2.7
HSOP28(275mil)
Pd max -- Ta
1.5
1.0
0.55
0.5
0
0
25
50
75
100
No.A1628-2/9
LV5232VH
Pin Assignment
25 24 23
21
20
19 18 17
28
27 26
22
16 15
1
2
3
4
5
6
7
8
9
10 11
12
13 14
Top view
Pin Descriptions
Pin No.
Pin name
I/O
Description
1
SV
Power supply
CC
2
SOUT
O
O
O
shift register output (final-stage shift register)
LEDO8 Latch output (LEDO8 of shift register)
LEDO7 Latch output (LEDO7 of shift register)
GND
3
LEDO8
LEDO7
PGND2
LEDO6
LEDO5
4
5
6
O
O
LEDO6 Latch output (LEDO6 of shift register)
LEDO5 Latch output (LEDO5 of shift register)
7
Heat sink
8
9
LEDO4
LEDO3
PGND1
LEDO2
LEDO1
SDATAIN
XRESET
SGND
O
O
LEDO4 Latch output (LEDO4 of shift register)
LEDO3 Latch output (LEDO3 of shift register)
GND
10
11
O
O
I
LEDO2 Latch output (LEDO2 of shift register)
LEDO1 Latch output (LEDO1 of shift register)
Serial Input
12
13
14
I
Reset input (shift register and latch)
GND
15
16
SCK
I
Clock input (for shift register)
17
LEDO16
LEDO15
PGND4
LEDO14
LEDO13
O
O
LEDO16 Latch output (LEDO16 of shift register)
LEDO15 Latch output (LEDO15 of shift register)
GND
18
19
20
O
O
LEDO14 Latch output (LEDO14 of shift register)
LEDO13 Latch output (LEDO13 of shift register)
21
Heat sink
22
LEDO12
LEDO11
PGND3
PGND10
PGND9
LATCH
O
O
LEDO12 Latch output (LEDO12 of shift register)
LEDO11 Latch output (LEDO11 of shift register)
GND
23
24
25
26
27
O
O
I
LEDO10 Latch output (LEDO10 of shift register)
LEDO9 Latch output (LEDO9 of shift register)
Latch input
When the latch input is held low, the LED0 output status is retained.
When a high-level is input, the LED0 outputs change when the status of the shift register changes.
28
XEN
I
Enable inputs (LEDO1 to LEDO16)
When a high-level is input, all the LED0 outputs are turned off.
When a low-level is input, the shift register data is output to LED0.
No.A1628-3/9
LV5232VH
Block Diagram
SCK SDATAIN LATCH XEN
SV
CC
SV _protection
CC
XRESET
LEDO1
LEDO2
LEDO3
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
D Q
C Q
R
C Q
R
LEDO4
LEDO13
LEDO14
D Q
D Q
C Q
R
C Q
R
LEDO15
LEDO16
D Q
C Q
R
D Q
C Q
R
D Q
D Q
C Q
R
C Q
R
LEDO1 LEDO5 LEDO9 LEDO13
LEDO2 LEDO6 LEDO10 LEDO14
LEDO3 LEDO7 LEDO11 LEDO15
LEDO4 LEDO8 LEDO12 LEDO16
D Q
C Q
R
PGND3
Heat sink & GND
PGND4
SOU
PGND1
T
PGND2
SGND
No.A1628-4/9
LV5232VH
Pin Functions
Pin No.
Pin Name
Pin function
Pull-down input
Equivalent Circuit
13
16
SDATAIN
SV
CC
SCK
SDATAIN/
SCK
SGND
14
27
28
XRESET
LATCH
XEN
Pull-up input
SV
CC
XRESET/
LATCH/
XEN
SGND
2
SOUT
SOUT output
SV
CC
SOUT
SGND
3
LEDO8
LEDO7
LEDO6
LEDO5
LEDO4
LEDO3
LEDO2
LEDO1
LEDO16
LEDO15
LEDO14
LEDO13
LEDO12
LEDO11
LEDO10
LEDO9
LEDO outputs
LEDO1/LEDO2/LEDO3/LEDO4/
LEDO5/LEDO6/LEDO7/LEDO8/
LEDO9/LEDO10/LEDO11/LEDO12/
LEDO13/LEDO14/LEDO15/LEDO16
4
LEDO1 to LEDO16
6
7
SV
8
CC
9
11
12
17
18
20
21
22
23
25
26
SGND
PGND
No.A1628-5/9
LV5232VH
Function
The LV5232VH consists of 1) an 16-stage D-type flip-flop and 2) an 16-stage D-type flip-flop connected to the output
of 1). When data is supplied to the serial data input (SDATAIN) and the clock pulse is supplied to the clock input
(SCK), the serial data input signal is input to the internal shift register and the data already in the shift register shifted
sequentially when the clock changes from low to high.
The serial output (SOUT) is used to connect multiple LV5232VH to expand the number of bits and is connected to the
SDATAIN of the next stage. (Cascade connection supported.)
For parallel output, when the output control enable input (XEN) is low, the latch input (LATCH) changes from low to
high and the clock pulse input changes from low to high, the serial data input signal is output to LEDO1, and the output
is shifted sequentially. For parallel outputs (LEDO2 to LEDO16), the signals whose polarities inverted from those of
the serial data input (SDATAIN) are output.
When the EN input is high, outputs LEDO1 through LEDO16 all turn off.
When the reset input is low, outputs LEDO1 through LEDO16 and SOUT outputs all turn off. The power must be
turned on after checking that the reset input is low.
To prevent the malfunction, the output load protection circuit is built into. The output of LEDO1 to LEDO16 is
compulsorily turned off when becoming below the voltage with a constant there is V
.
CC
Timing conditions
Parameter
Clock frequency
Clock pulse width
Latch pulse width
Data set up time
Data hold time
symbol
fs1
Conditions
min
typ
max
unit
MHz
ns
SCK Duty = 50%
SCK
10
twck
twla
ts1
50
50
LATCH
ns
SDATAIN setup time relative to the rise of SCK
SDATAIN data hold time relative to the rise of SCK
25
ns
th1
25
ns
Clock latch time
Input conditions 1
Input conditions 2
tla1
ton
100
ns
SCK and SDATAIN rise time
SCL and SDATAIN fall time
100
100
ns
toff
ns
twck
90% 90%
SCK
2.5V
th1
2.5V
10%
10%
ts1
ton
toff
2.5V
2.5V
SDATAIN
LATCH
twla
tla1
2.5V
2.5V
No.A1628-6/9
LV5232VH
SOUT output timings
Parameter
SOUT delay time 1
SOUT delay time 2
symbol
tdso1
tdso2
Conditions
min
typ
max
unit
MHz
ns
The time from a SCK falling edge to SOUT rising edge
The time from a SCK falling edge to SOUT falling edge
50
50
SCK
2.5V
2.5V
tdso1
tdso2
2.5V
2.5V
SOUT
LEDO output timings
Parameter
symbol
tdled1
Conditions
min
typ
max
unit
ns
LEDO delay time 1
The time from an XEN rising edge to LEDO rising edge
CL = 30pF, I = 100mA, V = 42V
100
100
200
200
200
O
O
LEDO delay time 2
LEDO rise time
tdled2
trled
The time from an XEN falling edge to LEDO falling edge
CL = 30pF, I = 100mA, V = 42V
ns
ns
ns
ns
O
O
LEDO rise time
CL = 30pF, I = 100mA, V = 42V
O
O
LEDO fall time
tfled
LEDO fall time
CL = 30pF, I = 100mA, V = 42V
O
O
LEDO delay time 3
tdled3
The time from a LATCH rising edge to LEDO falling edge
CL = 30pF, I = 100mA, V = 42V
O
O
XEN
2.5V
2.5V
tdled1
tdled2
90%
90%
90%
10%
10%
LEDO
trled
tfled
tdled3
2.5V
LATCH
No.A1628-7/9
LV5232VH
Application Circuit Example
max:42V
5V
SV
CC
SV
CC
To
SDATAIN
LEDO1
LEDO1
SDATAIN
CPU
SDATAIN
SCK
SCK
LATCH
LATCH
XEN
LEDO16
SOUT
XEN
LEDO16
SOUT
XRESET
XRESET
Temperature properties graph
I
O
-- LEDO
I
O
-- LEDO
100
90
100
Ta = 25 C
50 C
Ta = 25
C
50 C
90
80
80
70
70
60
duty cycle 100%
duty cycle 80%
60
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Number of output ports, LEDO
Number of output ports, LEDO
I
O
-- LEDO
100
Ta = 25 C
50 C
75 C
90
80
70
60
duty cycle 50%
0
2
4
6
8
10
12
14
16
Number of output ports, LEDO
No.A1628-8/9
LV5232VH
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
2000 / Tape & Reel
HSOP28 (275mil)
(Pb-Free / Halogen Free)
LV5232VH-TLM-H
HSOP28 (275mil)
(Pb-Free / Halogen Free)
LV5232VH-MPB-H
30 / Fan-Fold
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PS No.A1628-9/9
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