LV8324CGR2G [ONSEMI]
24 V Single-Phase BLDC Motor Driver;
| 型号： | LV8324CGR2G |
| 厂家： | 
ONSEMI |
| 描述： | 24 V Single-Phase BLDC Motor Driver |
| 文件： | 总30页 (文件大小：1991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductor
Is Now
To learn more about onsemi™, please visit our website at
www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
24 V Single-Phase BLDC
Motor Driver
LV8324C
INTRODUCTION
Overview
www.onsemi.com
The LV8324C is the driver for 24 V single phase BLDC motor. Its
target output duty-cycle can be set by input PWM duty cycle. The
output duty-cycle curve setting can be stored to the internal
nonvolatile memory (NVM). In addition, lead-angle can also be
adjusted by the configuration saved in the internal NVM. Thus, it can
drive various kinds of motors at high efficiency and low noise.
14
1
TSSOP−14
CASE 948AW
Features
• Selectable Soft Start or Direct Output PWM Duty Control in Start-up
• Power On Delay Function
PIN ASSIGNMENT
(Programmable Ignore Time for PWM Input)
• Single-phase Full Wave Driver with Open-loop Output Duty−cycle
Control
OUT1
PVCC
VCC
REG
VDD
IN1
1
2
3
4
5
6
7
14 RF
13 (NC)
12 OUT2
11 GND
10 TSL
• Embedded Power FETs, I
= 1.0 A
omax[peak]
• PWM Duty Cycle Input (25 Hz to 80 kHz)
9
8
PWM
FG
IN2
• PWM Soft Switching Phase Transition
• Soft PWM Duty Cycle Transitions
(Changing the Target Output−Duty Gradually)
• Built-in Current Limit Function and Over Current Protection
Function
(Top View)
MARKING DIAGRAM
• Built-in Thermal Protection Function
14
• Built-in Locked Rotor Protection and Automatic Recovery Function
• FG or RD or RDA Signal Output Selectable
• Dynamic Lead Angle Adjustment with Respect to Rotation Speed
• Parameter Setting by Serial Communication
• Embedded EEPROM as NVM
LV83
24C
ALYWG
G
1
LV8324C = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Parameter Setting to the NVM
• The Device is Pb-Free and Halogen Free
Typical Applications
• Fan Motor in Factory Automation
ORDERING INFORMATION
†
Device
LV8324CGR2G
Package
Shipping
TSSOP−14
(Pb-Free/
2,500 /
Tape & Reel
Halogen Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
October, 2020 − Rev. 0
LV8324C/D
LV8324C
Application Diagram
Figure 1 shows the application diagram.
Figure 1. Application Diagram
External Components
The power supplies of the IC need to be decoupled
properly. This means that at least one external capacitor C1
must be connected in between GND and VCC, and one
external capacitor C2 between REG, VDD and GND.
Table 1 shows the external component list. Please refer to
section “Pin Description” (Table 7) as well.
Table 1. EXAMPLE OF EXTERNAL COMPONENT VALUE FOR 24 V APPLICATION (Figure 1)
Manufacture
Part Number
Device
D1
Qty
1
Description
Anti−reverse connection diode
Anti−abnormal boost Zener diode
VCC bypass capacitor
REG bypass capacitor
Filter of system noise
Value
−
Tol
−
Footprint
Manufacture
D2
1
−
−
C1
1
10 mF 50 V
1 mF 25 V
0.1 mF 50 V
2 kW 1/4 W
10 kW 1/4 W
150 mW 1/8 W
10%
10%
10%
5%
5%
1%
C2
1
C3
1
R1
1
Current limiter resistor for Hall
FG pull−up resistor
R2
1
R3
1
Sense resistor for CLM/OCP
Hall element
T1
1
www.onsemi.com
2
LV8324C
VCC and GND (VCC, GND)
Command Input Pin (PWM)
The power supplies of the IC need to be decoupled
properly. The following three capacitors must be connected.
• between VCC (pin 3) and ground as C1 in the
application diagrams
This pin reads the duty cycle of the PWM pulse which
controls rotational speed. The PWM input signal level is
supported from 2.8 V to 5.5 V. Linear voltage control is not
supported. The minimum pulse width is 100 ns.
• between REG (VDD) and ground as C2
Current Limiter Resistor for Hall (R1)
The Zener diode (D2) in Figure 1 is mandatory to prevent
the IC break down in case the supply voltage exceeds the
absolute maximum ratings due to the flyback voltage.
Hall output amplitude can be adjusted by R1.
The amplitude is proportional to Hall bias level VH for
particular magnetic flux density. VH is determined by the
following equation.
Hall−Sensor Input Pins (IN1, IN2)
Differential output signals of the hall sensor are connected
at IN1 and IN2. It is recommended that the capacitor (C3) is
connected between both pins to filter system noise. The
value of C3 should be selected properly depending on the
system noise. When a Hall IC is used, the output of the Hall
IC must be connected to the IN1 pin and the IN2 pin must be
kept in the middle level of the Hall IC power supply voltage
which should be corresponded to recommended operating
range.
Rh
ǒRh ) R1Ǔ
VH + VREG
(eq. 1)
Where
VREG: REG pin voltage (5 V)
Rh: Hall resistance
However, it should be considered with Hall sensor
specification and Hall bias current. The bias current should
be set under 20 mA which is REG pin max current.
Table 2. TRUTH TABLE
IN1
IN2
*Inner PWM state
OUT1
OUT2
FG
Operation state
Drive mode
L
H
On
Off
On
Off
L
L
H
L
L
L
Hi−Z
Regeneration mode
Drive mode
H
L
H
L
L
Regeneration mode
*Inner PWM state means the OUTPUT active period decided by inner control logic. Don’t match with PWM−pin input signal.
*Condition: Register “DRVMODE [1:0]” = 01
www.onsemi.com
3
LV8324C
SPECIFICATIONS
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Rating
Unit
V
Maximum Supply Voltage
VCC
VCC pin
36
MAX
OUTMAX
OUTMAX
REGMAX
Maximum Output Voltage
V
OUT1/OUT2 pin
OUT1/OUT2 pin
REG pin
36
V
Maximum Output Current (Note 1)
REG Pin Maximum Output Current
IN1/IN2 Pin Maximum Input Voltage
PWM Pin Maximum Input Voltage
FG Pin Withstanding Voltage
FG Pin Maximum Current
I
1.0
A
I
20
mA
V
V
INMAX
IN1/IN2 pin
5.5
V
PWM pin
5.5
V
PWMMAX
V
FG pin
36
7.5
V
FGMAX
FGMAX
I
FG pin
mA
W
Allowable Power Dissipation (Note 2)
Pd
MAX
with exposed pad
without exposed pad
0.93
0.80
Operating Temperature
T
−40 to +105
−55 to +150
150
°C
°C
°C
−
OP
Storage Temperature
T
STG
T
jmax
Maximum Junction Temperature
Moisture Sensitivity Level (MSL) (Note 3)
MSL
1
Lead Temperature Soldering Pb-Free Versions
(30 s or less) (Note 4)
255
°C
T
SLD
ESD Human Body Model: HBM (Note 5)
ESD
3000
V
HBM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
is the peak value of the motor supply current.
OUTMAX
2
2. Specified circuit board: Toroidal shaped. The actual area is 369 mm , thickness is 0.8 mm and glass epoxy 2-layer board which has 1 oz
internal power and ground plane and 1/2 oz copper traces on top and bottom of the board.
3. Moisture Sensitivity Level (MSL): IPC/JEDEC standard: J−STD−020A.
4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
5. ESD Human Body Model is based on JEDEC standard: JESD22−A114.
Table 4. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
156
Unit
°C/W
°C/W
°C/W
°C/W
Thermal Resistance, Junction-to-Ambient without Exposed Pad (Note 2)
Thermal Resistance, Junction-to-Ambient with Exposed Pad (Note 2)
Thermal Resistance, Junction-to-Case (Top) without Exposed Pad (Note 2)
Thermal Resistance, Junction-to-Case (Top) with Exposed Pad (Note 2)
R
q
JA
R
134
q
JA
R
13.5
5.7
Y
JT
R
Y
JT
Table 5. RECOMMENDED OPERATING RANGES
Parameter
Symbol
Conditions
Rating
24
Unit
V
VCC Supply Voltage
VCC
VCC
VCC pin
TYP
OP1
NVM
VCC Operating Supply Voltage Range1
VCC pin
VCC pin
6.0 to 34
14 to 34
V
VCC Operating Supply Voltage Range for NVM Program/
Erase Operation
VCC
V
PWM Input Frequency Range
PWM Minimum Input Low/High Pulse Width
IN1 Input Voltage Range
F
PWM pin
PWM pin
IN1 pin
25 to 80k
100
Hz
ns
V
PWM
T
WPWM
V
V
0 to VDD
0.3 to 0.55 × VDD
0.15
IN1
IN2 Input Voltage Range
IN2 pin
V
IN2
Minimum External Resister Value
R_RFmin
W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
4
LV8324C
Table 6. ELECTRICAL CHARACTERISTICS (T = 25°C, VCC = 24 V unless otherwise noted)
A
OP
Parameter
Circuit Current
Symbol
Conditions
Min
−
Typ
7
Max
10.5
0.8
0.8
−
Unit
mA
W
I
Under the Power On Delay state
CC
OUT1/OUT2 High-side On-resistance
OUT1/OUT2 Low-side On-resistance
OUT1/OUT2 PWM Output Frequency
PWM Pin Low Level Input Voltage
PWM Pin High Level Input Voltage
PWM Input Resolution
R
I
= 0.3 A
= 0.3 A
−
0.5
0.5
48
−
OH-ON
O
O
R
I
−
W
OL-ON
PWMO
f
−
kHz
V
V
0
0.7
VDD
−
PWML
PWMH
V
2.8
−
−
V
D
8
Bit
mA
PWM
PWM Input Bias Current
(VDD = 5.5 V, PWM = 0 V)
Ipwmin
25
50
75
FG Pin On-resistance
FG Pin Leak Current
REG Pin Output Voltage
V
I
= 5 mA
60
1
W
mA
V
FGL
FG
I
V
= 34 V, V = 34 V
−
4.7
−
−
5.0
−
FGLK
CC
FG
V
REG
5.3
50
REG Pin Output Voltage Load
Regulation
DV
I
= −10 mA
mV
REGLD
REG
Lock-detection Time1 (Note 6)
Lock-detection Time2 (Note 7)
Lock-Stop Release Time1
from 1 to 4 Off Time (Note 7)
Lock-Restart On Time (Note 7)
Lock-Restart Time Ratio1
T
Under rotation
−
−
−
0.3
0.95
9.0
−
−
−
S
S
S
LD1
T
LD2
Start-up/Restart, LOCK_DET = 3
RESTART_INT = 3
T
LRoff1
st
th
T
LRon
LOCK_DET = 3
−
−
0.95
9
−
−
S
R
T
/T LOCK_DET = 3,
−
LR1
LRoff1 LRon,
RESTART_INT = 3
Lock-Stop Release Time2 as from
T
−
−
14
15
−
−
−
−
S
−
LRoff2
th
5
Off Time (Note 8)
Lock-Restart Time Ratio2 as from
R
T
/T
, LOCK_DET = 3
LR2
TSD
LRoff2 LRon
th
5
Off Time (Note 8)
Thermal Shutdown Protection
Detection Temperature
T
(Guaranteed by design)
(Guaranteed by design)
150
−
180
40
°C
°C
Thermal Shutdown Protection
Detection Hysteresis
DT
TSD
Over Current Detection Voltage
Current Limiter
I
−
90
−
150
100
−
−
110
1
mV
mV
mA
mV
V
OVC
I
CL
hin
Hall Input Bias Current
Hall Input Sensitivity
I
IN1, IN2 = 0 V
DVhin
Vuvdet
Vuvrls
DVuv
40
−
−
−
UVLO Detection Voltage
UVLO Release Voltage
UVLO Hysteresis Voltage
5.2
5.6
0.4
−
−
−
V
−
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. When a motor rotates with below 50 rpm (phase change period over 0.3 s), lock protection will works. See Figure 17 for the detail.
7. When a motor can’t rotate for the time which is set by the register named LOCK_DET after start-up, lock protection will work. See Figure 18
for the detail.
th
8. When the locked rotor state continues for long time, lock stop period changes as from 5 off time. See Figure 18 for the detail.
www.onsemi.com
5
LV8324C
BLOCK DIAGRAM
Figure 2 shows the functional block diagram of LV8324C.
OUT1
1
RF
14
PVCC
2
NC
13
VCC
OUT2
12
Current
limitter
3
Boot strap
Pre−driver
REG
4
SGND
11
5V
regulator
UVLO
TSD
VDD
5
TSL
10
Drive control logic
Duty Cycle
Counter
IN1
6
PWM
9
SWI
NVM
IN2
7
FG
8
Hall
comparator
OSC
Figure 2. Block Diagram
www.onsemi.com
6
LV8324C
PIN DESCRIPTION
Table 7 shows the pin list and their functions.
Table 7. PIN LIST AND FUNCTION
Pin No.
Pin Name
OUT1
PVCC
VCC
Description
1
2
3
4
Motor drive output pin. This pin is connected to the built−in power MOSFET.
Power supply pin for built−in power MOSFET.
Power supply for internal circuit, ex. pre−driver, charge−pump.
REG
5.0 V regulator output. This voltage acts as a power source for oscillator, protection circuits, and so on. The
maximum load current of REG is 20 mA. Be sure not to exceed this maximum current
5
6
7
8
VDD
IN1
IN2
FG
Power supply pin for both digital and analog circuits. This pin must be connected to REG pin
Hall sensor input pin. The differential outputs of the hall sensor need to be connected to IN1 and IN2 each.
The FG (frequency generator) output controls the motor electrical rotational speed (FG output synchronizes
with the Hall sensor signal). This pin can function as RD (rotation detection) and RDA (Rotation Decline
Alarm ) by bit setting of Reg. 0x010C “TACHSEL”. The FG pin is an open drain output. Recommended pull
up resistor is 1 kW to 100 kW. Leave the pin open when not in use. Parameter setting through the communi-
cation is performed by the pin use
9
PWM
TSL
Rotational control signal input pin. The rotational speed is controlled by duty−cycle of the pulse and is propor-
tional to the duty−cycle ratio. Parameter setting through the communication is performed by this pin
10
Communication input selection and internal test mode pin.
When short to GND, FG pin is serial in/out.
When short to REG, PWM pin is serial in and FG pin is for serial out
11
12
13
14
SGND
OUT2
NC
Internal circuit ground pin
Motor drive output pin. This pin is connected to the built−in power MOSFET.
No connection
RF
Sense resistor voltage input for current limit / over current protection
SIMPLIFIED EQUIVALENT CIRCUITS
Table 8 shows the pin information. The pull-up/down resistor and diode path are included.
Table 8. PIN EQUIVALENT CIRCUIT
OUT1, OUT2
PVCC, VCC/SGND
(OUT+4.5 V)
PVCC
PVCC
VCC
OUT1
OUT2
SGND
RF
VDD
RF
SGND
www.onsemi.com
7
LV8324C
Table 8. PIN EQUIVALENT CIRCUIT (continued)
REG
VDD
VCC
VDD
REG
SGND
SGND
IN1
IN2
VCC
VDD
IN 2
IN 1
SGND
SGND
PWM
FG
VCC
VDD
VCC
FG
Low
96k
VDD
PWM
SGND
SGND
TSL
RF
VDD
VDD
RF
TSL
SGND
GND
www.onsemi.com
8
LV8324C
OPERATION DESCRIPTION
duty-cycle is 5 ms and rising time is 2.5 ms. In case of
“SS_SW_SEL = 1”, each time is half of the case of
“SS_SW_SEL = 0”.
If a motor already rotates at the power on in faster speed
than 304 rpm, the soft start mode is skipped and goes to
steady rotation mode immediately.
The LV8324C has various functions and parameters
which are defined by built-in registers. Refer to the Register
map and description page for the detail.
Spin-up Sequence
To spin-up a motor, power is applied to VCC pin and the
appropriate input PWM signal (see “DUTY_L”
and“DUTY_S” setting description in section “Steady
Rotation”) is applied to PWM pin. The LV8324C starts
driving the motor whose current direction is determined by
the Hall sensor signal. In this sequence, the wait time for
spin-up is adjustable by “ST_DLY_TIM” which set the time
to ignore PWM signal as shown in Table 9. This setting is
stored to NVM. In the wait time, both OUT1 and OUT2 are
Hi-Z and other circuits are active. After the wait time, OUT1
and OUT2 are active.
Soft Start
For soft start mode, the duty-cycle ramp up profile is
defined by the initial duty-cycle, slope, and exit condition.
The initial duty-cycle is fixed and it starts from 4%. The
slope is programmable. It is determined by registers
“SSTART_SEL” and “INCTIM”. The duty-cycle is
increased up to the end duty-cycle “SSTART_SEL” for
duration time “INCTIM”. The end duty-cycle is selectable
at 0%, 24%, 54% or 80% (see Table 10). The duration time
can be selected from 0.0002 sec to 15.2 s (see Table 11). The
exit condition means it’s in the state of either the duty-cycle
reaches “SSTART_SEL”. Soft start operation requires at
least 8 electrical cycles (4 mechanical cycles in case of
4 poles single phase motor) independent on the exit
condition.
Table 9. PWM INPUT IGNORE TIME
ST_DLY_TIM
PWM Input Ignore Time [s]
0
1
2
3
0
0.5
1.0
1.5
Table 10. SOFT START END DUTY-CYCLE
SSTART_SEL
End Duty-cycle
0% output duty-cycle (Disable Soft Start)
24% output duty-cycle
0
1
2
3
To avoid the unnecessary rush current, the “soft start”
mode is provided, which gradually increases output
duty-cycle. After the soft start mode, LV8324C goes to
steady rotation mode. The detail of the soft start mode and
steady rotation mode are described in the sections below.
In addition, soft switch function in start-up mode is
available. In case of “SS_SW_SEL = 0”, falling time of
54% output duty-cycle
80% output duty-cycle
Table 11. SOFT START DURATION TIME
INCTIM
Duration Time (s)
SSTART_SEL = 1
SSTART_SEL = 2
SSTART_SEL = 3
(End Duty-cycle = 24%)
(End Duty-cycle = 54%)
(End Duty-cycle = 80%)
[2]
0
[1]
0
[0]
0
SSTART_SEL = 0
0
0
0
0
0
0
0
0
0.0002
0.48
0.96
1.50
2.00
3.00
5.00
10.0
0.10
0.50
1.00
1.50
2.00
3.00
5.00
10.0
0.15
0.76
1.52
2.28
3.04
4.56
7.60
15.2
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
www.onsemi.com
9
LV8324C
Figure 3 shows the image of soft start mode.
by INCTIM
4
time [s]
by INCTIM
4
time [s]
Figure 3. The Image of Soft Start Exit by End Duty-cycle
As the green curve shown in Figure 3, the output
duty-cycle in the soft start mode starts from 4% of the output
duty. Then the output duty-cycle is increased to the end
duty-cycle linearly, which is shown by yellow circle. After
that, LV8324C goes to the steady rotation mode.
Figure 4 is the example of the duration time in case of
“SSTART_SEL = 3”.
In case of “SSTART_SEL = 0”, the output duty-cycle
increases according to the input duty-cycle and the setting of
registers which are “PWM_ROC” and “STEPSEL”. About
these registers, see the section “Output duty cycle
transitions” and Table 13 for more detail.
Figure 4. Example: The Image of Soft Start Duration
Time in Case of SSTART_SEL = 3
www.onsemi.com
10
LV8324C
Steady Rotation
The motor speed is defined by the output duty−cycle
which is controlled by input PWM pin.
The input PWM frequency range is 25 Hz−80 kHz. The
output frequency is fixed to 48 kHz and it is not related to
input PWM frequency. Figure 5 shows the output duty-cycle
control profile which is relationship between input PWM
duty-cycle and the target output duty-cycle. Registers to
determine this relationship are;
• TAG_L (Address 0x0100 D [7:0]):
Minimum output duty-cycle
• TAG_H (Address 0x0101 D [7:0]):
Maximum output duty-cycle
• DUTY_L (Address 0x0102 D [7:0]):
Minimum input duty-cycle
• DUTY_H (Address 0x0103 D [7:0]):
Maximum input duty-cycle
• FULL (Address 0x0108 D [6]):
Output duty-cycle selection at input duty-cycle over
DUTY_H
• DUTY_S (Address 0x0109 D [3:0]):
Output duty-cycle selection at input duty-cycle under
DUTY_L
Figure 5. Target Output Duty-cycle Control Profile
Variable max.
output duty−cycle
(DUTY_H, TAG_H)
The detail of each register will be explained later.
TAG_L/TAG_H: Minimum/Maximum Target Output
Duty-cycle Setting
(DUTY_L, TAG_L)
The minimum output duty-cycle is set by “TAG_L” and
the maximum output duty-cycle is set by “TAG_H” within
the range of DUTY_L and DUTY_H (See Figure 6).
Do not set the maximum output duty-cycle setting
(TAG_H) less than the minimum output duty-cycle setting
(TAG_L).
Variable min.
output duty−cycle
DUTY_L
DUTY_H
Input PWM duty [%]
100%
0%
DUTY_L/DUTY_H: Minimum/Maximum Input
Duty-cycle Setting
The range of PWM input duty-cycle can be set by the
registers “DUTY_L” and “DUTY_H” whose range is 0 to
100%. The equation of resolution is
Figure 6. Max/Min Speed Setting
DUTY_L
Dmit
+
100 [%]
(eq. 2)
255
DUTY_H
255
Dmax
+
100 [%]
(eq. 3)
Where:
D
D
is minimum input duty-cycle.
is maximum input duty-cycle.
min
max
Do not set “DUTY_H” less than “DUTY_L”.
Figure 7 shows the relationship between input duty-cycle
and target output duty-cycle. TAG_L/TAG_H define the
start and end points of the output duty-cycle curve and the
value between (DUTY_L, TAG_L) and (DUTY_H,
TAG_H) are interpolated linearly.
Figure 7. Input Duty-cycle Setting
www.onsemi.com
11
LV8324C
FULL: Output Duty-cycle Selection at Input Duty-cycle
over DUTY_H
Table 12. THE SETTING OF DUTY_S
DUTY_S
Motor Stop Duty Setting (%)
For the behavior at input duty-cycle which is over
DUTY_H, the register “FULL” provides two options.
FULL = 0 is to keep the output duty-cycle specified by
“TAG_H” and FULL = 1 is to go to 100% output duty-cycle
as shown in Figure 8.
0
1
0
1.9
2
3.9
3
5.8
4
7.8
5
9.8
6
11.7
7
13.7
8
15.6
9
17.6
10
11
12
13
14
15
19.6
21.5
23.5
25.4
27.4
The value of DUTY_L
When DUTY_S = 15, the threshold duty-cycle is same as
the “DUTY_L” setting.
Figure 8. Max Speed Function Setting
When DUTY_S = 1 to 14, the output duty-cycle keeps
“TAG_L” setting from “DUTY_L” to “DUTY_S” and goes
to 0 % at defined by Equation 2.
When DUTY_S = 0, the output duty keeps “TAG_L”
setting whenever input duty-cycle is less than “DUTY_L”.
If “DUTY_L” setting is smaller than “DUTY_S” setting,
the threshold is same as “DUTY_L” setting.
To restart the motor rotation, the input duty-cycle must be
set higher than “DUTY_S” + 1.6% (i.e. the hysteresis is
1.6%).
DUTY_S: Output Duty-cycle Selection at Input
Duty-cycle under DUTY_L
For the behavior at input duty-cycle less than DUTY_L,
the register “DUTY_S” provides several options.
The “DUTY_S” sets the input duty cycle of the output
duty-cycle to 0%. It is calculated by Equation 4, except for
the case of “DUTY_S” = 15.
5 DUTY_S
D0
+
100 [%]
(eq. 4)
255
Where D is input duty-cycle of the motor speed 0 rpm.
0
Figure 9 shows the speed curves for various “DUTY_S”.
Table 12 shows the option of “DUTY_S”.
Figure 9. Min Speed Function Setting
www.onsemi.com
12
LV8324C
Output Duty Cycle Transitions
Output Waveform
When PWM input duty cycle changes, output PWM target
duty changes along with input and output characteristics
setting. The rate that actual output duty cycle changes is set
by the register “STEPSEL” and “PWM_ROC”. In case of
STEPSEL = 0, actual output duty cycle changes
immediately to the target. In case of STEPSEL = 1, actual
output duty cycle transfers gradually to the target according
to the rate which is defined by PWM_ROC as shown in
Table 13. In addition, this register setting is effective not
only in changing the input duty cycle but also in changing
the mode from Start-up to normal.
The output pulse signal is about 0 V−V . The duty
CC
before commutation change decreases gradually to 0% and
the duty after commutation change increases gradually to
the duty level controlled by speed control function by
built-in function called Soft Switch. This state is shown in
Figure 10 as a schematic view.
Soft Switch Setting
The LV8324C can adjust soft switch period as the ratio of
L and S shown in Figure 11. It is defined by Equation 5 and
Register “SSWHIGH” and “SSWLOW” can adjust it.
S
L
Soft Switch Period [%] + 100
(eq. 5)
Table 13. RATE OF CHANGE FOR OUTPUT DUTY
Where:
S is Soft Switch period.
L is one commutation period.
STEPSEL PWM_ROC
Rate of Change for Output Duty
Change immediately to the target
0.1% per 64 output PWM pulses
0.1% per 128 output PWM pulses
0.1% per 256 output PWM pulses
0.1% per 512 output PWM pulses
0
1
1
1
1
x
0
1
2
3
Figure 11 shows the soft switch image.
Due to the Soft switch, the averaged output voltage is
shown in the blue in Figure 11.
NOTE: x: Don’t care
Figure 10. Output Waveform
Output
averaged
voltage
Figure 11. L (Length) and S (Soft Switch)
www.onsemi.com
13
LV8324C
p
2
N
60
SSWHIGH is for the maximum output duty-cycle defined
fFG [Hz] +
(eq. 6)
by TAG_H and SSWLOW is for the minimum output
duty-cycle defined by TAG_L. Each register has 4 bits and
Table 14 shows the adjustable value.
Where:
N is motor speed [rpm].
p is number of Pole.
Table 14. SOFT SWITCH PERIOD ADJUSTMENT
Figure 13 shows the timing chart of the hall sensor output
and the FG output.
SSWHIGH
SSWLOW
SSWHIGH
SSWLOW
S/L Ratio
2.9%
S/L Ratio
26.4%
29.3%
32.2%
35.2%
38.1%
41.0%
43.9%
46.9%
0
1
2
3
4
5
6
7
8
5.9%
9
8.8%
10
11
12
13
14
15
11.7%
14.6%
17.6%
20.5%
23.4%
Once “SSWHIGH” and “SSWLOW” are set, the ratio of
Soft Switch in other speed settings is as shown in Figure 12.
FG Output
FG signal output is decided by the Hall signal cross point.
The relationship between motor speed and FG frequency
represents the following equation.
Figure 12. The Relationship between Soft Switch
and Speed
Figure 13. Timing Chart of Output
www.onsemi.com
14
LV8324C
Lead Angle Setting
In the output, the output current delays from the output
voltage because of the inductance of motor coil. The output
current which flows in a motor coil generates torque for the
motor and the torque is maximized by the synchronization
of output current with the BEMF phase. Therefore, this
delay decreases an efficiency of motor rotation. It is
generally increased in proportion to the rotational speed.
The LV8324C can cancel the delay by earlier
commutation than the Hall sensor signal as shown in
Figure 14. This phase adjustment is called the “Lead-angle”.
In Figure 14, when the output voltage VOUT1 and the
output current IOUT1 in black are changed to the waveform
in red after the Lead-angle adjustment and it is the most
optimum commutation timing.
Figure 14. The Relationship between the Lead-angle and the Delay of Output Current
The relationship between output duty-cycle and
Lead-angle is shown in Figure 15. The optimum Lead-angle
will vary by the motor characteristics so it is necessary to
adjust the Lead-angle based on the motor in use.
The LV8324C can set the Lead-angle at maximum target
output duty-cycle (TAG_H) and at minimum target output
duty-cycle (TAG_L) by “DLDEG_H” and “DLDEG_L”
individually. These register have 8 bits D[7:0] in each and
both MSBs define the direction of phase delay. When MSB
sets to “0”, the Lead-angle is set to minus value which means
phase delay, that is, the output voltage commutation is delay
than the Hall sensor signal. When MSB sets to 1, the
Lead-angle is set to plus value which means phase advance,
that is, the output voltage commutation is earlier than the
Hall sensor signal. The resolution is approximately 0.175°.
Hence, the adjustable range of both is from −22.225° to
22.225° expressed in the following equation.
22.225
Lmax
+
DLDEGH [deg]
(eq. 7)
127
22.225
127
Lmin
+
DLDEGL [deg]
(eq. 8)
Where:
L
is Lead-angle at maximum target output duty-cycle
max
(TAG_H)
L
is Lead-angle at minimum target output duty-cycle
min
(TAG_L)
Once DLDEG_H and DLDEG_L are set, the Lead-angle
in other output duty-cycle is set to interpolated and
extrapolated value according to the output duty-cycle, even
though the output duty-cycle is defined by FULL = 1.
TAG_L
TAG_H
Figure 15. Lead-angle Curve Image
www.onsemi.com
15
LV8324C
Protections
Table 17. RDA CLEAR SPEED
The LV8324C has the following protection functions:
RDA_HYS
RDA Clear Speed
• TSD (Thermal Shut Down)
• UVLO (Under Voltage Lock Out)
• RDA Detection
• Lock Protection
• CLM (Current Limiter)
• OCP (Over Current Protection)
0
1
2
3
Detection speed + (Detection speed) × 1/16
Detection speed + (Detection speed) × 1/8
Detection speed + (Detection speed) × 1/4
Detection speed + (Detection speed) × 1/2
This detection is masked in Spin-up sequence and in the
input duty lower than the “Available duty” which is defined
by RDA_MASK. The “available duty” is calculated by
following equation.
When the TSD or Lock protection works, all of the
internal FETs are turned off. When UVLO or CLM works,
the output PWM is off and the motor goes to re-circulation
mode.
Available Duty [%] + N 4
(eq. 9)
Thermal Shutdown Protection (TSD)
Where:
N is value of RDA_MASK
When LV8324C junction temperature rises to 180°C,
TSD will activate and turns off high-side and low-side
Power FET. Therefore, OUT1 and OUT2 will become high
impedance and the coil current will shut off. When it falls
under 140°C, TSD will deactivate and motor will start to
rotate.
Hence, the “Available duty” is set from 0% to 60% by 4%
step. Figure 16 shows the image of RDA detection.
Under Voltage Lock Out (UVLO)
When VCC voltage goes to low level (5.2 V), UVLO will
active and stop the motor. VCC voltage is recovered to above
5.6 V.
The TRUTH TABLE of Operating State with UVLO is as
shown in Table 15.
Table 15. UVLO TRUTH TABLE
Input
Register
DRVMODE
00 / 01
Output
OUT1
IN1
L
IN2
H
OUT2
Hi-Z
L
L
H
L
00 / 01
Hi-Z
Figure 16. The Image of RDA Detection
RDA (Rotation Decline Alarm) Detection
Lock Detection and Lock Protection
When motor rotational speed is lower than the threshold,
the detect signal is output from FG pin. This function is
called “RDA detection”. When the LV8324C detects it, FG
pin goes to high and “RDA” register (Address 0x020A,
D[3]) posts 1. This detection is enable by “TACHSEL”=1.
Motor rotational speed is calculated with hall signal cycle
and the threshold is defined by “RDA_DET” as shown in
Table 16.
When the motor is locked, the heat is continuously
generated because the LV8324C keeps trying to rotate the
motor.
The lock protection works to prevent such a heat
generation by turning OUT1 and OUT2 into high impedance
and shutting off the motor current. When a motor is locked
in the steady rotation mode and the LV8324C doesn’t detect
the FG edge for more than 0.3 s which is equivalent to
50 rpm, the lock protection works (Figure 17).
The lock protection signal can be output from FG pin by
setting the register “TACHSEL”. In this mode, the RD signal
goes to “High”, though it is “Low” at motor starts.
When the motor restarts and IC detects 4 phase changes
at least (depends on rotation speed), the RD signal goes to
“Low”.
Table 16. RDA THRESHOLD SPEED SETTING
RDA_DET
0 to 15
RDA Threshold Speed Setting
100 rpm step from 500 rpm to 2000 rpm
200 rpm step from 2200 rpm to 11600 rpm
16 to 63
When motor rotational speed is higher than the threshold,
RDA is cleared. The threshold of rotational speed to release
RDA is defined by “RDA_HYS”.
www.onsemi.com
16
LV8324C
Figure 17. Timing Chart of the Lock Protection
The period of motor lock protection is adjustable and is
defined by “RESTART_INT” as shown in Table 18.
Table 19. STAND-BY PERIOD FOR FG
LOCK_DET
Stand-by Period for FG [s]
0
1
2
3
0.4
0.7
Table 18. MOTOR LOCK PROTECTION PERIOD
RESTART_INT
Motor Lock Protection Period [s]
0.85
0.95
0
1
2
3
3.5
5.5
7.7
9.0
Figure 18 shows the relationship between protection
period and the number of protection times. The 1 to 4
st
th
protection period take a time set by “RESTART_INT” and
5 protection period takes 14 s. To reset the lock protection
mode, Stop duty cycle must be applied to the PWM input
signal. To retry the motor rotation, Proper duty cycle must
be applied to the PWM input signal.
th
After the period of motor lock protection, the LV8324C
tries to rotate the motor and stand-by for FG edge for
a certain period defined by “LOCK_DET” as shown in
Table 19.
Figure 18. The Relationship between Protection Time and the Number of Protection Times
www.onsemi.com
17
LV8324C
These protection periods and the number of protection
is entered during lock protection period. In this case, the lock
protection counter will activate from the initial state starting
from PWM Pos−Edge and protection period will start from
1st time as shown in Figure 19 and Figure 20.
times are applied in accordance with the internal counter. It
will reset the counter if the duty−cycle which sets the motor
speed to 0 rpm determined by “DUTY_L” and “DUTY_S”
Figure 19. Lock Protection Counter Reset during 3.5 Sec Lock Protection Period
Figure 20. Lock Protection Counter Reset during 14 Sec Lock Protection Period
The lock protection period is changed by the condition of
restart period is applied immediately when PWM Pos−Edge
will be input as shown in pink in Figure 21. In this case, the
protection period is not related to the internal lock protection
timer and protection period is not fixed to 3.5 sec or 14 sec.
output signal. If the duty−cycle which sets motor speed to 0
rpm is input and the output signals are disappeared during
the restart period in lock protection period as shown in light
blue in Figure 21, the counter is not reset and the remaining
www.onsemi.com
18
LV8324C
Figure 21. In Case of having Changes in Protection Period
www.onsemi.com
19
LV8324C
Current Limiter (CLM)
When the coil current becomes large, CLM will activate
and then output will be in the re-circulation state. The
current is monitored by RF pin and the threshold is 100 mV.
There are three registers related to the current limiter
function. The first one is CL_SKIP which can set the period
of protection operation when CLM is detected. The second
one is CL_ASYNC. When “1” is set to this register while
CLM is active, synchronous rectification of the output
becomes disabled. The third one is OCP_MASK which sets
the masking time to ignore upper and lower FET’s reverse
recovery. Table 20 shows the mask time.
Standalone
Table 20. CLM MASK TIME
OCP_MASK
CLM Mask Time [ms]
0
1
2
3
0.5
1.0
2.0
4.0
Overcurrent Protection (OCP)
Figure 22. Image of the Internal Register and
Nonvolatile Memory
OCP monitors the coil current by RF pin and if it becomes
larger than 150 mV even if CLM is activated, OCP works to
prevent the device or motor from breakdown. OCP
operation is to turn OUT1 and OUT2 into high impedance
and to shut off the motor current.
Serial Interface
The LV8324C allows communication via UART
(Universal Asynchronous Receiver Transmitter). Various
parameter registers can be accessed through UART
communication.
This function has also the mask time same as CLM
function shown in Table 20.
Register called OCP_LAT_CLR allows to select behavior
when OCP is activated. One is to keep the motor stopped
until the next power on sequence, and the other one is to
activate Lock protection mode.
UART is one to one communication and the LV8324C
doesn’t support parallel access to the multiple devices, so be
sure to turn on only the target devices.
The LV8324C provides two UART modes, a one-wire
mode and a two-wire mode. In one-wire mode, the FG pin
is used for both input and output. In two-wire mode, the FG
pin is used as output and the PWM pin is used as input. The
state of the TSL pin defines the UART mode as shown in
Table 21.
Nonvolatile Memory
The LV8324C has internal nonvolatile memory which can
store register values which define various parameters and
settings. The stored register values will be reloaded at POR
shown as Figure 22. LV8324C has also the communication
mode. It allows user to modify register values, and to store
them to the nonvolatile memory (Figure 22). It doesn’t need
the resistors as like the conventional models to set the
various review. In addition, PCB design becomes simpler.
Here is a list of the main configurable items:
Table 21. I/O PIN CONDITION IN UART MODE
One-wire Mode
Two-wire Mode
TSL pin
Pull down (GND)
Pull-up (VDD)
Communi-
cation Pin
FG pin (for Read
and Write)
PWM pin (for Write)
FG pin (for Read)
• Max/Min Output duty-cycle
• Max/Min input duty-cycle
• Lead-angle
Figure 23 shows the connection image of one-wire mode.
The communication line FG should be open-drain type
because it supports duplex mode. Therefore the
communication pin of the MPU or CPU must be an
open-drain output. Figure 24 shows the connection image of
two-wire mode. Please refer to the Application note
AND9761/D for the detail.
• Soft start
Program/Erase to the memory is performed through
a built-in register. Please note that Program/Erase is allowed
for 10 times only. For the detail, please see the application
note “NVM Programming Procedure”.
www.onsemi.com
20
LV8324C
Figure 23. Connection Image of One-wire Mode UART
Figure 24. Connection Image of Two-wire Mode UART
About the detail of communication protocol, please see the Application note, AND9761/D.
www.onsemi.com
21
LV8324C
REGISTER MAP
Register MAP
Internal register map can be classified into four types as shown in Table 22 and 23.
Read Only
Read/Write, User defined registers to be written to nonvolatile memory.
Read/Write
Write Only (Auto Clear)
Table 22. REGISTER MAP 1 (ADDRESS 0x0000−0x0116)
Register
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
D0
0
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
0x010A
0x010B
Initial
0xAA
0x55
0x00
0x00
0x00
0x10
0x00
0xFF
0x00
0xFF
0x00
0x00
0x66
0x01
0xA4
0x00
0x02
0x02
1
0
1
0
1
0
1
0
1
0
0
RECALC_EN
RELOAD_EN
RELOAD
RECALC
Identification Number
TAG_L[7:0]
TAG_H[7:0]
DUTY_L[7]
DUTY_H[7]
DUTY_L[6:0]
DUTY_H[6:0]
DLDEG_L[7:0]
DLDEG_H[7:0]
SSWHIGH[3:0]
SSWLOW[3:0]
0
PWMIN_INV
0
DRVMODE[0]
STEPSEL
Reserved
FULL
SS_SW_SEL
SSTART_SEL[1:0]
INCTIM[2:0]
DUTY_S[3:0]
DTIME[1:0]
CL_SKIP
CL_ASYNC
OCP_LAT_
CLR
0x010C
0x010D
0x010E
0x010F
0x00
0x00
0x02
NA
TACHSEL[1:0]
PWMAV[1:0]
OCP_MASK[1:0]
0
0
0
0
ON_
0
INTERNAL
0x0110
0x0111
0x0112
0x0113
0x0114
0x0115
0x0116
0x00
0x00
0x0A
0xF0
0x40
NA
LOCK_FAULT
0
0
0
0
0
0
0
MSKDEG_TP[3:0]
0
1
PWM_ROC[1:0]
LOCK_DET[1:0]
RDA_HYS[1:0]
RESTART_INT[1:0]
RDA_MASK[3:0]
RDA_DET[5:0]
ON_INTERNAL
0x08
ST_DLY_TIM[1:0]
0
0
Table 23. REGISTER MAP 3 (ADDRESS 0x0219)
Register
D7
D6
D5
D4
D3
D2
D1
D0
Address
Key
Initial
0x0219
Free
0x00
SWI_ERR[6:0]
Registers in the black cells do not exist. Therefore, these
registers cannot be written and the read values are always
zero. The bits with numeric values (0 or 1) must remain as-is.
There are some register addresses which contain both the
bits stored in NVM and the bits not stored in NVM. Confirm
the bit types to save the data to NVM.
www.onsemi.com
22
LV8324C
Register Description
Table 24. REGISTER ADDRESS 0x0000−0x0005 − REGISTER DESCRIPTION 1
Function
Fixed Register 1
Fixed Register 2
Address
0x0000
0x0001
Bits
[7:0]
[7:0]
Register Name
Description
Data of 0xAA are stored. (Read only)
Data of 0x55 are stored. (Read only)
−
−
This register enable re-calculation of
Speed/Lead Angle/Soft SW setting.
0: Disable
Enable Re-calculation
0x0002
[1]
RECALC_EN
1: Enable
This register enables data reloading from NVM.
0: Disable
1: Enable
Register Re-loading
(Memory to Register)
0x0002
0x0003
[0]
[0]
RELOAD_EN
RELOAD
When this bit is set to 1, data reloading from NVM is
executed while RELOAD_EN is set to 1.
Register Re-loading
(Memory to Register)
This register is auto clear type.
When this bit is set to 1, re-calculation of Speed/Lead
Angle/Soft SW setting is executed while RECALC_EN is
set to 1.
Trigger of Re-calculation
Device ID
0x0004
0x0005
[0]
RECALC
This register is auto clear type.
[7:0]
ID_NUMBER
Data of device ID are stored. (Read only)
Table 25. REGISTER ADDRESS 0x0100−0x0116 − REGISTER DESCRIPTION 2
Function
Address
Bits
Register Name
Description
These registers set minimum/maximum output duty−cycle.
Minimum Speed Setting
0x0100
[7:0]
TAG_L
TAG_L\TAG_H = 0 to 250
Output duty_cycle (%) = TAG_L\TAG_H x 0.4
TAG_L\TAG_H = 251 to 255
Output duty_cycle (%) = 100
* Refer to the section “Steady Rotation” for details.
Maximum Speed Setting
0x0101
0x0102
0x0103
0x0104
[7:0]
[7:0]
[7:0]
[7:0]
TAG_H
DUTY_L
DUTY_H
DLDEG_L
These registers set minimum input duty-cycle.
Minimum Input Duty
Cycle Setting
0000 0000: Duty 0%
0111 1111: Duty 49.8%
These registers set maximum input duty-cycle.
Maximum Input Duty
Cycle Setting
1000 0000: Duty 50.2%
1111 1111: Duty 100%
This register adjusts lead-angle at rotational speed set by
TAG_L.
Lead-angle Setting at
Minimum Speed
000 0000: 0 degree,
111 1111: −22.225 deg (DLDEG_L[7] = 0)
000 0000: 0 degree,
111 1111: +22.225 deg (DLDEG_L[7] = 1)
This register adjusts lead-angle at rotational speed by
Lead-angle Setting at
0x0105
[7:0]
DLDEG_H
TAG_H.
Maximum Speed
000 0000: 0 degree,
111 1111: -22.225 deg (DLDEG_H[7] = 0)
000 0000: 0 degree,
111 1111: +22.225 deg (DLDEG_H[7] = 1)
Soft switch width is set at output duty-cycle set by TAG_H.
0000: 2.9% equivalency of one commutation period.
1111: 46.9% equivalency of one commutation period.
Soft Switch Width Setting
at Maximum Output
Duty-cycle
0x0106
0x0106
[7:4]
[3:0]
SSWHIGH
SSWLOW
Soft switch width is set at output duty-cycle set by TAG_L.
0000: 2.9% equivalency of one commutation period.
1111: 46.9% equivalency of one commutation period.
Soft Switch Width Setting
at Minimum Output
Duty-cycle
www.onsemi.com
23
LV8324C
Table 25. REGISTER ADDRESS 0x0100−0x0116 − REGISTER DESCRIPTION 2 (continued)
Function
Address
Bits
Register Name
Description
Control slope polarity for input duty-cycle is changed.
Speed Control Slope
Invert
0x0107
[2]
PWMIN_INV
0: Normal mode (Low duty-cycle is low speed rotation)
1: Invert mode (Low duty-cycle is high speed rotation)
This register selects synchronous/asynchronous drive.
Sync/Async Drive Select
0x0107
[0]
DRVMODE
00: High-side switching is PWM. Low-side switching is
asynchronous
01: High-side switching is PWM. Low-side switching is
synchronous
Reserved
0x0108
0x0108
[7]
[6]
Reserved
FULL
Must be kept as 1
This register defines the output behavior when input PWM is
greater than the duty cycle set by DUTY_H.
Maximum Speed
Setting 2
0: Fixed speed set by TAG_H
1: Fixed duty cycle of 100% with soft switch
This register sets soft switch period in soft start mode.
0: Rise 2.5 ms, Fall 5 ms
1: Rise 1.25 ms, Fall 2.5 ms
Soft Switch Mask Time
Select
0x0108
0x0108
[5]
SS_SW_SEL
This register sets Soft start end duty-cycle.
Soft Start End Duty-cycle
[4:3]
SSTART_SEL[1:0]
0: 0% output duty-cycle (Disable Soft Start)
1: 24% output duty-cycle
2: 54% output duty-cycle
3: 80% output duty-cycle
Soft Start Release Time
Minimum Speed Setting 2
0x0108
0x0109
[2:0]
[3:0]
This register sets the soft start duration time.
INCTIM
This register sets the various speed when input duty-cycle is
less than DUTY_L.
DUTY_S
This register sets dead time in synchronous rectification
drive.
Dead Time setting
0x010A
[1:0]
DTIME
00: 125 ns
01: 250 ns
10: 500 ns
11: 0 ns
This register sets disable period of motor current when CLM
is active.
0: only for corresponding PWM pulse
1: for corresponding and next PWM pulse
Disable Period of Motor
Current in CL
0x010B
0x010B
[3]
[2]
CL_SKIP
This register disables motor synchronous rectification when
CLM is active.
0: Synchronous rectification is not disable when CLM is
active.
Disable Motor
Synchronous
Rectification in CL
CL_ASYNC
1: Synchronous rectification is disable until detecting Hall
signal or motor stop signal when CLM is active. After
detecting Hall signal or motor stop, synchronous
rectification is enabled.
This register selects the status when OCP is activated.
0: The motor stops until next power on sequence.
1: The IC goes to “Lock Protection mode”.
Condition to Enter Lock
Protection Mode in OCP
Active
0x010B
0x010B
[1]
[0]
OCP_LAT_CLR
STEPSEL
To prevent drastic changes of a target speed in the closed
loop control, this register selects slopes of the target speed
change against the input duty cycle change. (The amount is
prescribed in the time per 1FG pulse)
Speed Control Slope
Setting
0: 1/4 of the existing speed, or 2047 rpm
(smaller one is chosen)
1: 1/8 of the existing speed, or 1023 rpm
(smaller one is chosen)
This register sets FG pin function.
00: FG output
01: RDA output
FG/RD Select
0x010C
[1:0]
TACHSEL
10: RD output (Rotation is Low, Locked motor is High)
11: RD output (Rotation is High Locked motor is Low)
www.onsemi.com
24
LV8324C
Table 25. REGISTER ADDRESS 0x0100−0x0116 − REGISTER DESCRIPTION 2 (continued)
Function
Address
Bits
Register Name
Description
The number of times to perform averaging for input PWM
duty cycle.
Input PWM Average
Setting
0x010D
[1:0]
PWMAV
00: Not averaged
01: Averaged 4 times
10: Averaged 8 times
11: Averaged 16 times
This register sets the masking time to ignore the reverse
recovery for both high-side and low-side Power FET.
Mask Time for Reverse
Recovery Time Setting
0x010E
[1:0]
OCP_MASK
00: 0.5 ms
01: 1.0 ms
10: 2.0 ms
11: 4.0 ms
This register selects enable or disable of the lock protection
function.
0: Lock protection enable
1: Lock protection disable
Lock Protection Enable
OFF Time Setting (TOP)
0x0110
0x0111
[3]
LOCK_FAULT
MSKDEG_TP
This register sets off period at commutation initiation. It is
selected as follows:
[7:4]
[7]
0: In angle
1: In time
[6:4]
000: 0 deg or 0 s
001: 0.35 deg or 2.0 ms
010: 0.70 deg or 4.0 ms
011: 1.05 deg or 10.0 ms
100: 2.10 deg or 14.0 ms
101: 3.50 deg or 20.0 ms
110: 4.90 deg or 28.0 ms
111: 7.00 deg or 40.0 ms
This register sets the increment ratio of the output-duty in
case of “STEPSEL=1”.
00: 0.1% per 64 pulses
01: 0.1% per 128 pulses
10: 0.1% per 256 pulses
11: 0.1% per 512 pulses
Increment Ratio of the
Output-duty
0x0112
0x0113
0x0113
[1:0]
[7:6]
[5:4]
PWM_ROC
LOCK_DET
This register sets standby period for FG pulse in Lock
protection.
00: 0.4s
01: 0.7s
10: 0.85s
11: 0.95s
Standby Period for FG
Pulse in Lock Protection
This register sets Lock protection period.
Lock Protection Period
RESTART_INT
00: 3.5 s
01: 5.5 s
10: 7.7 s
11: 9.0 s
This register sets the input duty-cycle to mask RDA. See
(eq. 9) to calculate the output duty-cycle of RDA MASK.
Threshold of RDA MASK
RDA Release Threshold
0x0113
0x0114
[3:0]
[7:6]
RDA_MASK[3:0]
RDA_HYS
This register sets the threshold of RDA release.
00: Detection speed + (Detection speed) × 1/16
01: Detection speed + (Detection speed) × 1/8
10: Detection speed + (Detection speed) × 1/4
11: Detection speed + (Detection speed) × 1/2
This register sets the threshold of RDA detection.
RDA Detection Threshold
0x0114
[5:0]
RDA_DET
0−15: 100 rpm step from 500 rpm to 2000 rpm
16−63: 200 rpm step from 2200 rpm to 11600 rpm
www.onsemi.com
25
LV8324C
Table 25. REGISTER ADDRESS 0x0100−0x0116 − REGISTER DESCRIPTION 2 (continued)
Function
Address
Bits
Register Name
Description
Ignore Time of PWM
Input Duty Cycle
0x0116
[3:2]
ST_DLY_TIM
This register sets the ignore time of PWM input duty-cycle.
00: 0 s
01: 0.5 s
10: 1.0 s
11: 1.5 s
Table 26. REGISTER ADDRESS 0x0219 REGISTER DESCRIPTION
Function
Address
Bits
Register Name
Description
Communication Error
Status
0x0219
[6:0]
SWI_ERR
Communication error status store to these registers.
(Read only)
Refers to the section “COMMUNICATION ERROR” for
details.
Communication Error
The Communication error is reported in the Register (Address 0x0219). Table 27 shows the error report functions.
Table 27. ERROR REPORT DESCRIPTION
State after Error
Transferred
DRV
MODE
Data
Mode
Communication
Address
Bit
Error Description
0x0219
D[6]
R/W Field Data Error
Non-zero value is written
in the D[5:1] in R/W Field
Wait for the
data from the
master
Enable
In write mode;
Nullified
In read mode;
No action
D[5]
Time Out Error
The delay between the
fields in “Communication
mode” is longer than 3
fields
“Standby”
Terminated
−
D[4]
D[3]
D[2]
Checksum Error
Checksum value is wrong
in write mode
“Error”
“Error”
“Error”
Terminated
Terminated
Terminated
Nullified
Nullified
Nullified
Data Length Field Par-
ity Error
The parity in “Data Length
Field” is wrong
R/W Field Parity Error
The parity in “R/W Field”
is wrong
D[1]
D[0]
Header Error
Framing Error
Header input is not correct
“Error”
“Error”
Terminated
Terminated
Nullified
Nullified
The signal pin is “Low”
state in Stop bits
www.onsemi.com
26
LV8324C
When “Time out error” posts “1” in D[5] of register
mode” as well. To recover from “Error mode”, the
communication pin should be kept “High” for longer than
the time corresponding to 4 “Fields”, then the LV8324C
goes to “Standby mode” automatically despite of the status
of error register.
0x0219, the LV8324C goes into standby mode.
If the data length is long and the “Time out Error” is
happened during the Register write, the data with the correct
“Checksum” transferred before the “Time out Error” is
stored in register, then the LV8324C goes to “Standby
mode”.
Each error register keeps the error bit until the master
reads the error register.
When “Checksum error” posts “1” in D[4] of Register
0x0219 while in the Write mode, the LV8324C goes into
Error mode and the communication is terminated. In this
case, the transferred data is discarded but the data with
correct “Checksum” transferred before the “Checksum
error” is stored in the register.
Reading Reg. 0x0219 as 1 byte will clear the error bits.
Multiple read will not clear the error bits.
It is recommended to read the error register after every
transaction to confirm that the communication is completed
successfully.
Figure 25 shows the state diagram. Refer to the
application note AND9761/D as well for more information
regarding the communication.
Other errors, except for “R/W Field Data Error” also write
“1” in the specified register and the LV8324C goes to “Error
Figure 25. State Transition Diagram of Each Error
www.onsemi.com
27
LV8324C
PACKAGE DIMENSIONS
TSSOP−14 EP
CASE 948AW
ISSUE C
NOTES:
NOTE 6
NOTE 5
B
14
8
b
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
b1
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADI-
US OF THE FOOT. MINIMUM SPACE BETWEEN PRO-
TRUSION AND ADJACENT LEAD IS 0.07.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 mm PER SIDE. DIMENSION D IS DETERMINED AT
DATUM H.
c1
E1
E
SECTION B−B
c
NOTE 8
PIN 1
1
7
0.20 C B A
REFERENCE
e
2X 14 TIPS
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM
THE SEATING PLANE TO THE LOWEST POINT ON THE
PACKAGE BODY.
TOP VIEW
NOTE 6
A
D
A2
NOTE 4
A
DETAIL A
0.05 C
B
M
0.10 C
8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mm
FROM THE LEAD TIP.
14X
b
0.10 C B
S
S
C
SEATINGc
PLANE
14X
A
MILLIMETERS
NOTE 3
B
DIM MIN
MAX
1.20
0.15
1.05
0.30
0.25
0.20
0.16
5.10
3.62
END VIEW
A
A1
A2
b
b1
c
c1
D
D2
E
−−−−
0.05
0.80
0.19
0.19
0.09
0.09
4.90
3.09
SIDE VIEW
D2
H
L2
C
6.40 BSC
E2
E1
E2
e
4.30
2.69
0.65 BSC
4.50
3.22
A1
NOTE 7
L
GAUGE
PLANE
DETAIL A
L
L2
M
0.45
0
0.75
0.25 BSC
8
_
_
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
14X
3.40
1.15
3.06
6.70
1
14X
0.42
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
28
LV8324C
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
ON Semiconductor Website: www.onsemi.com
◊
www.onsemi.com
相关型号：
©2020 ICPDF网 联系我们和版权申明