M74HCT4851ADTR2G [ONSEMI]
Analog Multiplexers/ Demultiplexers with Injection Current Effect Control with LSTTL Compatible Inputs; 模拟多路复用器/多路解复用器与注入电流效应控制与LSTTL兼容输入
| 型号： | M74HCT4851ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexers/ Demultiplexers with Injection Current Effect Control with LSTTL Compatible Inputs |
| 文件： | 总14页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT4851A,
MC74HCT4852A
Analog Multiplexers/
Demultiplexers with
Injection Current Effect
Control with LSTTL
Compatible Inputs
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MARKING
DIAGRAMS
Automotive Customized
16
SOIC−16
D SUFFIX
CASE 751B
HCT485xAG
AWLYWW
This device is pin compatible to standard HC405x and MC1405xB
analog mux/demux devices, but feature injection current effect
control. This makes them especially suited for usage in automotive
applications where voltages in excess of normal logic voltage are
common.
The injection current effect control allows signals at disabled analog
input channels to exceed the supply voltage range without affecting
the signal of the enabled analog channel. This eliminates the need for
external diode/ resistor networks typically used to keep the analog
channel signals within the supply voltage range.
16
16
1
1
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
HCT485xA
AWLYWWG
1
1
The devices utilize low power silicon gate CMOS technology. The
Channel Select and Enable inputs are compatible with standard CMOS
or LSTTL outputs.
16
TSSOP−16
DT SUFFIX
CASE 948F
HCT4
85xA
ALYWG
G
16
Features
1
• Injection Current Cross−Coupling Less than 1mV/mA
(See Figure 6)
1
• Pin Compatible to HC405x and MC1405xB Devices
X
A
WL, L
YY, Y
= 1 or 2
= Assembly Location
= Wafer Lot
• Power Supply Range (V − GND) = 4.5 to 5.5 V
CC
• In Compliance With the Requirements of JEDEC Standard
No. 7 A
= Year
WW, W = Work Week
• Chip Complexity: 154 FETs or 36 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
• These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2013 − Rev. 6
MC74HCT4851A/D
MC74HCT4851A, MC74HCT4852A
FUNCTION TABLE − MC74HCT4851A
Control Inputs
Select
B
13
14
15
12
1
X0
X1
X2
X3
X4
X5
X6
X7
A
Enable
C
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X0
X1
X2
X3
X4
X5
X6
X7
NONE
ANALOG
INPUTS/
OUTPUTS
MULTIPLEXER/
DEMULTIPLEXER
3
COMMON
OUTPUT/
INPUT
X
L
H
H
H
H
X
5
L
2
H
H
X
4
11
10
9
X
CHANNEL
SELECT
INPUTS
B
V
X2
X1
14
X0
X3
12
A
B
C
9
C
CC
6
ENABLE
16
15
13
11
10
PIN 16 = V
CC
PIN 8 = GND
Figure 1. MC74HCT4851A Logic Diagram
Single−Pole, 8−Position Plus Common Off
1
2
3
4
5
6
7
8
X4
X6
X
X7
X5 Enable NC GND
Figure 2. MC74HCT4851A 16−Lead Pinout (Top View)
FUNCTION TABLE − MC74HCT4852A
Control Inputs
Select
Enable
B
A
ON Channels
12
X0
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
X1
X2
X3
14
X1
13
X SWITCH
Y SWITCH
X
Y
15
11
X2
X3
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
NONE
1
5
Y0
Y1
Y2
Y3
A
X = Don’t Care
3
2
4
V
X2
15
X1
14
X
X0
12
X3
11
A
B
9
CC
10
9
16
13
10
CHANNEL‐SELECT
INPUTS
PIN 16 = V
CC
PIN 8 = GND
B
6
ENABLE
Figure 3. MC74HCT4852A Logic Diagram
Double−Pole, 4−Position Plus Common Off
1
2
3
4
5
6
7
8
Y0
Y2
Y
Y3
Y1 Enable NC GND
Figure 4. MC74HCT4852A 16−Lead Pinout (Top View)
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2
MC74HCT4851A, MC74HCT4852A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
Positive DC Supply Voltage
DC Input Voltage (Any Pin)
(Referenced to GND)
(Referenced to GND)
–0.5 to + 7.0
CC
V
–0.5 to V
0.5
+
CC
V
in
I
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air,
$25
500
450
mA
cuit. For proper operation, V and
P
D
SOIC Package†
TSSOP Package†
mW
in
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
T
Storage Temperature Range
–65 to + 150
°C
°C
stg
Unused inputs must always be
tied to an appropriate logic voltage
T
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
L
level (e.g., either GND or V ).
CC
260
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage
DC Input Voltage (Any Pin)
Min
4.5
Max
Unit
V
V
CC
(Referenced to GND)
(Referenced to GND)
5.5
V
in
GND
0.0
V
CC
V
V *
IO
Static or Dynamic Voltage Across Switch
1.2
V
T
Operating Temperature Range, All Package Types
–
55
+ 125
°C
ns
A
t , t
r
Input Rise/Fall Time
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
f
(Channel Select or Enable Inputs)
*For voltage drops across switch greater than 1.2 V (switch on), excessive V current may be
CC
drawn; i.e., the current out of the switch may contain both V and switch input components. The
CC
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V = GND, Except Where Noted
EE
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
V
V
CC
Symbol
Parameter
Condition
Unit
V
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
R
R
= Per Spec
4.5
to
5.5
2.0
2.0
2.0
V
IH
on
V
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
= Per Spec
4.5
to
0.8
0.8
0.8
V
IL
on
5.5
I
Maximum Input Leakage Current on Digital Pins
(Enable/A/B/C)
V
= V or GND
5.5
5.5
0.1
1.0
1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply Current
(per Package)
V
V
= V or GND
2.0
20
40
CC
in(digital)
in(analog)
CC
= GND
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3
MC74HCT4851A, MC74HCT4852A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
Symbol
Parameter
Condition
= V or V ;V = V to
V
Unit
CC
R
on
Maximum “ON” Resistance
V
in
4.5
5.5
550
400
650
500
750
600
W
IL
IH IS
CC
GND; I ≤ 2.0 mA
S
DR
Delta “ON” Resistance
V
= V or V ; V = V /2
≤ 2.0 mA
4.5
5.5
80
60
100
80
120
100
W
on
in
IL
IH IS
CC
I
S
I
Maximum Off−Channel Leakage Current,
Any One Channel
V
= V or GND
mA
off
in
CC
5.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Common Channel
I
on
Maximum On−Channel Leakage
Channel−to−Channel
V
in
= V or GND
mA
CC
0.1
0.1
0.1
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns, V = 5.0 V 10%)
L
r
f
CC
Symbol
Parameter
V
CC
−55 to 25°C ≤85°C ≤125°C Unit
t
,
Maximum Propagation Delay, Analog Input to Analog Output
5.0
40
45
50
ns
PHL
t
PLH
t
,
Maximum Propagation Delay, Enable or Channel−Select to Analog Output
5.0
80
90
100
ns
PHL
t
PHZ,PZH
t
,
PLH
t
PLZ,PZL
C
Maximum Input Capacitance
(All Switches Off)
(All Switches Off)
Digital Pins
Any Single Analog Pin
Common Analog Pin
10
35
40
10
35
40
10
35
40
pF
pF
in
C
PD
Power Dissipation Capacitance
Typical
5.0
20
INJECTION CURRENT COUPLING SPECIFICATIONS (V = 5V, T = −55°C to +125°C)
CC
A
Symbol
Parameter
Maximum Shift of Output Voltage of Enabled Analog Channel
Condition
Typ
Max
Unit
VD
I * ≤ 1 mA, R ≤ 3,9 kW
0.1
1.0
0.5
5.0
1.0
5.0
2.0
20
mV
out
in
S
I * ≤ 10 mA, R ≤ 3,9 kW
in
S
I * ≤ 1 mA, R ≤ 20 kW
in
S
I * ≤ 10 mA, R ≤ 20 kW
in
S
* I = Total current injected into all disabled channels.
in
Figure 5. Typical On Resistance VCC = 4.5V
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4
MC74HCT4851A, MC74HCT4852A
External DC P.S.
V
CC
= 5 V
Vin2 / Iin2 meas. here.
Current Source
HP4155C
Smu #2
4
16
X7
RS
Vin1 = 4.9 V (Smu3)
Iin1 meas. Here
Vout
X0
X
13
3
Vm2 connected here.
Vm1 connected here.
6
8
NOTES: Rs = 3.9 KW or 20 KW.
NOTES: Vm1 & Vm2 are internal
NOTES:
HP4155C Voltmeters.
GND or V
SS
Figure 6. Injection Current Coupling Specification
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5
MC74HCT4851A, MC74HCT4852A
5V
6V
5V
V
CC
V
CC
HCT4051A
Microcontroller
Sensor
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D - Input
Figure 7. Actual Technology
Requires 32 passive components and one extra 6V regulator
to suppress injection current into a standard HCT4051 multiplexer
5V
V
CC
V
CC
HCT4851A
Microcontroller
Sensor
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D - Input
Figure 8. MC74HCT4851A Solution
Solution by applying the HCT4851A multiplexer
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6
MC74HCT4851A, MC74HCT4852A
PLOTTER
V
CC
PROGRAMMABLE
POWER
SUPPLY
V
MINI COMPUTER
DC ANALYZER
CC
16
V
V
EE
OFF
OFF
-
+
A
V
V
CC
CC
COMMON O/I
NC
DEVICE
UNDER TEST
6
8
IH
ANALOG IN
COMMON OUT
GND
Figure 10. Maximum Off Channel Leakage Current,
Figure 9. On Resistance Test Set−Up
Any One Channel, Test Set−Up
V
CC
V
CC
V
CC
V
CC
16
16
V
V
A
EE
ANALOG I/O
OFF
ON
N/C
V
EE
CC
COMMON O/I
OFF
OFF
COMMON O/I
V
CC
ANALOG I/O
V
IH
V
IL
6
6
8
8
Figure 11. Maximum Off Channel Leakage Current,
Figure 12. Maximum On Channel Leakage Current,
Common Channel, Test Set−Up
Channel to Channel, Test Set−Up
V
CC
V
CC
16
V
CC
CHANNEL
SELECT
(V )
ON/OFF
OFF/ON
COMMON O/I
C *
TEST
POINT
V
M
ANALOG I/O
I
GND
L
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
V = GND to 3.0 V
I
V
M
= 1.3 V
Figure 13. Propagation Delays, Channel Select
to Analog Out
Figure 14. Propagation Delay, Test Set−Up Channel
Select to Analog Out
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7
MC74HCT4851A, MC74HCT4852A
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ANALOG
IN
(V )
ON
50%
L
I
GND
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
V = GND to 3.0 V
I
V
M
= 1.3 V
*Includes all probe and jig capacitance
Figure 15. Propagation Delays, Analog In
to Analog Out
Figure 16. Propagation Delay, Test Set−Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
AND t
PZH
POSITION 2 WHEN TESTING t AND t
f
r
PHZ
1
2
PLZ
PZL
V
CC
90%
V
ENABLE
(V )
M
10%
V
CC
I
GND
10kW
V
CC
16
t
t
PLZ
PZL
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
PHZ
PZH
6
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
V = GND to 3.0 V
I
V
M
= 1.3 V
Figure 17. Propagation Delays, Enable to
Analog Out
Figure 18. Propagation Delay, Test Set−Up
Enable to Analog Out
V
CC
A
V
CC
16
ON/OFF
OFF/ON
COMMON O/I
NC
ANALOG I/O
V
CC
6
8
11
CHANNEL SELECT
Figure 19. Power Dissipation Capacitance,
Test Set−Up
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8
MC74HCT4851A, MC74HCT4852A
Gate = V
CC
(Disabled)
Disabled Analog Mux Input
V > V + 0.7V
Common Analog Output
> V
V
out
CC
in
CC
P+
P+
+
+
+
N - Substrate (on V potential)
CC
Figure 20. Diagram of Bipolar Coupling Mechanism
Appears if Vin exceeds VCC, driving injection current into the substrate
INJECTION
CURRENT
CONTROL
13
14
15
12
1
11
10
X0
X1
X2
X3
X4
X5
X6
X7
X
A
B
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
9
INJECTION
CURRENT
CONTROL
C
INJECTION
CURRENT
CONTROL
5
INJECTION
CURRENT
CONTROL
2
6
ENABLE
INJECTION
CURRENT
CONTROL
4
INJECTION
CURRENT
CONTROL
3
Figure 21. Function Diagram, HCT4851A
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9
MC74HCT4851A, MC74HCT4852A
INJECTION
CURRENT
CONTROL
13
14
15
12
13
1
10
X0
X1
X2
X3
X
A
B
INJECTION
CURRENT
CONTROL
9
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
6
INJECTION
CURRENT
CONTROL
ENABLE
Y0
Y1
Y2
Y3
Y
INJECTION
CURRENT
CONTROL
5
INJECTION
CURRENT
CONTROL
2
INJECTION
CURRENT
CONTROL
4
INJECTION
CURRENT
CONTROL
3
Figure 22. Function Diagram, HCT4852A
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10
MC74HCT4851A, MC74HCT4852A
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT4851ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4851ADR2G
NLV74HCT4851ADR2G*
MC74HCT4851ADTG
M74HCT4851ADTR2G
NLVHCT4851ADTR2G*
M74HCT4851ADWR2G
MC74HCT4852ADG
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
48 Units / Rail
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
1000 Units / Tape & Reel
48 Units / Rail
TSSOP−16
(Pb−Free)
SOIC−16 WIDE
(Pb−Free)
SOIC−16
(Pb−Free)
MC74HCT4852ADR2G
MC74HCT4852ADTG
M74HCT4852ADTR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
48 Units / Rail
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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11
MC74HCT4851A, MC74HCT4852A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
01.56X8
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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12
MC74HCT4851A, MC74HCT4852A
PACKAGE DIMENSIONS
SOIC−16 WIDE
DW SUFFIX
CASE 751G−03
ISSUE C
NOTES:
A
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
q
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
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13
MC74HCT4851A, MC74HCT4852A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X K REF
NOTES:
M
S
S
0.10 (0.004)
T U
V
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
0.15 (0.006) T U
K
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
ꢀꢁ4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
ꢀꢁ5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
ꢀꢁ6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K1
16
9
2X L/2
J1
SECTION N−N
B
L
−U−
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
ꢀꢁ7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
S
0.15 (0.006) T U
A
N
A
B
C
D
F
G
H
J
J1
K
K1
L
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
−V−
F
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
0.026 BSC
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
DETAIL E
0.65 BSC
0.18
0.09
0.09
0.19
0.19
−W−
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
M
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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