M74VHC1G135DFT2G-L22038 [ONSEMI]
Single 2-Input NAND Gate, Schmitt Trigger ,Open Drain;
| 型号： | M74VHC1G135DFT2G-L22038 |
| 厂家： | 
ONSEMI |
| 描述： | Single 2-Input NAND Gate, Schmitt Trigger ,Open Drain 栅 |
| 文件： | 总6页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1G135
2−Input NAND
Schmitt−Trigger with
Open Drain Output
The MC74VHC1G135 is a single gate CMOS Schmitt NAND
trigger with an open drain output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
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MARKING
DIAGRAMS
The internal circuit is composed of three stages, including an open
drain output which provides the capability to set the output switching
level. This allows the MC74VHC1G135 to be used to interface 5 V
5
5
1
VZ M G
circuits to circuits of any voltage between V and 7 V using an
SC−88A/SOT−353/SC−70
DF SUFFIX
CC
G
external resistor and power supply.
1
5
CASE 419A
The MC74VHC1G135 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
The MC74VHC1G135 can be used to enhance noise immunity or to
square up slowly changing waveforms.
5
VZ M G
1
G
Features
TSOP−5/SOT−23/SC−59
DT SUFFIX
1
• High Speed: t = 4.9 ns (Typ) at V = 5 V
PD
CC
CASE 483
• Low Internal Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
VZ = Device Code
• Power Down Protection Provided on Inputs
M
G
= Date Code*
= Pb−Free Package
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 70; Equivalent Gates = 18
• Pb−Free Packages are Available
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
2
3
4
5
IN B
V
IN B
IN A
GND
1
2
3
5
CC
IN A
GND
OVT
OUT Y
V
CC
OUT Y
4
FUNCTION TABLE
Inputs
Output
Y
A
B
Figure 1. Pinout (Top View)
L
L
L
H
L
Z
Z
Z
L
H
H
H
IN A
IN B
&
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 15
MC74VHC1G135/D
MC74VHC1G135
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
DC Supply Voltage
DC Input Voltage
−0.5 to +7.0
CC
V
−0.5 to +7.0
V
IN
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
−0.5 to 7.0
V
OUT
I
−20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
V
< GND; V
> V
CC
+20
OK
OUT
OUT
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power dissipation in still air
Thermal resistance
SC−88A, TSOP−5
SC−88A, TSOP−5
200
D
q
333
260
JA
T
Lead temperature, 1 mm from case for 10 secs
Junction temperature under bias
Storage temperature
L
J
T
+150
°C
T
−65 to +150
Level 1
°C
stg
MSL
Moisture Sensitivity
F
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
R
V
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
ESD
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
500
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
Max
5.5
Unit
V
V
DC Supply Voltage
CC
V
DC Input Voltage
5.5
V
IN
V
DC Output Voltage
7.0
V
OUT
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
°C
ns/V
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
f
CC
CC
Device Junction Temperature versus
Time to 0.1% Bond Failures
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G135
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
Positive Threshold
Voltage
3.0
4.5
5.5
1.50 1.88 2.25 1.50 2.25
2.35 2.66 3.10 2.35 3.10
2.80 3.21 3.70 2.80 3.70
1.50
2.35
2.80
2.25
3.10
3.70
V
T+
V
Negative Threshold
Voltage
3.0
4.5
5.5
0.65 1.03 1.40 0.65 1.40
1.10 1.62 2.10 1.10 2.10
1.45 2.02 2.60 1.45 2.60
0.65
1.10
1.45
1.40
2.10
2.60
V
V
V
T−
V
Hysteresis Voltage
3.0
4.5
5.5
0.30 0.85 1.60 0.30 1.60
0.40 1.05 2.00 0.40 2.00
0.50 1.20 2.25 0.50 2.25
0.30
0.40
0.50
1.60
2.00
2.25
H
V
= V or V
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Maximum Low−Level
Output Voltage
IN
IH
IL
OL
I
OL
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
OL
OL
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
40
5
mA
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
1.0
20
CC
IN
CC
I
Power Off−Output
Leakage Current
V
V
= 5.5 V
= 5.5 V
0
0.25
2.5
OFF
OUT
IN
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t /t = 3.0 ns
r f
load
T
A
= 25°C
Typ
T
≤ 85°C
−55 ≤ T ≤ 125°C
A
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
= 3.3 0.3 V C = 15 pF
7.6
10.1 15.4
11.9
1.0
1.0
14.0
17.5
1.0
1.0
16.1
19.6
ns
t
Maximum Output
Enable Time, A or B to Y
CC
L
PZL
R = R = 500 W
C = 50 pF
L
I
L
V
= 5.0 0.5 V C = 15 pF
4.9
6.4
7.7
9.7
1.0
1.0
9.0
11.0
1.0
1.0
10.3
12.3
CC
L
R = R = 500 W
C = 50 pF
L
I
L
V
= 3.3 0.3 V C = 50 pF
I
10.1 15.4
17.5
11.0
10
19.6
12.3
10
ns
t
Maximum Output
Disable Time
CC
L
PLZ
R = R = 500 W
L
V
= 5.0 0.5 V C = 50 pF
6.4
5.0
9.7
10
CC
L
R = R = 500 W
L
I
C
Maximum Input
Capacitance
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
16
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G135
V
V
− 7 V
CC
CC
V
A or B
CC
A
B
50%
R
L
OVT
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
+0.3 V
50% V
Y
CC
V
OL
Figure 4. Output Voltage Mismatch Application
Figure 5. Switching Waveforms
V
CC
V
x 2
CC
R
1
PULSE
GENERATOR
DUT
R
T
C
L
R
L
C = 50 pF equivalent (Includes jig and probe capacitance)
L
R = R = 500 W or equivalent
L
1
R = Z
T
of pulse generator (typically 50 W)
OUT
Figure 6. Test Circuit
V
CC
MC74VHC1G135
MC74VHC1G03
A
B
2.2 kW
C
D
E = (A • B) + (C+D)
Figure 7. Complex Boolean Functions
V
V
CC
CC
MC74VHC1G135
1
2
5
4
B
A
1.5 V
220 W
3.3 V
R
LED
A
B
3
GTL
Figure 8. LED Driver
Figure 9. GTL Driver
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC1G135DFT1
M74VHC1G135DFT1G
SC70−5 / SC−88A / SOT−353
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G135DFT2
M74VHC1G135DFT2G
SC70−5 / SC−88A / SOT−353
3000 Units / Tape & Reel
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G135DTT1
M74VHC1G135DTT1G
SOT23−5 / TSSOP−5 / SC59−5
SOT23−5 / TSSOP−5 / SC59−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G135
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
D 5 PL
0.2 (0.008)
B
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1G135
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
C
D
G
H
J
K
L
M
S
0.90
0.25
0.95 BSC
1.10
0.50
C
SEATING
PLANE
0.05
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
T
10
3.00
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC1G135/D
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