MAC12SM_05 [ONSEMI]

Sensitive Gate Triacs Silicon Bidirectional Thyristors; 敏感的门双向可控硅硅双向晶闸管
MAC12SM_05
型号: MAC12SM_05
厂家: ONSEMI    ONSEMI
描述:

Sensitive Gate Triacs Silicon Bidirectional Thyristors
敏感的门双向可控硅硅双向晶闸管

可控硅 栅
文件: 总5页 (文件大小:60K)
中文:  中文翻译
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MAC12SM, MAC12SN  
Preferred Device  
Sensitive Gate Triacs  
Silicon Bidirectional Thyristors  
Designed for industrial and consumer applications for full wave  
control of AC loads such as appliance controls, heater controls, motor  
controls, and other power switching applications.  
http://onsemi.com  
Features  
TRIACS  
12 AMPERES RMS  
600 thru 800 VOLTS  
Sensitive Gate Allows Triggering by Microcontrollers and other  
Logic Circuits  
Blocking Voltage to 800 Volts  
On-State Current Rating of 12 Amperes RMS at 70°C  
High Surge Current Capability − 90 Amperes  
Rugged, Economical TO−220AB Package  
Glass Passivated Junctions for Reliability and Uniformity  
Maximum Values of I , V and I Specified for Ease of Design  
High Commutating di/dt − 8.0 A/ms Minimum at 110°C  
Immunity to dV/dt − 15 V/msec Minimum at 110°C  
Operational in Three Quadrants: Q1, Q2, and Q3  
Pb−Free Packages are Available*  
MT2  
MT1  
G
MARKING  
DIAGRAM  
GT GT  
H
MAC12SxG  
AYWW  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
TO−220AB  
CASE 221A−09  
STYLE 4  
Rating  
Symbol  
Value  
Unit  
1
2
Peak Repetitive Off−State Voltage (Note 1)  
(T = −40 to 110°C, Sine Wave,  
50 to 60 Hz, Gate Open)  
V
V
DRM,  
3
V
J
RRM  
MAC12SM  
MAC12SN  
600  
800  
x
= M, or N  
A
Y
= Assembly Location  
= Year  
On-State RMS Current  
(All Conduction Angles; T = 70°C)  
I
12  
A
A
T(RMS)  
C
WW = Work Week  
G
= Pb−Free Package  
Peak Non-Repetitive Surge Current  
(One Full Cycle Sine Wave, 60 Hz,  
I
TSM  
90  
T = 110°C)  
J
PIN ASSIGNMENT  
2
2
Circuit Fusing Consideration (t = 8.33 ms)  
I t  
33  
16  
A sec  
1
Main Terminal 1  
Peak Gate Power  
(Pulse Width = 1.0 msec, T = 70°C)  
P
W
W
GM  
2
3
4
Main Terminal 2  
Gate  
C
Average Gate Power  
(t = 8.3 msec, T = 70°C)  
P
0.35  
G(AV)  
C
Main Terminal 2  
Operating Junction Temperature Range  
Storage Temperature Range  
T
−40 to 110  
−40 to 150  
°C  
°C  
J
T
stg  
ORDERING INFORMATION  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
Device  
Package  
Shipping  
MAC12SM  
TO−220AB  
50 Units / Rail  
50 Units / Rail  
MAC12SMG  
TO−220AB  
(Pb−Free)  
1. (V  
and V  
for all types can be applied on a continuous basis. Blocking  
DRM  
RRM  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the devices are exceeded.  
MAC12SN  
TO−220AB  
50 Units / Rail  
50 Units / Rail  
MAC12SNG  
TO−220AB  
(Pb−Free)  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Preferred devices are recommended choices for future use  
and best overall value.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
December, 2005 − Rev. 3  
MAC12SM/D  
 
MAC12SM, MAC12SN  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Value  
Unit  
Thermal Resistance,  
Junction−to−Case  
Junction−to−Ambient  
R
R
2.2  
62.5  
°C/W  
q
JC  
JA  
q
Maximum Lead Temperature for Soldering Purposes 1/8from Case for 10 Seconds  
T
260  
°C  
L
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted; Electricals apply in both directions)  
J
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Peak Repetitive Blocking Current  
I
I
,
mA  
DRM  
0.01  
2.0  
(V = Rated V , V  
DRM  
; Gate Open)  
RRM  
T = 25°C  
T = 110°C  
J
RRM  
D
J
ON CHARACTERISTICS  
Peak On-State Voltage (Note 2)  
V
1.85  
V
TM  
(I 17 A)  
=
TM  
Gate Trigger Current (Continuous dc) (V = 12 V, R = 100 W)  
I
mA  
D
L
GT  
1.5  
2.5  
2.7  
5.0  
5.0  
5.0  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
Holding Current  
(V = 12 V, Gate Open, Initiating Current = 200 mA)  
D
I
2.5  
10  
mA  
mA  
H
Latching Current (V = 12 V, I = 5 mA)  
I
D
G
L
3.0  
5.0  
3.0  
15  
20  
15  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
Gate Trigger Voltage (Continuous dc) (V = 12 V, R = 100 W)  
V
V
D
L
GT  
0.45  
0.45  
0.45  
0.68  
0.62  
0.67  
1.5  
1.5  
1.5  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
DYNAMIC CHARACTERISTICS  
Critical Rate of Change of Commutating Current  
(V = 400 V, I = 3.5 A, Commutating dV/dt = 10 V/ms, Gate Open, T = 110°C,  
(di/dt)  
8.0  
10  
A/ms  
c
D
TM  
J
f = 500 Hz, Snubber: Cs = 0.01 mf, Rs = 15 W)  
Critical Rate of Rise of Off-State Voltage  
dV/dt  
di/dt  
15  
40  
V/ms  
A/ms  
(V = 67% V  
D
, Exponential Waveform, R = 1 KW, T = 110°C)  
DRM GK J  
Repetitive Critical Rate of Rise of On-State Current  
10  
IPK = 50 A; PW = 40 msec; diG/dt = 1 A/msec; Igt = 100 mA; f = 60 Hz  
2. Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.  
Voltage Current Characteristic of Triacs  
(Bidirectional Device)  
+ Current  
Quadrant 1  
MainTerminal 2 +  
Symbol  
Parameter  
V
TM  
V
Peak Repetitive Forward Off State Voltage  
Peak Forward Blocking Current  
DRM  
DRM  
on state  
I
I
H
I
at V  
RRM  
V
Peak Repetitive Reverse Off State Voltage  
Peak Reverse Blocking Current  
RRM  
RRM  
I
RRM  
V
Maximum On State Voltage  
Holding Current  
+ Voltage  
off state  
TM  
I
I
at V  
H
DRM  
DRM  
I
H
Quadrant 3  
MainTerminal 2 −  
V
TM  
http://onsemi.com  
2
MAC12SM, MAC12SN  
Quadrant Definitions for a Triac  
MT2 POSITIVE  
(Positive Half Cycle)  
+
(+) MT2  
(+) MT2  
Quadrant II  
Quadrant I  
(−) I  
(+) I  
GT  
GT  
GATE  
GATE  
MT1  
MT1  
REF  
REF  
I
+ I  
GT  
GT  
(−) MT2  
(−) MT2  
Quadrant III  
Quadrant IV  
(+) I  
(−) I  
GT  
GT  
GATE  
GATE  
MT1  
REF  
MT1  
REF  
MT2 NEGATIVE  
(Negative Half Cycle)  
All polarities are referenced to MT1.  
With in−phase signals (using standard AC lines) quadrants I and III are used.  
0.90  
Q1  
0.85  
100  
10  
0.80  
Q3  
Q2  
0.75  
0.70  
Q2  
Q3  
Q1  
0.65  
0.60  
0.55  
0.50  
1
0.45  
0.40  
0.1  
40 25 10  
5
20 35 50 65 80 95 110  
40 25 10  
5
20 35  
50 65 80  
95 110  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 2. Typical Gate Trigger Voltage  
versus Junction Temperature  
Figure 1. Typical Gate Trigger Current  
versus Junction Temperature  
http://onsemi.com  
3
MAC12SM, MAC12SN  
100  
100  
10  
Q1  
10  
Q2  
Q3  
MT2 Positive  
MT2 Negative  
1
1
0.1  
0.1  
40 25 10  
5
20 35 50 65 80 95 110  
40 25 10  
5
20 35 50 65 80 95 110  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 4. Typical Holding Current  
versus Junction Temperature  
Figure 3. Typical Latching Current  
versus Junction Temperature  
25  
20  
15  
10  
110  
100  
90  
DC  
180°  
120°  
30°, 60°  
90°  
60°  
90°  
80  
30°  
180°  
70  
60  
5
0
DC  
0
2
4
6
8
10  
12  
0
2
4
6
8
10  
12  
I
, RMS ON-STATE CURRENT (AMPS)  
T(RMS)  
I , AVERAGE ON-STATE CURRENT (AMPS)  
T(AV)  
Figure 5. Typical RMS Current Derating  
Figure 6. On-State Power Dissipation  
100  
1
Typical @ T = 25°C  
J
Maximum @ T = 110°C  
J
Maximum @ T = 25°C  
J
10  
0.1  
1
0.01  
0.1  
1
10  
100  
1000  
10000  
t, TIME (ms)  
Figure 8. Typical Thermal Response  
0.1  
0.5  
1.5  
2.5  
3.5  
4.5  
V , INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)  
T
Figure 7. Typical On-State Characteristics  
http://onsemi.com  
4
MAC12SM, MAC12SN  
PACKAGE DIMENSIONS  
TO−220AB  
CASE 221A−09  
ISSUE AA  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
SEATING  
PLANE  
−T−  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION Z DEFINES A ZONE WHERE ALL  
BODY AND LEAD IRREGULARITIES ARE  
ALLOWED.  
C
S
B
F
T
4
INCHES  
DIM MIN MAX  
MILLIMETERS  
MIN  
14.48  
9.66  
4.07  
0.64  
3.61  
2.42  
2.80  
0.46  
12.70  
1.15  
4.83  
2.54  
2.04  
1.15  
5.97  
0.00  
1.15  
−−−  
MAX  
15.75  
10.28  
4.82  
0.88  
3.73  
2.66  
3.93  
0.64  
14.27  
1.52  
5.33  
3.04  
2.79  
1.39  
6.47  
1.27  
−−−  
A
K
Q
Z
A
B
C
D
F
0.570  
0.380  
0.160  
0.025  
0.142  
0.095  
0.110  
0.018  
0.500  
0.045  
0.190  
0.100  
0.080  
0.045  
0.235  
0.000  
0.045  
0.620  
0.405  
0.190  
0.035  
0.147  
0.105  
0.155  
0.025  
0.562  
0.060  
0.210  
0.120  
0.110  
0.055  
0.255  
0.050  
−−−  
1
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
−−− 0.080  
2.04  
STYLE 4:  
PIN 1. MAIN TERMINAL 1  
2. MAIN TERMINAL 2  
3. GATE  
4. MAIN TERMINAL 2  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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USA/Canada  
ON Semiconductor Website: http://onsemi.com  
Order Literature: http://www.onsemi.com/litorder  
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada  
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Phone: 81−3−5773−3850  
For additional information, please contact your  
local Sales Representative.  
MAC12SM/D  

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