MC00LVELT22MNR4G_技术文档

MC100LVELT22

3.3VꢀDual LVTTL/LVCMOS

to Differential LVPECL

Translator

Description

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MARKING

The MC100LVELT22 is a dual LVTTL/LVCMOS to differential

LVPECL translator. Because LVPECL (Low Voltage Positive ECL)

levels are used, only +3.3 V and ground are required. The small outline

8-lead package and the low skew, dual gate design of the LVELT22

makes it ideal for applications which require the translation of a clock

and a data signal.

DIAGRAMS*

8

1

KVT22

ALYW

G

Features

SOIC−8

D SUFFIX

CASE 751

• 350 ps Typical Propagation Delay

• <100 ps Output−to−Output Skew

• Flow Through Pinouts

1

8

• The 100 Series Contains Temperature Compensation

1

KR22

• LVPECL Operating Range: V = 3.0 V to 3.8 V

CC

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

with GND = 0 V

G

• When Unused TTL Input is left Open, Q Output will Default High

• Pb−Free Packages are Available

1

DFN8

MN SUFFIX

CASE 506AA

1

4

A

L

Y

= Assembly Location

= Wafer Lot

= Year

W = Work Week

M = Date Code

G

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

©

Semiconductor Components Industries, LLC, 2007

1

Publication Order Number:

March, 2007 − Rev. 5

MC100LVELT22/D

MC100LVELT22

Table 1. PIN DESCRIPTION

Q0

1

2

8

7

V

CC

FUNCTION

Qn, Qn

D0, D1

V_CC

LVPECL Differential Outputs

LVTTL/LVCMOS Inputs

Positive Supply

D0

D1

LVTTL/

LVCMOS

LVPECL

GND

Ground

Q1

3

4

6

5

EP

Exposed pad must be connected

to a sufficient thermal conduit.

Electrically connect to the most

negative supply or leave floating

open.

GND

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

EP

Table 2. ATTRIBUTES

Characteristics

Value

N/A

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

N/A

ESD Protection

Human Body Model

Machine Model

> 4 kV

> 200 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

UL 94 V−0 @ 0.125 in

164

Flammability Rating

Transistor Count

Oxygen Index: 28 to 34

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Positive Power Supply

Condition 1

GND = 0 V

Condition 2

Rating

Unit

V

7

V

CC

I

Input Voltage

GND = 0 V

V ꢀ V

I

CC

I

Output Current

Continuous

Surge

50

mA

out

100

T

Operating Temperature Range

Storage Temperature Range

−40 to +85

°C

A

T

−65 to +150

stg

JA

q

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SO−8

190

130

°C/W

q

Thermal Resistance (Junction−to−Case)

std bd

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

std bd

Thermal Resistance (Junction−to−Ambient) 0 lfpm

SO−8

41 to 44 5%

°C/W

JC

JA

TSSOP−8

185

140

°C/W

q

Thermal Resistance (Junction−to−Case)

TSSOP−8

41 to 44 5%

°C/W

JC

JA

DFN8

129

84

°C/W

500 lfpm

T

sol

Wave Solder

Pb <2 to 3 sec @ 248°C

Pb−Free <2 to 3 sec @ 260°C

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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2

MC100LVELT22

Table 4. LVPECL DC CHARACTERISTICS V = 3.3 V; GND = 0.0 V (Note 2)

CC

−40°C

25°C

85°C

Symbol

Characteristic

Power Supply Current

Min

Typ

Max

28

Min

Typ

Max

28

Min

Typ

Max

29

Unit

mA

mV

I

CC

V

Output HIGH Voltage (Note 3)

Output LOW Voltage (Note 3)

2275

1490

2420

1680

2275

1490

2420

1680

2275

1490

2420

1680

OH

OL

V

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Output parameters vary 1:1 with V . V can vary 0.15 V.

CC

3. Outputs are terminated through a 50 ohm resistor to V −2 volts.

CC

Table 5. LVTTL/LVCMOS INPUT DC CHARACTERISTICS V = 3.3 V; T = −40°C to 85°C (Note 4)

CC

A

Symbol

Characteristic

Input HIGH Current

Min

Typ

Max

20

Unit

mA

V

Condition

= 2.7 V

I

V

IH

IN

I

Input HIGH Current

Input LOW Current

100

−0.2

−1.2

= V

CC

IHH

IL

= 0.5 V

= −18 mA

V

I

IN

IK

IH

IL

Input HIGH Voltage

Input LOW Voltage

2.0

V

0.8

V

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

4. V can vary 0.15 V.

CC

Table 6. AC CHARACTERISTICS V = 3.3 V; GND = 0.0 V (Note 5)

CC

−40°C

25°C

Typ

350

30

85°C

Symbol

Characteristic

Maximum Toggle Frequency

Propagation Delay (Note 6)

Min

Typ

Max

Min

Max

Min

Typ

Max

Unit

MHz

ps

f

max

PLH

skew

t

200

350

30

600

200

600

200

350

30

600

t

Skew

Output−to−Output

Part−to−Part

100

400

100

400

100

400

ps

tJITTER

Random Clock Jitter (RMS)

1.6

ps

t /t

r f

Output Rise/Fall Time (20−80%)

200

550

200

500

200

500

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5.

V

can vary 0.15 V.

CC

6. Specifications for standard TTL input signal.

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3

MC100LVELT22

Z = 50 W

Q

D

o

Receiver

Device

Driver

Device

Z = 50 W

o

50 W

V

TT

V

= V − 3.0 V

TT

CC

Figure 1. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

ORDERING INFORMATION

†

Device

MC100LVELT22D

MC100LVELT22DG

Package

Shipping

SOIC−8

98 Units / Rail

SOIC−8

(Pb−Free)

MC100LVELT22DR2

MC100LVELT22DR2G

SOIC−8

2500 / Tape & Reel

SOIC−8

(Pb−Free)

MC100LVELT22DT

MC100LVELT22DTG

TSSOP−8

100 Units / Rail

TSSOP−8

(Pb−Free)

MC100LVELT22DTR2

MC100LVELT22DTR2G

TSSOP−8

2500 / Tape & Reel

TSSOP−8

(Pb−Free)

MC100LVELT22MNR4

MC00LVELT22MNR4G

DFN8

1000 / Tape & Reel

DFN8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D

AN1406/D

AN1503/D

AN1504/D

AN1568/D

AN1672/D

AND8001/D

AND8002/D

AND8020/D

AND8066/D

AND8090/D

−

ECL Clock Distribution Techniques

Designing with PECL (ECL at +5.0 V)

ECLinPSt I/O SPiCE Modeling Kit

Metastability and the ECLinPS Family

Interfacing Between LVDS and ECL

The ECL Translator Guide

Odd Number Counters Design

Marking and Date Codes

Termination of ECL Logic Devices

Interfacing with ECLinPS

AC Characteristics of ECL Devices

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4

MC100LVELT22

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

−Z−

1.27 BSC

0.050 BSC

0.10 (0.004)

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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5

MC100LVELT22

PACKAGE DIMENSIONS

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

8x K REF

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

M

S

V

0.10 (0.004)

T U

S

0.15 (0.006) T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

2X L/2

8

5

4

0.25 (0.010)

B

−U−

L

1

M

PIN 1

IDENT

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE −W−.

S

0.15 (0.006) T U

A

−V−

F

DETAIL E

MILLIMETERS

INCHES

MIN

DIM MIN

MAX

3.10

MAX

0.122

0.043

0.006

0.028

A

B

C

D

F

2.90

0.80

0.05

0.40

0.114

C

1.10 0.031

0.15 0.002

0.70 0.016

0.10 (0.004)

−W−

SEATING

D

−T−

G

K

L

0.65 BSC

0.026 BSC

PLANE

0.25

0.40 0.010

0.016

4.90 BSC

0.193 BSC

0

DETAIL E

M

0

6

_

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MC100LVELT22

PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

D

A

B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

MILLIMETERS

DIM MIN

MAX

1.00

0.05

E

A

A1

A3

b

0.80

0.00

0.20 REF

0.20

0.30

2 X

D

2.00 BSC

0.10

C

D2

E

E2

e

K

L

1.10

2.00 BSC

0.70

0.50 BSC

0.20

0.25

1.30

2 X

0.90

0.10

C

TOP VIEW

−−−

0.35

A

0.10

0.08

C

8 X

(A3)

SIDE VIEW

D2

A1

SEATING

PLANE

C

e

e/2

4

1

^{8 X}L

E2

K

8

5

0.10 C A B

8 X b

0.05

C

NOTE 3

BOTTOM VIEW

ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

MC100LVELT22/D

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型号：	MC00LVELT22MNR4G
厂家：	ONSEMI
描述：	3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator 3.3V双路LVTTL / LVCMOS到差分LVPECL翻译
文件：	总7页 (文件大小：80K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC00LVELT22MNR4G [ONSEMI]

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