MC100E445 [ONSEMI]
5V ECL 4-Bit Serial/Parallel Converter; 5V ECL 4位串行/并行转换器
| 型号： | MC100E445 |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL 4-Bit Serial/Parallel Converter |
| 文件： | 总13页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E445, MC100E445
5VꢀECL 4-Bit Serial/Parallel
Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first serial bit to Q0, the
second to Q1 etc.
Two selectable serial inputs provide a loopback capability for testing
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
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PLCC−28
FN SUFFIX
CASE 776
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn−1. For each additional
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to
“swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn−1
output (see Timing Diagram B).
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the data on the output will
change on every eighth clock cycle thus allowing for an 8-bit conversion
scheme using two E445’s. When cascaded in an 8-bit conversion scheme
the devices will not operate at the 2.0 Gb/s data rate of a single device.
Refer to the applications section of this data sheet for more information on
cascading the E445.
MARKING DIAGRAM*
1 28
MCxxxE445FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Upon power-up the internal flip-flops will attain a random state. To
synchronize multiple E445’s in a system the master reset must be asserted.
The V pin, an internally generated voltage supply, is available to this
BB
*For additional marking information, refer to
Application Note AND8002/D.
device only. For single-ended input conditions, the unused differential
input is connected to V as a switching reference voltage. V may also
BB
BB
rebias AC coupled inputs. When used, decouple V and V via a
BB
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, V should be left open.
BB
The 100 Series contains temperature compensation.
Features
• On-Chip Clock ÷4 and ÷8
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• 2.0 Gb/s Data Rate Capability
• Differential Clock and Serial Inputs
• Meets or Exceeds JEDEC Spec EIA/JESD78
IC Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 528 devices
• V Output for Single-Ended Input Applications
BB
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = −4.2 V to −5.7 V
EE
with V = 0 V
EE
• Internal Input 50 kW Pulldown Resistors
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 12
MC10E445/D
MC10E445, MC100E445
Table 1. PIN DESCRIPTION
SINA SINA
MODE NC V
CCO
PIN
FUNCTION
25 24 23 22 21 20 19
18
SINA, SINA
SINB, SINB
SEL
ECL Differential Serial Data Input A
ECL Differential Serial Data Input B
ECL Serial Input Selector Pin
ECL Parallel Data Outputs
ECL Differential Clock Inputs
ECL Differential ÷4 Clock Output
ECL Differential ÷8 Clock Output
ECL Conversion Mode 4-Bit/8-Bit
ECL Conversion Synchronizing Input
Reference Voltage Output
Positive Supply
SINB 26
SINB 27
SEL 28
SOUT
SOUT
17
16
15
14
13
12
Q0−Q3
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
V
CC
MC10E445
V
1
2
3
4
Q0
Q1
V
EE
SYNCH
CLK
CLK
V
V
V
BB
CC
EE
, V
CCO
CCO
Negative Supply
NC
No Connect
V
Q2
BB
5
6
7
8
9
10 11
CL/8 CL/8 V
CL/4 CL/4 V Q3
CCO
CCO
* All V and V
pins are tied together on the die.
CCO
CC
Warning: All V , V
, and V pins must be externally con-
CCO EE
CC
nected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
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2
MC10E445, MC100E445
SINB
SINB
SINA
D
Q
D
D
D
D
Q
Q
Q
Q
Q3
Q2
SINA
SEL
D
D
D
Q
Q
Q
Q1
Q0
SOUT
SOUT
1
0
MODE
CL/4
CL/4
Out
÷4
CLK
CLK
InOut
Latch
R
EN
CL/8
CL/8
Out
÷2
D
Q
D
SYNC
R
Q
RESET
V
BB
Figure 2. Logic Diagram
Table 2. FUNCTION TABLES
Mode
Conversion
SEL
Serial Input
L
H
4-Bit
8-Bit
H
L
A
B
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MC10E445, MC100E445
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
PECL Mode Power Supply
V
= 0 V
8
V
CC
I
EE
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ≤ V
6
−6
V
V
EE
CC
I
CC
V ≥ V
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
0 to +85
A
T
−65 to +150
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC10E445, MC100E445
Table 4. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 1)
EE
CCx
0°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
154
Max
185
Min
Max
185
Min
Max
185
Unit
mA
mV
mV
mV
mV
mV
V
I
154
154
EE
V
Output HIGH Voltage (Note 2)
Output HIGH Voltage sout/sout
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3980
3975
3050
3830
3050
3.62
2.2
4070
4160
4170
3370
4160
3520
3.74
4.6
4020
3975
3050
3870
3050
3.65
2.2
4105
4190
4170
3370
4190
3520
3.75
4.6
4090
3975
3050
3940
3050
3.69
2.2
4185
4280
4170
3405
4280
3555
3.81
4.6
OH
VOH
sout
V
V
V
V
V
3210
3995
3285
3210
4030
3285
3227
4110
3302
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
3. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 5. 10E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 4)
EE
CCx
0°C
Typ
154
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
185
Min
Max
185
Min
Max
185
Unit
mA
mV
mV
I
154
154
EE
V
Output HIGH Voltage (Note 5)
Output HIGH Voltage sout/sout
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1020 −930
−1025
−840
−980
−895
−810
−910
−815
−720
−830
OH
VOH
−830 −1025
−830 −1025
sout
V
V
V
V
V
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV
−1170 −1005 −840 −1130 −970 −810 −1060 −970 −720 mV
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV
OL
IH
IL
−1.38
−2.8
−1.27 −1.35
−1.25 −1.31
−1.19
−0.4
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
−0.4
−2.8
−0.4
−2.8
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.065
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
5. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
6. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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MC10E445, MC100E445
Table 6. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 7)
EE
CCx
0°C
25°C
Typ
85°C
Typ
177
Symbol
Characteristic
Power Supply Current
Min
Typ
154
Max
185
Min
Max
185
Min
Max
Unit
mA
mV
mV
mV
mV
mV
V
I
154
212
EE
V
Output HIGH Voltage (Note 8)
Output HIGH Voltage sout/sout
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3975
3975
3190
3835
3190
3.62
2.2
4050
4120
4170
3380
4120
3525
3.74
4.6
3975
3975
3190
3835
3190
3.62
2.2
4050
4120
4170
3380
4120
3525
3.74
4.6
3975 4050 4120
3975 4170
OH
VOH
sout
V
V
V
V
V
3295
3975
3355
3255
3975
3355
3190 3260 3380
3835 3975 4120
3190 3355 3525
OL
IH
IL
3.62
2.2
3.74
4.6
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration Configuration)
(Note 9)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
9. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 7. 100E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 10)
EE
CCx
0°C5
Typ
154
25°C
Typ
154
85°C
Typ
177
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
212
Unit
mA
mV
mV
I
185
185
EE
V
Output HIGH Voltage (Note 11)
Output HIGH Voltage sout/sout
Output LOW Voltage (Note 11)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1025 −950
−1025
−880 −1025 −950
−830 −1025
−880 −1025 −950
−830 −1025
−880
−830
OH
VOH
sout
V
V
V
V
V
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
OL
IH
IL
−1.38
−2.8
−1.26 −1.38
−1.26 −1.38
−1.26
−0.4
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential) Configuration
(Note 12)
−0.4
−2.8
−0.4
−2.8
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
11. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
12.V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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MC10E445, MC100E445
Table 8. AC CHARACTERISTICS V
= 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 13)
CCx EE
CCx
EE
0°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
Maximum Conversion Frequency
2.0
2.0
2.0
Gb/s
NRZ
MAX
t
t
Propagation Delay to Output
CLK to Q, Reset to Q
CLK to SOUT (Diff)
CLK to CL/4(Diff)
ps
PLH
PHL
1500
800
1100
1100
1800
975
1325
1325
2100
1150
1550
1550
1500
800
1100
1100
1800
975
1325
1325
2100
1150
1550
1550
1500
800
1100
1100
1800
975
1325
1325
2100
1150
1550
1550
CLK to CL/8(Diff)
t
t
Setup Time
SINA, SINB
SEL
ps
ps
s
−100 −250
−100 −250
−100 −250
0
−200
0
−200
0
−200
Hold Time
h
SINA, SINB, SEL
450
500
300
300
450
500
300
300
450
500
300
300
t
t
Reset Recovery Time
ps
ps
RR
Minimum Pulse Width
CLK, MR
PW
400
150
400
150
400
150
t
Random Clock Jitter (RMS)
< 1
< 1
< 1
ps
JITTER
V
Input Voltage Swing
(Differential Configuration)
1000
1000
1000
mV
PP
t
t
Rise/Fall Times 20%−80%
ps
r
f
SOUT
Other
100
200
225
425
350
650
100
200
225
425
350
650
100
200
225
425
350
650
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
14.Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
tRR
Reset
CLK / CLK
Figure 3.
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MC10E445, MC100E445
CLK
SIN
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1 Dn+2 Dn+3
RESET
Q0
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Q1
Dn+1
Q2
Dn+2
Q3
Dn+3
SOUT
CL/4
CL/8
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1 Dn+2 Dn+3
Timing Diagram A. 1:4 Serial to Parallel Conversion
CLK
SIN
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1 Dn+2 Dn+3 Dn+4
RESET
SYNC
Q0
Dn-4
Dn-3
Dn-2
Dn-1
Dn+1
Q1
Dn+2
Q2
Dn+3
Q3
Dn+4
SOUT
CL/4
CL/8
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1 Dn+2 Dn+3 Dn+4
Timing Diagram B. 1:4 Serial to Parallel Conversion With SYNC Pulse
Figure 4. Timing Diagrams
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MC10E445, MC100E445
APPLICATIONS INFORMATION
CLOCK
CLOCK
The MC10E/100E445 is an integrated 1:4 serial to parallel
converter. The chip is designed to work with the E446 device
to provide both transmission and receiving of a high speed
serial data path. The E445, can convert up to a 2.0 Gb/s NRZ
data stream into 4-bit parallel data. The device also provides
a divide by four clock output to be used to synchronize the
parallel data with the rest of the system.
E445a
E445b
SERIAL
INPUT
DATA
SIN
SIN
SOUT
SOUT
SIN
SIN
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
The E445 features multiplexed dual serial inputs to
provide test loop capability when used in conjunction with
the E446. Figure 5 illustrates the loop test architecture. The
architecture allows for the electrical testing of the link
without requiring actual transmission over the serial data
path medium. The SINA serial input of the E445 has an extra
buffer delay and thus should be used as the loop back serial
input.
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
PARALLEL OUTPUT DATA
100ps
CLOCK
CLK
SOUT
SOUT
TO SERIAL
MEDIUM
T
PARALLEL
DATA
pd
to SOUT
800 ps
1150 ps
SINA
SINA
PARALLEL
DATA
Figure 6. Cascaded 1:8 Converter Architecture
FROM
SERIAL
MEDIUM
SINB
SINB
With a minimum delay of 800 ps on this output the clock
for the lower order E445 cannot be delayed more than 800 ps
relative to the clock of the first E445 without potentially
missing a bit of information. Because the setup time on the
serial input pin is negative coincident excursions on the data
and clock inputs of the E445 will result in correct operation.
Figure 5. Loopback Test Architecture
The E445 features a differential serial output and a divide
by 8 clock output to facilitate the cascading of two devices
to build a 1:8 demultiplexer. Figure 6 illustrates the
architecture for a 1:8 demultiplexer using two E445’s; the
timing diagram for this configuration can be found on the
following page. Notice the serial outputs (SOUT) of the
lower order converter feed the serial inputs of the the higher
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock to
serial output propagation delay plus the setup time of the
serial input pins must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
TPD CLK to SOUT = 1150 ps and tS for SIN = −100 ps,
yields a minimum period of 1050 ps or a clock frequency of
950 MHz.
The clock frequency is significantly lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E445. By
delaying the clock feeding the second E445 relative to the
clock of the first E445 the frequency of operation can be
increased. The delay between the two clocks can be
increased until the minimum delay of clock to serial out
would potentially cause a serial bit to be swallowed
(Figure 7).
CLOCK A
CLOCK B
T
CLK
to SOUT
pd
800 ps
1150 ps
Figure 7. Cascade Frequency Limitation
Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock inputs
of the E445. By connecting the clock for the second E445 to
the complementary clock input pin the device will clock a
half a clock period after the first E445 (Figure 8). Utilizing
this simple technique will raise the potential conversion
frequency up to 1.4 GHz. The divide by eight clock of the
second E445 should be used to synchronize the parallel data
to the rest of the system as the parallel data of the two E445’s
will no longer be synchronized. This skew problem between
the outputs can be worked around as the parallel information
will be static for eight more clock pulses.
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MC10E445, MC100E445
CLOCK
CLOCK
700ps
(1.4GHz)
100ps
E445a
E445b
CLOCK A
SERIAL
INPUT
DATA
SIN
SIN
SOUT
SOUT
SIN
SIN
CLOCK B
T
CLK
to SOUT
pd
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
800ps
1150ps
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
PARALLEL OUTPUT DATA
Figure 8. Extended Frequency 1:8 Demultiplexer
CLK
SINa
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1 Dn+2 Dn+3
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Q0
Q1
Q2
Q3
Q4 (Q0 a)
Q5 (Q1 a)
Q6 (Q2 a)
Q7 (Q3 a)
SOUTa
SOUTb
CL/4a
Dn+1
Dn+2
Dn+3
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1 Dn+2 Dn+3
Dn-3 Dn-2 Dn-1
Dn-4
Dn
Dn+1
CL/4b
CL/8a
CL/8b
Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion
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10
MC10E445, MC100E445
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E445FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E445FNG
PLCC−28
(Pb−Free)
MC10E445FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E445FNR2G
PLCC−28
(Pb−Free)
MC100E445FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E445FNG
PLCC−28
(Pb−Free)
MC100E445FNR2
MC100E445FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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11
MC10E445, MC100E445
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
N
0.007 (0.180)
T L−M
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T L−M
T L−M
N
M
S
S
N
0.007 (0.180)
T L−M
H
Z
M
S
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
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12
MC10E445, MC100E445
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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For additional information, please contact your local
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MC10E445/D
相关型号：
MC100E446FNG
100E SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC28, LEAD FREE, PLASTIC, LCC-28
ROCHESTER
MC100E446FNR2G
100E SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC28, LEAD FREE, PLASTIC, LCC-28
ROCHESTER
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