MC100EL14DWG [ONSEMI]
5V ECL 1:5 Clock Distribution Chip; 5V ECL 1 ： 5时钟分配芯片
| 型号： | MC100EL14DWG |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL 1:5 Clock Distribution Chip |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EL14
5V ECL 1:5 Clock
Distribution Chip
The MC100EL14 is a low skew 1:5 clock distribution chip designed
explicitly for low skew clock distribution applications. The V pin, an
BB
internally generated voltage supply, is available to this device only.
For single-ended input conditions, the unused differential input is
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connected to V as a switching reference voltage. V may also
BB
BB
rebias AC coupled inputs. When used, decouple V and V via a
BB
CC
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V should be left open.
BB
The EL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
SOIC−20L
DW SUFFIX
CASE 751D
MARKING DIAGRAM
20
Features
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
• Multiplexed Clock Input
100EL14
AWLYYWWG
• The 100 Series Contains Temperature Compensation
1
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
with V = 0 V
EE
WL
YY
WW
G
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Q Output will Default LOW with Inputs Open or at V
EE
• Internal Input Pull−down Resistors on All Inputs, Pull−up Resistors
*For additional marking information, refer to
Application Note AND8002/D.
on Inverted Inputs
• Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 7
MC100EL14/D
MC100EL14
V
EN
V
NC SCLK CLK CLK
V
SEL
V
EE
CC
CC
BB
Table 1. PIN DESCRIPTION
20
19
18
17
16
15
14
13
12
11
PIN
CLK, CLK
FUNCTION
ECL Diff Clock Inputs
1 0
SCLK
EN
ECL Scan Clock Input
ECL Sync Enable
D
Q
SEL
ECL Clock Select Input
ECL Diff Clock Outputs
Reference Voltage Output
Positive Supply
Q
Q
0−4, 0−4
1
2
3
4
5
6
7
8
9
10
V
BB
V
CC
V
EE
Q0
Q1
Q2
Q3
Q4
Q0
Q1
Q2
Q3
Q4
Negative Supply
* All V pins are tied together on the die.
CC
NC
No Connect
Warning: All V and V pins must be externally connected to
CC
EE
Power Supply to guarantee proper operation.
Table 2. FUNCTION TABLE
Figure 1. Logic Diagram and Pinout Assignment
CLK*
SCLK*
SEL*
EN*
Q
L
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
X
X
X
H
L
H
L
(Note )
1. On next negative transition of CLK or SCLK
**Pins will default low when left open.
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
> 2 kV
> 200 V
> 4 kV
Machine Model
Charge Device Model
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
303 Devices
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
MC100EL14
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
8
CC
EE
I
EE
V
V
−8
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ≤ V
6
−6
V
V
EE
I
CC
V ≥ V
CC
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−20L
SOIC−20L
90
60
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−20L
30 to 35
°C/W
°C
JC
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
265
265
Pb−Free <2 to 3 sec @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC100EL14
Table 5. 100EL SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0.0 V (Note 3)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
Typ
32
Max
40
Min
Max
40
Min
Max
42
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
32
34
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3915
3170
3835
3190
3.62
3995
3305
4120
3445
4120
3525
3.74
3975
3190
3835
3190
3.62
4045
3295
4120
3380
4120
3525
3.74
3975
3190
3835
3190
3.62
4050
3295
4120
3380
4120
3525
3.74
OH
OL
IH
IL
BB
Common Mode Range
(Differential Configuration)
V
IHCMR
(Note 5)
V
V
< 500 mV
≥ 500 mV
1.3
1.5
4.6
4.6
1.2
1.4
4.6
4.6
1.2
1.4
4.6
4.6
PP
PP
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V .V can vary +0.8 V / −0.5 V.
CC EE
4. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V .The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak−to−peak voltage lies between V (min) and 1 V.
PP
Table 6. 100EL SERIES NECL DC CHARACTERISTICSV = 0.0 V; V = −5.0 V (Note 6)
CC
EE
−40°C
25°C
Typ
32
85°C
Typ
34
Min
Typ
Max
Min
Max
Min
Max
42
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
32
40
40
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1085 −1005 −880 −1025 −955
−880 −1025 −955
−880
OH
OL
−1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620
−1165
−1810
−1.38
−880 −1165
−1475 −1810
−1.26 −1.38
−880 −1165
−1475 −1810
−1.26 −1.38
−880
−1475
−1.26
IH
IL
BB
Common Mode Range
V
IHCMR
(Differential Configuration)
(Note 8)
V
V
< 500 mV
≥ 500 mV
−3.7
−3.5
−0.4
−0.4
−3.8
−3.6
−0.4
−0.4
−3.8
−3.6
−0.4
−0.4
PP
PP
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V .V can vary +0.8 V / −0.5 V.
CC EE
7. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V .The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak−to−peak voltage lies between V (min)and 1 V.
PP
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4
MC100EL14
Table 7. AC CHARACTERISTICS V = 5.0 V; V = 0.0 V or V = 0.0 V; V = −5.0 V (Note 9)
CC
EE
CC
EE
−40°C
Typ
1
25°C
Typ
1
85°C
Typ
1
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
f
Maximum Toggle Frequency
GHz
max
(See Figure 2, f
/Jitter)
MAX
t
t
Prop
Delay
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
520
470
470
720
770
770
580
530
530
680
680
680
780
830
830
630
580
580
830
880
880
ps
PLH
PHL
t
t
Part-to-Part Skew
Within-Device Skew (Note 10)
200
50
200
50
200
50
ps
ps
SKEW
Random Clock Jitter (RMS) @ 1 GHz
1
1
1
JITTER
(See Figure 2, f
Setup Time EN
Hold Time EN
/Jitter)
MAX
t
t
0
0
−133
0
ps
ps
S
250
150
230
250
150
230
140
250
150
230
H
V
Input Swing (Note 11)
1000
500
1000
500
1000
500
mV
ps
PP
t
r
t
f
Output Rise/Fall Times Q
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. V can vary +0.8 V / −0.5 V. Outputs are terminated through a 50 W resistor to V − 2.0 V.
EE
CC
10.Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
11. V (min) is the minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
PP
800
700
600
500
400
300
200
2.0
1.5
V
OUTPP
Jitter
1.0
0.5
0
200
400
600
800
1000
1200
1400
F
IN
(MHz)
Figure 2. Output Voltage Amplitude / RMS Jitter vs.
Input Frequency at Ambient Temperature (Typical)
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5
MC100EL14
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION4
†
Device
Package
Shipping
MC100EL14DW
SOIC−20L
38 Units / Rail
38 Units / Rail
MC100EL14DWG
SOIC−20L
(Pb−Free)
MC100EL14DWR2
MC100EL14DWR2G
SOIC−20L
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20L
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MC100EL14
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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7
MC100EL14
PACKAGE DIMENSIONS
SO−20 WB
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
0.25
T A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
C
T
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC100EL14/D
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