MC100EL1648_06 [ONSEMI]
5 VECL Voltage Controlled Oscillator Amplifier; 5 V ？ ECL压控振荡器放大器
| 型号： | MC100EL1648_06 |
| 厂家： | 
ONSEMI |
| 描述： | 5 VECL Voltage Controlled Oscillator Amplifier |
| 文件： | 总16页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EL1648
5 VꢀECL Voltage Controlled
Oscillator Amplifier
Description
The MC100EL1648 is a voltage controlled oscillator amplifier that
requires an external parallel tank circuit consisting of the inductor (L)
and capacitor (C). A varactor diode may be incorporated into the tank
circuit to provide a voltage variable input for the oscillator (VCO).
This device may also be used in many other applications requiring a
fixed frequency clock.
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MARKING
DIAGRAMS*
The MC100EL1648 is ideal in applications requiring a local
oscillator, systems that include electronic test equipment, and digital
high−speed telecommunications.
The MC100EL1648 is based on the VCO circuit topology of the
MC1648. The MC100EL1648 uses advanced bipolar process
technology which results in a design which can operate at an extended
frequency range.
8
SOIC−8
D SUFFIX
CASE 751
K1648
ALYW
G
8
1
1
8
The ECL output circuitry of the MC100EL1648 is not a traditional
open emitter output structure and instead has an on−chip termination
TSSOP−8
DT SUFFIX
CASE 948R
emitter resistor, R , with a nominal value of 510 W. This facilitates
1648
E
8
direct ac−coupling of the output signal into a transmission line.
Because of this output configuration, an external pull−down resistor is
not required to provide the output with a dc current path. This output is
intended to drive one ECL load (3.0 pF). If the user needs to fanout the
signal, an ECL buffer such as the EL16 (EL11, EL14) type Line
Receiver/Driver should be used.
ALYWG
1
G
1
14
SOEIAJ−14
M SUFFIX
CASE 965
KEL1648
ALYWG
Features
14
• Typical Operating Frequency Up to 1100 MHz
• Low−Power 19 mA at 5.0 Vdc Power Supply
• PECL Mode Operating Range: V = 4.2 V to 5.5 V with V = 0 V
1
1
CC
EE
• NECL Mode Operating Range: V = 0 V with V = −4.2 V
CC
EE
DFN8
MN SUFFIX
CASE 506AA
to −5.5 V
• Input Capacitance = 6.0 pF (TYP)
• Pb−Free Packages are Available
1
4
NOTE: The MC100EL1648 is NOT useable as a crystal oscillator.
A
L,
Y
= Assembly Location
= Wafer Lot
= Year
V
CC
V
CC
W
M
= Work Week
= Date Code
G or G = Pb−Free Package
BIAS POINT
TANK
EXTERNAL
TANK
CIRCUIT
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
OUTPUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
V
EE
V
EE
AGC
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 6
MC100EL1648/D
MC100EL1648
BIAS
8
V
V
AGC
5
V
NC TANK NC BIAS NC
13 12 11 10 9
V
EE
EE
EE
CC
7
6
14
8
1
2
3
4
1
2
3
4
5
6
7
TANK
V
CC
V
CC
OUT
V
CC
NC OUT NC AGC NC
V
EE
8 Lead
14 Lead
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
Figure 2. Pinout Assignments
Table 1. PIN DESCRIPTION
Pin No.
8 Lead
14 Lead
Symbol
Description
1
2, 3
4
12
TANK
OSC Input Voltage
Positive Supply
1, 14
V
CC
3
OUT
AGC
ECL Output
5
5
Automatic Gain Control Input
Negative Output
6, 7
8
7, 8
10
V
EE
BIAS
NC
OSC Input Reference Voltage
No Connect
2, 4, 7, 9, 11, 13
EP
Exposed pad must be connected to a sufficient thermal conduit. Electrically
connect to the most negative supply or leave floating open.
Table 2. ATTRIBUTES
Characteristic
Value
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 1 kV
> 100 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 3
Level 1
Level 1
Level 3
Level 3
Level 1
TSSOP−8
SOEIAJ−14
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 23 to 34
UL 94 V−0 @ 0.125 in
11
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
MC100EL1648
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
7 to 0
Unit
V
V
CC
V
EE
V
I
Power Supply PECL Mode
Power Supply NECL Mode
V
V
= 0 V
= 0 V
EE
−7 to 0
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6 to 0
−6 to 0
V
V
EE
I
CC
V ꢁ V
CC
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
SOIC−8
41 to 44
°C/W
JC
JA
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
TSSOP−8
41 to 44
°C/W
JC
JA
SOIC−14
SOIC−14
150
110
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
SOIC−14
41 to 44
°C/W
JC
JA
DFN8
DFN8
129
84
°C/W
°C/W
500 lfpm
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC100EL1648
Table 4. PECL DC CHARACTERISTICS V = 5.0 V; V = 0.0 V +0.8 / −0.5 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
13
Typ
19
Max
25
Min
13
Max
25
Min
13
Max
25
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
19
19
EE
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Automatic Gain Control Input
Bias Voltage (Note 4)
3950
3040
1690
1650
1.5
4170
3410
4610
3600
1980
1800
3950
3040
1690
1650
1.35
4170
3410
4610
3600
1980
1800
3950
3040
1690
1650
1.2
4170
3410
4610
3600
1980
1800
OH
OL
AGC
V
V
V
BIAS
IL
2.0
1.85
1.7
V
IH
I
L
Input Current
−5.0
−5.0
−5.0
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Output parameters vary 1:1 with V
.
CC
3. 1.0 MW impedance.
4. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point.
Table 5. NECL DC CHARACTERISTICS V = 0.0 V; V = −5.0 V +0.8 / −0.5 V (Note 5)
CC
EE
−40°C
25°C
Typ
19
85°C
Typ
19
Min
Typ
Max
Min
Max
Min
Max
25
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
13
19
25
13
25
13
EE
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Automatic Gain Control Input
Bias Voltage (Note 7)
−1050 −830
−399 −1050 −830
−399 −1050 −830
−399
OH
−1960 −1590 −1400 −1960 −1590 −1400 −1960 −1590 −1400
OL
AGC
−3310
−3350
−3.5
−3020 −3310
−3200 −3350
−3.65
−3020 −3310
−3200 −3350
−3.8
−3020
−3200
V
V
V
BIAS
IL
−3.0
−3.15
−3.3
V
IH
I
L
Input Current
−5.0
−5.0
−5.0
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Output parameters vary 1:1 with V
.
CC
6. 1.0 MW impedance.
7. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point.
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4
MC100EL1648
GENERIC TEST CIRCUITS: Bypass to Supply Opposite GND
V
CC
0.1 mF
0.1 mF
2 (14)
3 (1)
8 (10)
V
IN
F
OUT
4 (3)
**
L
C
1 KW
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = MMBV609
*
1 (12)
Tank #1
6 (7) 7 (8)
5 (5)
V
EE
*
Use high impedance probe (>1.0 MW must be
used).
** The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
100 mF 0.01 mF
0.1 mF 0.1 mF
8 pin (14 pin) Lead Package
Tank Circuit Option #1, Varactor Diode
V
CC
0.1 mF
3 (1)
0.1 mF
2 (14)
8 (10)
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35pF Variable Capacitance (@ 10 pF)
4 (3)
F
OUT
0.1mF
L
C
Note 1 Capacitor for tank may be variable type.
(See Tank Circuit #3.)
Note 2 Use high impedance probe (> 1 MW ).
1 (12)
Test Point
Tank #2
6 (7) 7 (8)
5 (5)
8 pin (14 pin) Lead Package
V
EE
100 mF 0.01 mF
0.1 mF 0.1 mF
Tank Circuit Option #2, Fixed LC
Figure 3. Typical Test Circuit with Alternate Tank Circuits
50%
V
P−P
t
a
PRF = 1.0MHz
Duty Cycle (Vdc) −
t
t
a
b
t
b
Figure 4. Output Waveform
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5
MC100EL1648
OPERATION THEORY
Figure 5 illustrates the simplified circuit schematic for the
Q2 and Q3, in conjunction with output transistor Q1,
provide a highly buffered output that produces a square
wave. The typical output waveform can be seen in Figure 4.
The bias drive for the oscillator and output buffer is provided
by Q9 and Q11 transistors. In order to minimize current, the
output circuit is realized as an emitter−follower buffer with
MC100EL1648. The oscillator incorporates positive feedback
by coupling the base of transistor Q6 to the collector of Q7. An
automatic gain control (AGC) is incorporated to limit the
current through the emitter−coupled pair of transistors (Q7 and
Q6) and allow optimum frequency response of the oscillator.
In order to maintain the high quality factor (Q) on the oscillator,
and provide high spectral purity at the output, transistor Q4 is
used to translate the oscillator signal to the output differential
pair Q2 and Q3. Figure 16 indicates the high spectral purity
of the oscillator output (pin 4 on 8−pin SOIC). Transistors
an on chip pull−down resistor R .
E
V
CC
2 (14)
V
CC
3 (1)
800 W
1.36 KW
3.1 KW
660 W
167 W
Q9
Q1
Q3
Q2
1.6 KW
OUTPUT
4 (3)
Q4
Q11
Q10
Q7 Q6
D1
330 W
Q8
Q5
D2
400 W
16 KW
82 W
400 W
660 W
510 W
V
7 (8)
BIAS
8 (10)
TANK
1 (12)
V
6 (7)
AGC
5 (5)
EE
EE
8 pin (14 pin) Lead Package
Figure 5. Circuit Schematic
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6
MC100EL1648
30
25
20
15
Measured Frequency (MHz)
Calculated Frequency (MHz)
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
*
The 1200 W resistor and the scope termination
10
5
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
8 pin (14 pin) Lead Package
0
0
300
500
1000
2000
10000
0.1mF
10mF
CAPACITANCE (pF)
2 (14)
3(1)
8 (10)
1200*
L
0.1mF
C
4 (3)
SIGNAL
UNDER
TEST
1 (12)
Tank #3
6 (7) 7 (8)
5 (5)
V
EE
100 mF 0.01 mF
0.1 mF 0.1 mF
Figure 6. Low Frequency Plot
100
80
60
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
40
20
*
The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
Measured Frequency (MHz)
Calculated Frequency (MHz)
8 pin (14 pin) Lead Package
0
0
0.2
0.3
300
0.1mF
10mF
CAPACITANCE (pF)
2 (14)
3(1)
8 (10)
1200*
L
0.1mF
C
4 (3)
SIGNAL
UNDER
TEST
1 (12)
Tank #3
6 (7) 7 (8)
5 (5)
V
EE
100 mF 0.01 mF
0.1 mF 0.1 mF
Figure 7. High Frequency Plot
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MC100EL1648
FIXED FREQUENCY MODE
The MC100EL1648 external tank circuit components are
used to determine the desired frequency of operation as
shown in Figure 8, tank option #2. The tank circuit
Only high quality surface−mount RF chip capacitors
should be used in the tank circuit at high frequencies. These
capacitors should have very low dielectric loss (high−Q). At
a minimum, the capacitors selected should be operating at
100 MHz below their series resonance point. As the desired
frequency of operation increases, the values of the tank
capacitor will decrease since the series resonance point is a
function of the capacitance value. Typically, the inductor is
realized as a surface−mount chip or a wound coil. In
addition, the lead inductance and board inductance and
capacitance also have an impact on the final operating point.
The following equation will help to choose the appropriate
values for your tank circuit design.
components have direct impact on the tuning sensitivity, I
,
EE
and phase noise performance. Fixed frequency of the tank
circuit is usually realized by an inductor and capacitor (LC
network) that contains a high Quality factor (Q). The plotted
curve indicates various fixed frequencies obtained with a
single inductor and variable capacitor. The Q of the
components in the tank circuit has a direct impact on the
resulting phase noise of the oscillator. In general, when the
Q is high the oscillator will result in lower phase noise.
570
1
f
0 +
Ǹ
2p
L * C
T T
Measured Frequency (MHz)
Calculated Frequency (MHz)
470
370
270
170
Where
L = Total Inductance
T
C = Total Capacitance
T
Figure 9 and Figure 10 represent the ideal curve of
inductance/capacitance versus frequency with one known
tank component. This helps the designer of the tank circuit
to choose desired value of inductor/capacitor component for
the wanted frequency. The lead inductance and board
inductance and capacitance will also have an impact on the
tank component values (inductor and capacitor).
50
70
0
−30
0.3
300
500
1000
2000
10000
45
CAPACITANCE (pF)
40
35
30
V
CC
0.1 mF
0.1 mF
2 (14)
4 (3)
Inductance vs. Frequency with 5 pF Cap
25
3 (1)
20
15
10
8 (10)
0.1 mF
L
C
F
OUT
5
0
1 (12)
Test
Point
Tank #2
V
400
700
1000
1300
160
6 (7) 7 (8)
5 (5)
FREQUENCY (MHz)
EE
Figure 9. Capacitor Value Known (5 pF)
50
45
100 mF 0.01 mF
0.1 mF 0.1 mF
40
35
30
25
20
15
10
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
Note 1 Capacitor for tank may be variable type.
(See Tank Circuit #3.)
Note 2 Use high impedance probe (> 1 MW ).
Capacitance vs. Frequency with 4 nH Inductance
8 pin (14 pin) lead package
Q
≥ 100
L
5
0
Figure 8. Fixed Frequency LC Tank
400
700
1000
1300
160
FREQUENCY (Hz)
Figure 10. Inductor Value Known (4 nH)
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8
MC100EL1648
VOLTAGE CONTROLLED MODE
The tank circuit configuration presented in Figure 11,
When operating the oscillator in the voltage controlled
mode with Tank Circuit #1 (Figure 3), it should be noted that
the cathode of the varactor diode (D), pin 8 (for 8 lead
package) or pin 10 (for 14 lead package) should be biased at
Voltage Controlled Varactor Mode, allows the VCO to be
tuned across the full operating voltage of the power supply.
Deriving from Figure 6, the tank capacitor, C, is replaced
with a varactor diode whose capacitance changes with the
voltage applied, thus changing the resonant frequency at
which the VCO tank operates as shown in Figure 3, tank
option #1. The capacitive component in Equation 1 also
needs to include the input capacitance of the device and
other circuit and parasitic elements.
least 1.4 V above V
.
EE
Typical transfer characteristics employing the
capacitance of the varactor diode (plus the input capacitance
of the device, about 6.0 pF typical) in the voltage controlled
mode is shown in Plot 1, Dual Varactor MMBV609 V vs.
in
Frequency. Figure 6, Figure 7, and Figure 8 show the
accuracy of the measured frequency with the different
variable capacitance values. The 1.0 kW resistor in Figure 11
is used to protect the varactor diode during testing. It is not
necessary as long as the dc input voltage does not cause the
diode to become forward biased. The tuning range of the
oscillator in the voltage controlled mode may be calculated
as follows:
190
170
150
130
110
90
Ǹ
Ǹ
C (max) ) C
f
f
D
S
max
min
+
C (min) ) C
D
S
70
Where
Where
50
1
0
2
4
6
8
10
f
+
min
Ǹ
(
)
2p L(C (max) ) C
V , INPUT VOLTAGE (V)
in
D
S
Figure 12. Plot 1. Dual Varactor MMBV609,
V
IN vs. Frequency
C
S
= Shunt Capacitance (input plus external
capacitance)
V
CC
C
= Varactor Capacitance as a function of bias
voltage
D
0.1 mF
0.1 mF
2 (14)
3 (1)
Good RF and low−frequency bypassing is necessary on
the device power supply pins. Capacitors on the AGC pin
and the input varactor trace should be used to bypass the
AGC point and the VCO input (varactor diode),
guaranteeing only dc levels at these points. For output
frequency operation between 1.0 MHz and 50 MHz, a 0.1 mF
capacitor is sufficient. At higher frequencies, smaller values
of capacitance should be used; at lower frequencies, larger
values of capacitance. At high frequencies, the value of
bypass capacitors depends directly on the physical layout of
the system. All bypassing should be as close to the package
pins as possible to minimize unwanted lead inductance.
Several different capacitors may be needed to bypass
various frequencies.
8 (10)
V
IN
4 (3)
L
*
C
1 KW
1 (12)
Tank #1
6 (7) 7 (8)
5 (5)
**
V
EE
F
0.1 mF 0.1 mF
OUT
100 mF 0.01 mF
*Use high impedance probe (>1.0 MegW must be used).
**The 1200 W resistor and the scope termination imped-
ance constitute a 25:1 attenuator probe. Coax shall be
CT−070−50 or equivalent.
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = MMBV609
8 pin (14 pin) lead package
Figure 11. Voltage Controlled Varactor Mode
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MC100EL1648
WAVE−FORM CONDITIONING − SINE OR SQUARE WAVE
The peak−to−peak swing of the tank circuit is set
Figure 13. At frequencies above 100 MHz typical, it may be
desirable to increase the tank circuit peak−to−peak voltage
in order to shape the signal into a more square waveform at
the output of the MC100EL1648. This is accomplished by
tying a series resistor (1.0 kW minimum) from the AGC to
the most positive power potential (+5.0 V if a positive volt
supply is used, ground if a −5.2 V supply is used). Figure 14
illustrates this principle.
internally by the AGC pin. Since the voltage swing of the
tank circuit provides the drive for the output buffer, the AGC
potential directly affects the output waveform. If it is desired
to have a sine wave at the output of the MC100EL1648, a
series resistor is tied from the AGC point to the most
negative power potential (ground if positive volt supply is
used, −5.2 V if a negative supply is used) as shown in
+5.0Vdc
+5.0Vdc
1
14
1
7
14
10
12
10
12
3
5
Output
3
5
Output
1.0k min
7
8
8
Figure 13. Method of Obtaining a Sine−Wave Output
Figure 14. Method of Extending the Useful Range
of the MC100EL1648 (Square Wave Output)
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MC100EL1648
SPECTRAL PURITY
99.8
99.9
100.0
100.1
100.2
B.W. = 10 kHz, Center Frequency = 100 MHz
Scan Width = 50 kHz/div, Vertical Scale = 10 dB/div
Figure 15. Spectral Purity
0.1 mF
10 mF
2 (14)
3(1)
8 (10)
1200*
L
0.1 mF
C
4 (3)
SIGNAL
UNDER
TEST
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
1 (12)
Tank #3
6 (7) 7 (8)
5 (5)
V
EE
** The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
100 mF 0.01 mF
0.1 mF 0.1 mF
8 pin (14 pin) Lead Package
Spectral Purity Test Circuit
Figure 16. Spectral Purity of Signal Output for 200 MHz Testing
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC100EL1648
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EL1648D
SOIC−8, Narrow Body
98 Units / Rail
98 Units / Rail
MC100EL1648DG
SOIC−8, Narrow Body
(Pb−Free)
MC100EL1648DR2
MC100EL1648DR2G
SOIC−8, Narrow Body
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8, Narrow Body
(Pb−Free)
MC100EL1648DT
MC100EL1648DTG
TSSOP−8
100 Units / Rail
100 Units / Rail
TSSOP−8
(Pb−Free)
MC100EL1648DTR2
MC100EL1648DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EL1648M
SOEAIJ−14
50 Units / Rail
50 Units / Rail
MC100EL1648MG
SOEAIJ−14
(Pb−Free)
MC100EL1648MEL
MC100EL1648MELG
SOEAIJ−14
2000 / Tape & Reel
2000 / Tape & Reel
SOEAIJ−14
(Pb−Free)
MC100EL1648MNR4
MC100EL1648MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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12
MC100EL1648
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
MC100EL1648
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T
U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
_
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
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14
MC100EL1648
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
−−−
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
10.50 0.390
5.45 0.201
D
E
e
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
0.70
−−−
10
0.90 0.028
10
0.035
0.056
0
_
_
_
_
Q
1
Z
1.42
−−−
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15
MC100EL1648
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10
0.05
C A
B
8 X b
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC100EL1648/D
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