MC100ELT26D [ONSEMI]
Evaluation Board Manual for High Frequency SOIC 8; 评估板手册高频SOIC 8
| 型号： | MC100ELT26D |
| 厂家： | 
ONSEMI |
| 描述： | Evaluation Board Manual for High Frequency SOIC 8 |
| 文件： | 总20页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ECLSOIC8EVB
Evaluation Board Manual
for High Frequency SOIC 8
http://onsemi.com
EVALUATION BOARD MANUAL
Board Lay−Up
INTRODUCTION
The 8−lead SOIC evaluation board is implemented in four
layers with split (dual) power supplies (Figure 2.
Evaluation Board Lay−up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the
50 W internal impedance in the oscilloscope as a termination
for ECL devices. The first layer or primary trace layer is
0.008″ thick Rogers RO4003 material, which is designed to
have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground plane and a portion of the
ON Semiconductor has developed an evaluation board for
the devices in 8−lead SOIC package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 8−lead SOIC device
samples. The board provides a high bandwidth 50 W
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways, depending on
device under test (See Table 1. Configuration List).
This evaluation board manual contains:
plane is the V power plane. The FR4 dielectric material is
EE
placed between second and third layer and between third and
fourth layer. The third layer is also 1.0 oz copper ground
• Information on 8−lead SOIC Evaluation Board
• Assembly Instructions
• Appropriate Lab Setup
plane and a portion of this layer is V power plane. The
CC
fourth layer is the secondary trace layer.
• Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Figure 1. Top and Bottom View of the 8−lead SOIC Evaluation Board
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
August, 2004 − Rev. 1
ECLSOIC8EVB/D
ECLSOIC8EVB
LAY−UP DETAIL
4 LAYER
SILKSCREEN (TOP SIDE)
LAYER 1 (TOP SIDE)
0.062 $ 0.007
ROGERS 4003 0.008 in
LAYER 2 (GROUND AND VEE PLANE P1) 1 OZ
FR−4 0.020 in
LAYER 3 (GROUND AND VCC PLANE P2) 1 OZ
FR−4 0.025 in
LAYER 4 (BOTTOM SIDE)
Figure 2. Evaluation Board Lay−up
Board Layout
devices and the relevant configuration that utilizes this PCB
board. List of components and simple schematics are located
in Figures 4 through 14. Place SMA connectors on J1
through J7, 50 W chip resistors on R1 through R7, and chip
capacitors C1 through C4 according to configuration
figures. (C1 and C2 are 0.01 mF and C3 and C4 are 0.1 mF).
The 8−lead SOIC evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figure 3. The evaluation board has at least
eleven possible configurable options. Table 1. list the
Top View
Bottom View
Figure 3. Evaluation Board Layout
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2
ECLSOIC8EVB
Table 1. Configuration List
ECLinPS PlusE
ECLinPS LiteE
Device
Comments
See Figure 4
See Figure 4
See Figure 4
See Figure 6
See Figure 5
Configuration
Device
Comments
See Figure 4
See Figure 5
See Figure 4
See Figure 5
See Figure 6
See Figure 6
See Figure 5
See Figure 4
See Figure 7
See Figure 7
See Figure 4
See Figure 4
See Figure 4
See Figure 8
See Figure 6
See Figure 9
Configuration
MC10EP01D/MC100EP01D
MC10EP05D/MC100EP05D
MC10EP08D/MC100EP08D
MC10EP11D/MC100EP11D
1
1
1
3
2
MC10EL01D/MC100EL01D
MC10EL04D/MC100EL04D
MC10EL05D/MC100EL05D
MC10EL07D/MC100EL07D
MC10EL11D/MC100EL11D
MC10EL12D/MC100EL12D
MC10EL16D/MC100EL16D*
MC10EL31D/MC100EL31D
MC10EL32D/MC100EL32D
MC10EL33D/MC100EL33D
MC10EL35D/MC100EL35D
MC10EL51D/MC100EL51D
MC10EL52D/MC100EL52D
MC10EL58D/MC100EL58D
MC10EL89D/MC100EL89D
1
2
1
2
3
3
2
1
4
4
1
1
1
5
3
6
MC10EP16D/
MC100EP16D*
MC100EP16FD*
See Figure 5
See Figure 5
2
2
MC10EP16TD/
MC100EP16TD*
MC100EP16VAD*
See Figure 5
See Figure 5
See Figure 8
See Figure 5
See Figure 5
See Figure 4
See Figure 7
See Figure 7
See Figure 4
See Figure 4
See Figure 4
See Figure 8
See Figure 6
See Figure 9
2
2
5
2
2
1
4
4
1
1
1
5
3
6
MC100EP16VBD*
MC100EP16VCD*
MC100EP16VSD*
MC100EP16VTD*
MC10EP31D/MC100EP31D
MC10EP32D/MC100EP32D
MC10EP33D/MC100EP33D
MC10EP35D/MC100EP35D
MC10EP51D/MC100EP51D
MC10EP52D/MC100EP52D
MC10EP58D/MC100EP58D
MC100EP89D
MC10ELT20D/
MC100ELT20D
MC10ELT21D/
MC100ELT21D
See Figure 10
See Figure 11
7
8
MC10ELT22D/
MC100ELT22D
MC100ELT23D
See Figure 12
See Figure 13
9
MC10ELT26D/
MC100ELT26D
10
MC10EPT20D/
MC100EPT20D
MC10ELT28D/
MC100ELT28D
See Figure 14
11
MC100EPT21D*
MC100EPT22D
MC100EPT23D*
MC100EPT26D*
See Figure 10
See Figure 11
See Figure 12
See Figure 13
7
8
9
Low Voltage ECLinPSE
Comments
10
Device
MC100LVEL01D
MC100LVEL05D
MC100LVEL11D
MC100LVEL12D
MC100LVEL16D*
MC100LVEL31D
MC100LVEL32D
MC100LVEL33D
MC100LVEL51D
MC100LVEL58D
MC100LVELT22D
MC100LVELT23D
Configuration
See Figure 4
See Figure 4
See Figure 6
See Figure 6
See Figure 5
See Figure 4
See Figure 7
See Figure 7
See Figure 4
See Figure 8
See Figure 11
See Figure 12
1
1
3
3
2
1
4
4
1
5
8
9
Low Voltage ECLinPS Plus
Comments
Device
MC100LVEP11D
MC100LVEP16D*
Configuration
See Figure 6
3
2
See Figure 5
*See Appendix for additions or modifications to the current
configuration.
ECLinPS MAXE
Device
Comments
See Figure 6
See Figure 5
Configuration
NB6L11D
NB6L16D
3
2
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3
ECLSOIC8EVB
Evaluation Board Assembly Instructions
On the top side of the evaluation board solder the four
surface mount test point clips to the pads labeled V , V
The 8−lead SOIC evaluation board is designed for
characterizing devices in a 50 W laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of termination resistor
or bypassing capacitor depending on the input/output
configuration (see Table 1. Configuration List). Table 17
contains the Bill of Materials for this evaluation board.
,
CC EE
and GND. The V clip connects directly to pin 8 of the
CC
device. The V clip connects directly to pin 5 of the device.
EE
There are two GND clip footprints which can be connected
to the ground plane of the evaluation board depending on the
setup configuration.
It is recommended to solder 0.01 mF capacitors to C1 and
C2 to reduce the unwanted noise from the power supplies.
C3 and C4 pads are provided for 0.1 mF capacitor to further
diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.
Solder the Device on the Evaluation Board
The soldering can be accomplished by hand soldering or
soldering re−flow techniques. Make sure pin 1 of the device
is located next the white dotted mark U1 and all the pins are
aligned to the footprint pads. Solder the 8−lead SOIC device
to the evaluation board.
Termination
All ECL outputs need to be terminated to V (V = V
TT
TT
CC
Connecting Power and Ground Planes
–2.0 V = GND) via a 50 W resistor in a split power supply
lab set−up. 0603 chip resistor pads are provided on the
bottom side of the evaluation board to terminate the ECL
driver (More information on termination is provided in
AN8020). Solder the chip resistors to the bottom side of the
board on the appropriate input of the device pins labeled R1,
R2, R3, R4, R6, and R7, depending on the specific device.
For standard ECL lab setup and test, a split (dual) power
supply is required enabling the 50 W internal impedance in
the oscilloscope to be used as a termination of the ECL
signals (V = V – 2.0 V, in split power supply setup, V
TT
CC
TT
is the system ground, V is 2.0 V, and V is –3.0 V or
CC
EE
–1.3 V; see Table 2: Power Supply Levels).
Installing the SMA Connectors
Table 2. Power Supply Levels
Each configuration indicates the number of SMA
connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board. Please
note that alignment of the signal connector pin of the SMA
can influence the lab results. The reflection and launch of the
signals are largely influenced by imperfect alignment and
soldering of the SMA connector.
Power Supply
5.0 V
V
V
GND
0.0 V
0.0 V
0.0 V
CC
EE
2.0 V
2.0 V
2.0 V
−3.0 V
−1.3 V
−0.5 V
3.3 V
2.5 V
The power supply for voltage level translating device need
slight modification as indicated in Table 3. Power Supply
Levels for Translators.
Validating the Assembled Board
Table 3. Power Supply Levels for Translators
After assembling the evaluation board, it is recommended
to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.
V
CC
V
EE
GND
PECL Translators
3.3 V / 5.0 V
0.0 V
0.0 V
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ECLSOIC8EVB
CONFIGURATIONS
V
CC
GND
C4
0.1 mF
R1
50 W
C1
0.01 mF
J1
J2
J3
J4
R2
50 W
DUT
J5
J6
R3
50 W
C2
0.01 mF
R4
50 W
C3
0.1 mF
V
EE
GND
Figure 4. Configuration 1 Schematic
Table 4. Configuration 1
Pin 1
J1 R1
Pin 2
J2 R2
Pin 3
J3 R3
Pin 4
Pin 5
Pin 6
J6 R6
Pin 7
Pin 8
J4 R4 C2 C3
J7 R7 C1 C4
Device
MC10EL01D/MC100EL01D
MC10EL05D/MC100EL05D
MC10EL31D/MC100EL31D
MC10EL35D/MC100EL35D
MC10EL51D/MC100EL51D
MC10EL52D/MC100EL52D
MC100LVEL01D
MC100LVEL05D
MC100LVEL31D
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes
MC100LVEL51D
MC10EP01D/MC100EP01D
MC10EP05D/MC100EP05D
MC10EP08D/MC100EP08D
MC10EP31D/MC100EP31D
MC10EP35D/MC100EP35D
MC10EP51D/MC100EP51D
MC10EP52D/MC100EP52D
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
R2
50 W
DUT
J2
J3
J7
J6
Pin 6
R3
50 W
C2
0.01 mF
Pin 5
C3
0.1 mF
J4
(Optional)
V
EE
GND
Figure 5. Configuration 2 Schematic
Table 5. Configuration 2
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Device
MC10EL04D/MC100EL04D
MC10EL07D/MC100EL07D
MC10EL16D/MC100EL16D*
MC100LVEL16D*
MC10EP16D/MC100EP16D*
MC100EP16FD*
MC100LVEP160*
No No Yes Yes Yes Yes No No Yes Yes Yes No Yes No Yes Yes
MC10EP16TD/MC100EP16TD*
MC100EP16VAD*
MC100EP16VBD*
MC100EP16VSD*
MC100EP16VTD*
NB6L160D
*See Appendix for additional or modification to the current configuration
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
J1
J2
J3
J4
R7
50 W
DUT
J7
J6
Pin 6
R6
50 W
C2
0.01 mF
Pin 5
C3
0.1 mF
V
EE
GND
Figure 6. Configuration 3 Schematic
Table 6. Configuration 3
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Device
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
MC10EL11D/MC100EL11D
MC10EL12D/MC100EL12D
MC10EL89D/MC100EL89D
MC100LVEL11D
MC100LVEL12D
Yes No Yes No Yes No Yes No Yes Yes Yes Yes Yes Yes Yes Yes
MC10EP11D/MC100EP11D
MC100EP89D
MC100LVEP11D
NB6L11D
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
R1
50 W
C1
0.01 mF
J1
J2
R2
50 W
DUT
J7
J6
Pin 6
R3
50 W
C2
0.01 mF
J3
Pin 5
C3
0.1 mF
J4
(Optional)
V
EE
GND
Figure 7. Configuration 4 Schematic
Table 7. Configuration 4
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Device
MC10EL32D/MC100EL32D
MC10EL33D/MC100EL33D
MC100LVEL32D
Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No Yes No Yes Yes
MC100LVEL33D
MC10EP32D/MC100EP32D
MC10EP33D/MC100EP33D
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
R2
50 W
DUT
J2
J3
J7
J6
Pin 6
Pin 5
R3
50 W
C2
0.01 mF
R4
50 W
C3
0.1 mF
J4
(Optional)
V
EE
GND
Figure 8. Configuration 5 Schematic
Table 8. Configuration 5
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Device
MC100EP16VCD*
MC10EL58D/MC100EL58D
MC100LVEL58D
No No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes
MC10EP58D/MC100EP58D
*See Appendix for addition or modification to the current configuration
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
R7
50 W
(optional)
DUT
J2
J3
J7
Pin 6
Pin 5
Short
V
EE
GND
Figure 9. Configuration 6 − Translator Schematic
Table 9. Configuration 6
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
R7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7
C1 C4
Device
MC10ELT20D/MC100EL20D
MC10EPT20D/MC100EPT20D
No No Yes No Yes No No No No No No No Yes Optional Yes Yes
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
R2
50 W
DUT
J2
J3
J7
Pin 6
Pin 5
R3
50 W
Short
V
EE
GND
Figure 10. Configuration 7 − Translator Schematic
(Unloaded Testing Condition)
Table 10. Configuration 7
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Device
MC10ELT21D/MC100EL21D
MC100EPT21D
No No Yes Yes Yes Yes No No No No No No Yes No Yes Yes
*See Appendix for loaded testing condition.
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
J1
J2
J3
J4
R7
50 W
(optional)
DUT
J7
J6
Pin 6
Pin 5
R6
50 W
(optional)
Short
V
EE
GND
Figure 11. Configuration 8 − Translator Schematic
Table 11. Configuration 8
Device
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
R6
Pin 7
R7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6
J57
C1 C4
MC10ELT22D/
MC100EL22D
Yes No Yes No Yes No Yes No No No Yes Optional Yes Optional Yes Yes
MC100LVELT22D
MC100EPT22D
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
R1
50 W
C1
0.01 mF
J1
J2
J3
J4
R2
50 W
DUT
J7
J6
Pin 6
Pin 5
R3
50 W
R4
50 W
Short
V
EE
GND
Figure 12. Configuration 9 − Translator Schematic
(Unloaded Testing Condition)
Table 12. Configuration 9
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Device
MC100EL23D
Yes
MC100LVELT23D
Yes Yes Yes Yes Yes
Yes Yes No No Yes No Yes No Yes Yes
MC100EPT23D
*See Appendix for loaded testing condition.
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
C1
0.01 mF
R2
50 W
DUT
J2
J3
J7
J6
R3
50 W
Pin 6
Pin 5
Short
V
EE
GND
Figure 13. Configuration 10 − Translator Schematic
(Unloaded Testing Condition)
Table 13. Configuration 10
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4
Device
MC10ELT26D/MC100ELT26D
MC100EPT26D
Yes
Yes Yes
No No Yes Yes Yes Yes No No No No Yes Yes
No
*See Appendix for loaded testing condition.
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ECLSOIC8EVB
V
CC
GND
C4
0.1 mF
Pin 1
Pin 2
Pin 3
Pin 4
Pin 8
Pin 7
R1
50 W
C1
0.01 mF
J2
R2
50 W
DUT
J2
J3
J3
J7
R6
50 W
(optional) J6
Pin 6
Pin 5
Short
V
EE
GND
Figure 14. Configuration 11 − Translator Schematic
Table 14. Configuration 11
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
R6
Pin 7
Pin 8
J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6
J7 R7 C1 C4
Device
MC10ELT28D/MC100ELT28D
Yes Yes Yes Yes Yes No Yes No No No Yes Optional Yes No Yes Yes
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ECLSOIC8EVB
LAB SETUP
Power Supply
V
CC
GND
OUT1
OUT1
Test Measuring
Equipment
J1
J2
J7
Channel 1
Differential
Signal Generator
DUT
Channel 2
TRIGGER
OUT2
J3
J6
J4
OUT2
TRIGGER
V GND
EE
Power Supply
Figure 15. Example of Standard Lab Setup (Configuration 1)
1. Connect appropriate power supplies to V , V
,
EE
The power supply for voltage level translating device need
slight modification as indicated in Table 16.
CC
and GND.
For standard ECL lab setup and test, a split (dual)
power supply is required enabling the 50 W
internal impedance in the oscilloscope to be used
Table 16. Power Supply Levels for Translators
V
CC
V
EE
GND
as a termination of the ECL signals (V = V
TT
CC
3.3 V / 5.0 V
0.0 V
0.0 V
PECL Translators
– 2.0 V, in split power supply setup, V is the
TT
system ground, V is 2.0 V, and V is –3.0 V or
–1.3 V; see Table 15).
CC
EE
2. Connect a signal generator to the input SMA
connectors. Setup input signal according to the
device data sheet.
3. Connect a test measurement device on the device
output SMA connectors.
Table 15. Power Supply Levels
Power Supply
5.0 V
V
V
GND
0.0 V
0.0 V
0.0 V
CC
EE
2.0 V
2.0 V
2.0 V
−3.0 V
−1.3 V
−0.5 V
NOTE: The test measurement device must contain 50 W
3.3 V
termination.
2.5 V
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ECLSOIC8EVB
Table 17. Bill of Materials
Components
Manufacturer
Description
Part Number
Web Site
SMA Connector
Rosenberger
SMA Connector, Side
Launch, Gold Plated
32K243−40ME3
http://www.rosenberger.de
http://www.rosenbergerna.com
Johnson
Components*
SMA Connector, Side
Launch, Gold Plated
142−0701−851
http://www.johnsoncomponents.com
Surface Mount Test
Points
Keystone*
SMT Miniature Test Point
SMT Compact Test Point
5015
5016
http://www.keyelco.com
Thru−Hole Mount
5005−5009
Compact Test Point
Chip Capacitor
Chip Resistor
AVC Corporation*
Vishay Dale*
0603 0.01 mF ±10%
0603 0.1 mF ±10%
06035C103KAT2A
06035C104KAT2A
CRCW060351R1J
http://www.avxcorp.com
http://www.vishay.com
0603 50 W ± 1% Thick
Film Resistor
Evaluation Board
Device Samples
ON Semiconductor SOIC 8 Evaluation Board
ON Semiconductor SOIC 8 Package Device
ECLSOIC8EVB
Various
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*Components are available through most distributors, i.e. www.newark.com, www.digikey.com
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ECLSOIC8EVB
Appendix A (Modified Configurations)
MC100EP16VSD
This device has an option of varying the output swing
amplitude and being driven single−endedly. In order to
utilize these options, Configuration 2 needs to be modified.
MC10EL16D/MC100EL16D
MC100LVEL16D
MC10EP16D/MC100EP16D
MC10EP16DF/MC100EP16DF
MC100EP16VAD
Output Swing Control
1. Connect a SMA connector on J1
2. Add a decoupling capacitor between J1 and V
MC100LVEP16D
CC
The devices listed above have the option of being driven
(0.01 mF)
single−endedly by using the provided V pin of the device.
In order to drive it single−endedly, Configuration 2 needs to
be modified.
BB
Drive Single−Endedly
1. Remove the 50 W chip resistor from R3.
2. Short pin 3 and pin 4 together.
Option A) Short R3 and R4.
Or
1. Remove the 50 W chip resistor from R3.
2. Short pin 3 and pin 4 together.
Option A) Short R3 and R4 trace pads.
Or
Option B) Place a SMA connector on J4 and use
a cable with SMA connectors to short
J3 and J4 connectors.
Option B) Place a SMA connector on J4 and use
a cable with SMA connectors to short
J3 and J4 connectors.
MC100EP16VTD
This device has an option of varying the output swing
amplitude and internal termination. In order to utilize these
options, Configuration 2 needs to be modified.
MC10EP16D/MC100EP16DT
This device has an option of being 50 W terminated
internally. To evaluate the internal 50 W resistor of the
device, Configuration 2 needs to be modified.
1. Remove the 50 W chip resistors from R2 and R3.
Output Swing Control
1. Connect a SMA connector on J1
2. Add a decoupling capacitor between J1 and V
CC
2. Short R1 and R4 to V (GND).
TT
(0.0 1 mF)
Option A) Short R1 and R4 to V (GND).
TT
Internal Termination
Or
1. Remove the 50 W chip resistors from R2 and R3.
2. Short R1 and R4 to V (GND)
Option B) Place SMA connectors on J1 and J4.
Place shorting barrels on J1 and J4
SMA connector.
TT
Option A) Short R1 and R4 to V (GND).
TT
Or
MC100EP16VBD
This device has an option of single−ended feedback
output and being driven single−endedly using the V . To
Option B) Place SMA connectors on J1 and J4.
Place shorting barrels on J1 and J4
SMA connector.
BB
utilize the feedback option and drive it single−endedly,
Configuration 2 needs to be modified.
MC10ELT21D/MC100EL21D
MC100EL23D
MC10ELT26D/MC100ELT26D
MC100EPT21D
Feedback option
1. Connect a SMA connector on J1
MC100EPT23D
MC100EPT26D
MC100LVELT23
Drive single−endedly
2. Remove the 50 W chip resistor from R3.
3. Short pin 3 and pin 4 together.
Option A) Short R3 and R4.
Or
The TTL output data presented in the data sheet are obtained
under 500 W load resistor in parallel with 20 pF fixture
capacitance. In order to obtain comparable data as in the data
sheet, the evaluation board needs to be modified.
1. Cut the output trace so that the 0402* size chip
resistor can be placed over the cut out trace.
2. Solder a 450 W chip resistor across the cut out
trace.
Option B) Place a SMA connector on J4 and use
a cable with SMA connectors to short
J3 and J4 connectors.
MC100EP16VCD
This device has an option of single−ended feedback
output with an enable pin. To utilize the feedback option and
enable option, Configuration 5 needs to be modified.
1. Connect a SMA connector on J1.
*Any size chip resistor can be used. The recommended size of the
chip resistor is 0402, to reduce the effect of parasitic with a 17 mil
trace width. 450 W in series with 50 W instrument resistance add up
to 500 W loaded condition.
2. Remove the 50 W chip resistor from R3.
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18
ECLSOIC8EVB
Appendix B (Gerber Files)
Top Layer
Second Layer (V and Ground Plane
EE
Third Layer (V and Ground Plane)
Bottom Layer
CC
Figure 16. Gerber Files
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19
ECLSOIC8EVB
ECLinPS, ECLinPS Lite, ECLinPS Plus, and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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ECLSOIC8EVB/D
相关型号：
MC100ELT28DTR2G
Translator, TTL to Differential PECL and Differential PECL to TTL, TSSOP 8 3.0x3.0x0.95 mm, 2500-REEL
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