MC100EP08DTR2G [ONSEMI]
差分 2 输入 XOR/XNOR 门极;
| 型号： | MC100EP08DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 差分 2 输入 XOR/XNOR 门极 栅 光电二极管 逻辑集成电路 石英晶振 栅极 |
| 文件： | 总11页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP08, MC100EP08
3.3V / 5VꢀECL 2-Input
Differential XOR/XNOR
Description
The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is
ideal for applications requiring the fastest AC performance available.
The 100 Series contains temperature compensation.
http://onsemi.com
MARKING DIAGRAMS*
Features
• 250 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
8
8
8
HEP08
ALYWG
G
KEP08
ALYWG
G
1
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
SOIC−8
D SUFFIX
CASE 751
with V = 0 V
EE
1
1
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
• Safety Clamp on Inputs
8
1
8
1
8
HP08
ALYWG
G
KP082
ALYWG
G
• Q Output Will Default LOW with Inputs Open or at V
• These are Pb−Free Devices
EE
1
TSSOP−8
DT SUFFIX
CASE 948R
1
1
5J DG
2Y DG
G
G
4
4
DFN8
MN SUFFIX
CASE 506AA
H
K
= MC10
= MC100
A
L
= Assembly Location
= Wafer Lot
5J = MC10
2Y = MC100
Y
W
G
= Year
= Work Week
= Pb−Free Package
D
= Date Code
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
September, 2012 − Rev. 6
MC10EP08/D
MC10EP08, MC100EP08
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0
D0
1
2
8
7
V
CC
D0, D1, D0, D1
Q, Q
ECL Data Inputs
ECL Data Outputs
V
CC
Positive Supply
Negative Supply
Q
V
EE
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
D1
D1
3
4
6
5
Q
Table 2. TRUTH TABLE
D0*
D1*
D0**
D1**
Q
Q
L
L
H
H
L
H
L
H
H
L
H
L
H
L
L
H
L
L
V
H
H
L
EE
H
L
H
*
Pins will default LOW when left open.
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
** Pins will default to 0.666% of V when left open.
CC
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
135 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
2
MC10EP08, MC100EP08
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
EE
= 0 V
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
I
CC
V w V
CC
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
−40 to +85
°C
°C
A
T
Storage Temperature Range
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
TSSOP−8
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
Wave Solder
Pb−Free <2 to 3 sec @ 260°C
(Note 2)
265
°C
sol
q
Thermal Resistance (Junction−to−Case)
DFN8
35 to 40
°C/W
JC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
−40°C
25°C
Typ
30
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
20
Typ
Max
Min
Max
Min
20
Max
38
Unit
mA
mV
mV
mV
mV
V
I
EE
28
36
20
38
32
V
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2165 2290 2415
1365 1490 1615
2230 2355 2480
1430 1555 1680
2290
1490
2215
1490
2.0
2415
1615
2540
1740
2540
1815
3.3
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
2090
1365
2.0
2415
1690
3.3
2155
1430
2.0
2480
1755
3.3
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
IHCMR
I
I
Input HIGH Current
150
150
150
mA
mA
IH
Input LOW Current
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
4. All loading with 50 W to V − 2.0 V.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
3
MC10EP08, MC100EP08
Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
−40°C
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
20
28
36
20
38
20
38
V
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
3865 3940 4115 3930 4055 4180 3990 4115 4240
3065 3190 3315 3130 3255 3380 3190 3315 3440
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
3790
3065
2.0
4115 3855
3390 3130
4180 3915
3455 3190
4240
3515
5.0
IH
IL
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 8)
5.0
2.0
5.0
2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
7. All loading with 50 W to V − 2.0 V.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. 10EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 9)
CC
EE
−40°C
Typ
28
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
20
Max
Min
Max
Min
Max
38
Unit
mA
mV
mV
mV
mV
V
I
EE
36
20
38
20
VOH
Output HIGH Voltage (Note 10)
Output LOW Voltage (Note 10)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
V
V
V
V
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560
OL
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
−1485
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 11)
V
EE
+ 2.0
0.0
V
EE
+ 2.0
0.0
V
EE
+ 2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with V
.
CC
10.All loading with 50 W to V − 2.0 V.
CC
11. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
4
MC10EP08, MC100EP08
Table 8. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 12)
CC
EE
−40°C
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
20
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
28
36
20
38
20
40
V
V
V
V
V
Output HIGH Voltage (Note 13)
Output LOW Voltage (Note 13)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
2155 2280 2405 2155 2280 2405 2155 2280 2405
1355 1480 1605 1355 1480 1605 1355 1480 1605
OH
OL
2075
1355
2.0
2420 2075
1675 1355
2420 2075
1675 1355
2420
1675
3.3
IH
IL
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 14)
3.3
2.0
3.3
2.0
IHCMR
I
I
Input HIGH Current
put LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
13.All loading with 50 W to V − 2.0 V.
CC
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 9. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 15)
CC
EE
−40°C
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
20
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
28
36
20
38
20
40
V
V
V
V
V
Output HIGH Voltage (Note 16)
Output LOW Voltage (Note 16)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
3855 3980 4105 3855 3980 4105 3855 3980 4105
3055 3180 3305 3055 3180 3305 3055 3180 3305
OH
OL
3775
3055
2.0
4120 3775
3375 3055
4120 3775
3375 3055
4120
3375
5.0
IH
IL
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 17)
5.0
2.0
5.0
2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
16.All loading with 50 W to V − 2.0 V.
CC
17.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
5
MC10EP08, MC100EP08
Table 10. 100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 18)
CC
EE
−40°C
25°C
Typ
30
85°C
Typ
32
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
20
28
36
20
38
20
40
V
V
V
V
V
Output HIGH Voltage (Note 19)
Output LOW Voltage (Note 19)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
−1625
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 20)
V
EE
+ 2.0
0.0
V
EE
+ 2.0
0.0
V
EE
+ 2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 W to V − 2.0 V.
CC
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 21)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 3
85°C
Typ
> 3
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
GHz
ps
f
Maximum Frequency (Figure 2)
> 3
max
t
t
,
Propagation Delay to
Output Differential
PLH
PHL
D, D to Q, Q 170
150
220
0.2
280
< 1
180
250
0.2
300
< 1
200
270
0.2
320
< 1
t
Cycle−to−Cycle Jitter (Figure 2)
ps
JITTER
V
PP
Input Voltage Swing
(Differential Configuration)
800
1200
150
80
800
1200
150
100
800
1200
mV
t
r
t
f
Output Rise/Fall Times
Q, Q
70
120
170
130
180
150
200
ps
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
http://onsemi.com
6
MC10EP08, MC100EP08
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
1
(JITTER)
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Z = 50 W
Q
Q
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
D
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
http://onsemi.com
7
MC10EP08, MC100EP08
ORDERING INFORMATION
Device
†
Package
Shipping
MC10EP08DG
SOIC−8
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
(Pb−Free)
MC10EP08DR2G
MC10EP08DTG
MC10EP08DTR2G
SOIC−8
(Pb−Free)
TSSOP−8
(Pb−Free)
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
1000 / Tape & Reel
98 Units / Rail
MC10EP08MNR4G
(Contact sales office for availability)
DFN8
(Pb−Free)
MC100EP08DG
SOIC−8
(Pb−Free)
MC100EP08DR2G
MC100EP08DTG
MC100EP08DTR2G
SOIC−8
2500 / Tape & Reel
100 Units / Rail
(Pb−Free)
TSSOP−8
(Pb−Free)
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
1000 / Tape & Reel
MC100EP08MNR4G
(Contact sales office for availability)
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1642/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
8
MC10EP08, MC100EP08
PACKAGE DIMENSIONS
DFN8
CASE 506AA
ISSUE E
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
DETAIL A
REFERENCE
E
OPTIONAL
CONSTRUCTIONS
MILLIMETERS
2X
0.10
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
2.00 BSC
EXPOSED Cu
MOLD CMPD
2X
0.10
C
TOP VIEW
0.30
D
D2
E
1.10
2.00 BSC
1.30
A
C
DETAIL B
0.10
0.08
C
C
DETAIL B
E2
e
K
L
0.70
0.90
OPTIONAL
0.50 BSC
0.30 REF
0.25 0.35
−−− 0.10
CONSTRUCTION
L1
(A3)
A1
NOTE 4
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
SIDE VIEW
8X
0.50
DETAIL A
1.30
D2
8X
L
PACKAGE
OUTLINE
4
5
1
E2
0.90
2.30
8
K
1
8X b
e/2
e
8X
0.30
0.10 C A B
0.50
PITCH
NOTE 3
C
0.05
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC10EP08, MC100EP08
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
10
MC10EP08, MC100EP08
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
1.10
0.15
0.70
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
0.031
0.002
0.016
C
0.10 (0.004)
−W−
SEATING
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
PLANE
0.25
0.40
0.010
0.016
4.90 BSC
_
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC10EP08/D
相关型号：
©2020 ICPDF网 联系我们和版权申明