MC100EP140 [ONSEMI]
3.3VECL Phase-Frequency Detector; 3.3V ？ ECL相位频率检测
| 型号： | MC100EP140 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3VECL Phase-Frequency Detector |
| 文件： | 总8页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP140
3.3VĄECL Phase-Frequency
Detector
The MC100EP140 is a three state phase frequency–detector intended for
phase–locked loop applications which require a minimum amount of phase
and frequency difference at lock. Since the part is designed with fully
differential internal gates, the noise is reduced throughout the circuit,
especially at high speeds. The basic operation of a Phase/Frequency
Detector (PFD) is to “compare” an incoming signal (feedback) to a set
reference signal. When the Reference (R) and Feedback (FB) inputs are
unequal in frequency and/or phase, the differential UP (U) and DOWN
(D) outputs will provide pulse streams which, when subtracted and
integrated, provide an error voltage for control of a VCO. Detector
states of operation are shown in the Figure 2 and the State Table.
The device is packaged in a small outline, surface mount 8–lead
SOIC package. The typical output amplitude of the EP140 is 400 mV,
allowing faster switching time and greater bandwidth. For proper
operation, the input edge rate of the R and FB inputs should be less
than 5 ns.
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MARKING
DIAGRAM
8
SO–8
D SUFFIX
CASE 751
KP140
ALYW
8
1
1
KP= MC100EP
A
L
= Assembly Location
= Wafer Lot
More information on Phase Lock Loop operation and application can
be found in AND8040.
The pinout is shown in Figure 1, the logic diagram in Figure 3, and
the typical termination in Figure 5.
Y
= Year
W = Work Week
• 500 ps Typical Propagation Delay
• Maximum Frequency > 2.1 GHz Typical
• Fully Differential Internally
• Advanced High Band Output Swing of 400 mV
ORDERING INFORMATION
• Transfer Gain: 1.0 mV/Degree at 1.4 GHz
Device
Package
Shipping
1.2 mV/Degree at 1.0 GHz
MC100EP140D
SO–8
98 Units/Rail
• Rise and Fall Time: 100 ps Typical
• The 100 Series Contains Temperature Compensation
MC100EP140DR2
SO–8
2500 Units/Reel
• PECL Mode Operating Range: V = 3.0 V to 3.6 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = –3.0 V to –3.6 V
EE
• Open Input Default State
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
September, 2002 – Rev. 5
MC100EP140/D
MC100EP140
PIN DESCRIPTION
V
CC
R
FB
V
EE
PIN
FUNCTION
8
7
6
5
D, D
Differential Down Outputs
U, U
R*
Differential Up Outputs
ECL Reference Input
FB*
ECL Feedback Input
Positive Supply
V
CC
V
EE
Negative Supply
1
2
3
4
*
Pins will default LOW when left open.
U
U
D
D
Figure 1. 8–Lead Pinout (Top View)
STATE TABLE
PHASE
DETECTOR
STATE
INPUT
OUTPUT
R
R
R
FB
U
D
PUMP DOWN
2–1–2
2
L
L
L
H
L
L
L
L
L
L
H
L
1
2
3
R
FB
Pump
Down
Pump
Up
2–1
U = L
D = H
U = L
D = L
U = H
D = L
1–2
2
H
L
L
L
PUMP UP
2–3–2
FB
FB
2
2–3
3–2
2
L
H
H
L
L
L
L
H
L
L
L
L
L
Figure 2. Phase Detector Logic Model
H
L
L
U
C
A
U
A
R
U
A
C
D
S
R
U
FF
A
Reset
C
B
Reset
Reset
D
V
EE
R
S
D
FF
Reset
B
B
FB
D
D
B
D
D
Figure 3. Logic Diagram
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2
MC100EP140
ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL–94 V–0 @ 0.125 in
457 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Units
V
V
V
6
V
V
CC
EE
I
EE
V
V
= 0 V
–6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V ꢀ V
6
–6
V
V
I
CC
EE
V ꢁ V
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
TA
Operating Temperature Range
Storage Temperature Range
–40 to +85
°C
°C
T
stg
–65 to +150
θ
Thermal Resistance (Junction–to–Ambient) 0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JA
θ
Thermal Resistance (Junction–to–Case)
Wave Solder
std bd
8 SOIC
41 to 44
265
°C/W
°C
JC
T
<2 to 3 sec @ 248°C
sol
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
–40°C
Typ
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Max
85
Min
60
Typ
74
Max
90
Min
Typ
78
Max
93
Unit
mA
mV
mV
mV
mV
µA
I
EE
55
70
63
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2155
1755
2075
1355
2280
1880
2405
2005
2420
1675
150
2155
1755
2075
1355
2280
1880
2405
2005
2420
1675
150
2155
1755
2075
1355
2280
1880
2405
2005
2420
1675
150
OH
OL
IH
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Input HIGH Current
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to –0.3 V.
CC
EE
4. All loading with 50 W to V –2.0 volts.
CC
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3
MC100EP140
100EP DC CHARACTERISTICS, NECL V = 0 V, V = –3.6 V to –3.0 V (Note 5)
CC
EE
–40°C
Typ
70
25°C
Typ
74
85°C
Typ
78
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
µA
I
EE
55
85
60
90
63
93
V
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895
–1545 –1420 –1295 –1545 –1420 –1295 –1545 –1420 –1295
OH
OL
IH
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Input HIGH Current
–1225
–1945
–880 –1225
–1625 –1945
150
–880 –1225
–1625 –1945
150
–880
–1625
150
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with V
.
CC
6. All loading with 50 W to V –2.0 volts.
CC
AC CHARACTERISTICS V = 0 V; V = –3.0 V to –3.6 V or
V
CC
= 3.0 V to 3.6 V; V = 0 V (Note 7)
CC
EE
EE
–40°C
Typ
25°C
85°C
Typ
> 2
Symbol
Characteristic
Min
Max
Min
Typ
Max
Min
Max
Unit
f
Maximum Frequency
(See Figure 4 F /JITTER)
> 2
> 2
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
R to U, FB to D 300
FB to U, R to D 400
450
600
6002
800
325
450
475
650
625
850
350
500
500
700
650
900
ps
ps
PLH
PHL
t
Cycle–to–Cycle Jitter
.2
< 1
.2
< 1
.2
< 1
JITTER
(See Figure 4 F
/JITTER)
max
V
Input Voltage Swing
400
800
90
1200
180
400
60
800
100
1200
200
400
70
800
120
1200
220
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(20% – 80%)
Q, Q
50
7. Measured using a 750 mV V pk–pk, 50% duty cycle, clock source. All loading with 50 W to V –2.0 V.
PP
CC
600
6
5
500
400
300
200
100
0
4
3
2
(JITTER)
1200
1
0
400
800
1600
2000
2400
FREQUENCY (MHz)
Figure 4. Fmax/Jitter
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4
MC100EP140
Q
Q
D
D
Receiver
Device
Driver
Device
50
TT
50
W
W
V
TT
V
V
=
– 2.0 V
CC
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
AND8040
ECLinPS Circuit Performance at Non–Standard VIH Levels
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire–OR Ties in ECLinPS Designs
The ECL Translator Guide
–
–
–
–
–
–
–
–
–
–
–
–
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
Phase Lock Loop Operation
For an updated list of Application Notes, please see our website at http://onsemi.com.
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5
MC100EP140
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–X–
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDAARD IS 751-07
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
M
J
H
D
K
M
N
S
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
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6
MC100EP140
Notes
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7
MC100EP140
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MC100EP140/D
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