MC100EP16TD [ONSEMI]
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination; 3.3V / 5V ECL差分接收器/驱动器,内部端接型号: | MC100EP16TD |
厂家: | ONSEMI |
描述: | 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination |
文件: | 总8页 (文件大小:79K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC10EP16T, MC100EP16T
3.3V / 5VĄECL Differential
Receiver/Driver with
Internal Termination
The EP16T is a world–class differential receiver/driver. The device
is functionally equivalent to the EP16 with internal termination
resistors. A 50 W resistor is connected from the D input to the VT pin
and from the D input to the VT pin. Tie the VT and VT pins to VTT
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MARKING DIAGRAMS*
supply (V – 2 V) for parallel termination or connect VT and VT
CC
pins for 100 W input series termination.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
The 100 Series contains temperature compensation.
8
1
8
8
HEP61
ALYW
KEP61
ALYW
1
SO–8
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
D SUFFIX
CASE 751
1
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
8
1
8
1
with V = 0 V
EE
8
1
• NECL Mode Operating Range: V = 0 V
HP61
ALYW
KP61
ALYW
CC
TSSOP–8
DT SUFFIX
CASE 948R
with V = –3.0 V to –5.5 V
EE
• Internal 50 W Termination Resistors
L = Wafer Lot
Y = Year
H = MC10
K = MC100
W = Work Week
A = Assembly Location
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP16TD
SO–8
98 Units/Rail
MC10EP16TDR2
MC100EP16TD
MC100EP16TDR2
MC10EP16TDT
SO–8
SO–8
2500 Tape & Reel
98 Units/Rail
SO–8
2500 Tape & Reel
100 Units/Rail
TSSOP–8
MC10EP16TDTR2 TSSOP–8 2500 Tape & Reel
MC100EP16TDT TSSOP–8 100 Units/Rail
MC100EP16TDTR2 TSSOP–8 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
September, 2002 – Rev. 3
MC10EP16T/D
MC10EP16T, MC100EP16T
VT
D
1
2
8
7
V
CC
50 W
PIN DESCRIPTION
Q
Q
PIN
FUNCTION
D, D
Q, Q
ECL Data Inputs
ECL Data Outputs
V
CC
V
EE
Positive Supply
D
3
4
6
5
Negative Supply
VT
VT
50 W Termination Resistor to D
50 W Termination Resistor to D
50 W
VT
V
EE
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
UL–94 V–0 @ 0.125 in
167
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Units
V
V
V
6
V
V
CC
EE
I
EE
V
V
= 0 V
–6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V ꢀ V
6
–6
V
V
I
CC
EE
V ꢁ V
I
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 0.5
mA
°C
BB
TA
Operating Temperature Range
Storage Temperature Range
–40 to +85
–65 to +150
T
°C
stg
θ
Thermal Resistance (Junction–to–Ambient) 0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JA
θ
θ
Thermal Resistance (Junction–to–Case)
std bd
8 SOIC
41 to 44
°C/W
JC
JA
Thermal Resistance (Junction–to–Ambient) 0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θ
Thermal Resistance (Junction–to–Case)
Wave Solder
std bd
8 TSSOP
41 to 44
265
°C/W
°C
JC
T
<2 to 3 sec @ 248°C
sol
2. Maximum Ratings are those values beyond which device damage may occur.
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2
MC10EP16T, MC100EP16T
10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
31
Min
16
Max
31
Min
16
Max
31
Unit
mA
mV
mV
mV
mV
V
I
EE
16
23
23
23
V
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2165
1365
2090
1365
2.0
2290
1490
2415
1615
2415
1690
3.3
2230
1430
2155
1430
2.0
2355
1555
2480
1680
2480
1755
3.3
2290
1490
2215
1490
2.0
2415
1615
2540
1740
2540
1815
3.3
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
µA
µA
Input LOW Current
–150
–150
–150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
4. All loading with 50 W to V –2.0 volts.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
31
Min
16
Max
31
Min
16
Max
31
Unit
mA
mV
mV
mV
mV
V
I
EE
16
23
23
23
V
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
3865
3065
3790
3065
2.0
3990
3190
4115
3315
4115
3390
5.0
3930
3130
3855
3130
2.0
4055
3255
4180
3380
4180
3455
5.0
3990
3190
3915
3190
2.0
4115
3315
4240
3440
4240
3515
5.0
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
µA
µA
Input LOW Current
–150
–150
–150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
7. All loading with 50 W to V –2.0 volts.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 9)
CC
EE
–40°C
Typ
23
25°C
Typ
23
85°C
Typ
23
Symbol
Characteristic
Power Supply Current
Min
16
Max
Min
Max
Min
Max
31
Unit
mA
mV
mV
mV
mV
V
I
EE
31
16
31
16
V
V
V
V
V
Output HIGH Voltage (Note 10)
Output LOW Voltage (Note 10)
–1135 –1010 –885 –1070 –945
–820 –1010 –885
–760
OH
OL
–1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
–1210
–1935
–885 –1145
–1610 –1870
–820 –1085
–1545 –1810
–760
–1485
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
µA
µA
Input LOW Current
–150
–150
–150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V
.
CC
10.All loading with 50 W to V –2.0 volts.
CC
11. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC10EP16T, MC100EP16T
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 12)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
35
Min
20
Max
37
Min
22
Max
39
Unit
mA
mV
mV
mV
mV
V
I
EE
18
25
27
29
V
V
V
V
V
Output HIGH Voltage (Note 13)
Output LOW Voltage (Note 13)
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
µA
µA
Input LOW Current
–150
–150
–150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12.Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
13.All loading with 50 W to V –2.0 volts.
CC
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 15)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
35
Min
20
Max
37
Min
22
Max
39
Unit
mA
mV
mV
mV
mV
V
I
EE
18
25
27
29
V
V
V
V
V
Output HIGH Voltage (Note 16)
Output LOW Voltage (Note 16)
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
µA
µA
Input LOW Current
–150
–150
–150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15.Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
16.All loading with 50 W to V –2.0 volts.
CC
17.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 18)
CC
EE
–40°C
Typ
25
25°C
Typ
27
85°C
Typ
29
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
18
35
20
37
22
39
V
V
V
V
V
Output HIGH Voltage (Note 19)
Output LOW Voltage (Note 19)
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895
–1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
–1225
–1945
–880 –1225
–1625 –1945
–880 –1225
–1625 –1945
–880
–1625
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
µA
µA
Input LOW Current
–150
–150
–150
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 W to V –2.0 volts.
CC
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP16T, MC100EP16T
AC CHARACTERISTICS V = 0 V; V = –3.0 V to –5.5 V or
V = 3.0 V to 5.5 V; V = 0 V (Note 21)
CC EE
CC
EE
–40°C
25°C
85°C
Typ
> 3
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
f
Maximum Frequency
(See Figure 2 F /JITTER)
> 3
> 3
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
150
230
300
150
240
300
200
275
350
ps
PLH
PHL
t
t
Duty Cycle Skew (Note 22)
Cycle–to–Cycle Jitter
5.0
0.2
20
5.0
0.2
20
5.0
0.2
20
ps
ps
SKEW
< 1
< 1
< 1
JITTER
(See Figure 2 F
/JITTER)
max
V
Input Voltage Swing (Differential)
150
70
800
120
1200
170
150
80
800
130
1200
180
150
100
800
140
1200
200
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(20% – 80%)
Q, Q
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V –2.0 V.
CC
22.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
(JITTER)
1
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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5
MC10EP16T, MC100EP16T
Q
Q
D
D
Receiver
Device
Driver
Device
50
TT
50
W
W
V
TT
V
V
=
– 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
ECLinPS Circuit Performance at Non–Standard VIH Levels
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire–OR Ties in ECLinPS Designs
The ECL Translator Guide
–
–
–
–
–
–
–
–
–
–
–
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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6
MC10EP16T, MC100EP16T
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–X–
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDAARD IS 751-07
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
M
J
H
D
K
M
N
S
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
–U–
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.15 (0.006) T U
A
–V–
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
–W–
SEATING
PLANE
D
–T–
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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7
MC10EP16T, MC100EP16T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
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PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
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MC10EP16T/D
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