MC100EP16VCMNR4G [ONSEMI]
3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output; 3.3V / 5V ECL差分接收器/驱动器,具有高增益和输出使能型号: | MC100EP16VCMNR4G |
厂家: | ONSEMI |
描述: | 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output |
文件: | 总11页 (文件大小:156K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC100EP16VC
3.3Vꢀ/ꢀ5VꢁECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
http://onsemi.com
MARKING DIAGRAMS*
The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
8
KEP66
ALYW
G
SOIC−8
D SUFFIX
CASE 751
8
1
1
1
EN goes HIGH, it will force the Q LOW and the Q HIGH on the
HG
HG
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
8
1
TSSOP−8
DT SUFFIX
CASE 948R
KP66
8
and Q remains LOW and Q remains HIGH. The next positive
HG
HG
ALYWG
transition of the data input is not passed on to the data outputs under
these conditions. The Q and Q outputs remain in their disabled
G
HG
HG
state as long as the EN input is held HIGH. The EN input has no
influence on the Q output and the data input is passed on (inverted) to
this output whether EN is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
DFN8
MN SUFFIX
CASE 506AA
1
4
The V /D pin is internally dedicated and available for differential
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
BB
interconnect. V /D may rebias AC coupled inputs. When used,
BB
decouple V /D and V via a 0.01 mF capacitor and limit current
BB
CC
sourcing or sinking to 1.5 mA. When not used, V /D should be left
BB
open.
The 100 Series contains temperature compensation.
(Note: Microdot may be in either location)
Features
*For additional marking information, refer to
Application Note AND8002/D.
• 310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
• Gain > 200
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
• Q Output Will Default LOW with D Inputs Open or at V
HG
EE
• V Output
BB
• Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 5
MC10EP16VC/D
MC100EP16VC
Table 1. PIN DESCRIPTION
Q
D
1
2
8
7
V
CC
Pin
Function
D*
Q
ECL Data Input
ECL Data Output
Q
Q
HG
HG
Q
, Q
/D
ECL High Gain Data Outputs
ECL Enable Input
HG
HG
EN*
V
V
V
Reference Voltage Output / ECL Data Input
Positive Supply
BB
3
4
6
5
CC
EE
V
BB
/D
Negative Supply
OE
Q
LEN
EP
Exposed pad must be connected to a sufficient
thermal conduit. Electrically connect to the most
negative supply or leave floating open.
V
BB
LATCH
V
EE
EN
D
*Pins will default LOW when left open.
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Value
75 kW
N/A
Internal Input Pullup Resistor
ESD Protection
Human Body Model
> 4 kV
> 200 V
> 2 kV
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
2
MC100EP16VC
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
6
EE
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
I
CC
V w V
CC
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 1.5
mA
°C
BB
T
Operating Temperature Range
−40 to +85
−65 to +150
A
T
Storage Temperature Range
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JA
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
8 SOIC
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
8 TSSOP
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
40
85°C
Typ
42
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
52
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
25
36
45
30
50
32
V
V
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2125 2250
1305 1400
2075
2375 2125 2250 2375 2125 2250
1555 1305 1400 1555 1305 1400
2375
1555
2420
1675
1960
3.3
OH
OL
2420 2075
1675 1355
2420 2075
1675 1355
IH
1355
IL
1730 1845
2.0
1960 1730 1845 1960 1730 1845
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 4)
3.3
2.0
3.3
2.0
IHCMR
I
I
Input HIGH Current
150
150
150
mA
mA
IH
Input LOW Current
D
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
3
MC100EP16VC
Table 5. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
40
85°C
Typ
42
Symbol
Characteristic
Power Supply Current
Min
25
Typ
Max
Min
Max
Min
Max
Unit
I
EE
36
45
30
50
32
52
mA
V
V
V
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3825 3950 4075 3825 3950 4075 3825 3950 4075
3005 3100 3255 3005 3100 3255 3005 3100 3255
mV
mV
mV
mV
mV
V
OH
OL
3775
3055
4120 3775
3375 3055
4120 3775
3375 3055
4120
3375
IH
IL
3430 3545 3660 3430 3545 3660 3430 3545 3660
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 7)
2.0
5.0
2.0
5.0
2.0
5.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
D
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 6. 100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
Typ
36
25°C
Typ
40
85°C
Typ
42
Symbol
Characteristic
Power Supply Current
Min
Max
45
Min
Max
Min
Max
Unit
I
EE
25
30
50
32
52
mA
V
V
V
V
V
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1175 −1050 −925 −1175 −1050 −925 −1175 −1050 −925
−1995 −1900 −1745 −1995 −1900 −1745 −1995 −1900 −1745
mV
mV
mV
mV
mV
V
OH
OL
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
IH
−1625
IL
−1570 −1455 −1340 −1570 −1455 −1340 −1570 −1455 −1340
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
EE
+ 2.0
0.0
V
EE
+ 2.0
0.0
V + 2.0
EE
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
4
MC100EP16VC
Table 7. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 11)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 3
85°C
Typ
> 3
Symbol
Characteristic
Maximum Frequency (Figure 2)
Propagation Delay (Differential) Q
Min
Max
Min
Max
Min
Max
Unit
GHz
ps
f
> 3
max
t
t
,
200
250
250
300
280
360
330
410
350
450
400
500
250
300
300
350
310
380
360
430
400
500
450
550
275
325
325
375
340
430
390
480
425
525
475
575
PLH
PHL
(Differential) QHG, QHG
(Single−Ended) Q
(Single−Ended) QHG, QHG
t
t
Setup Time
Hold Time
EN = L to D
EN =H to D
50
15
60
50
5
50
18
10
ps
ps
S
100
100
40
100
EN = L to D
EN =H to D
100
50
50
15
100
50
40
20
100
50
5
20
H
t
t
Duty Cycle Skew (Note 12)
5.0
0.2
20
5.0
0.2
20
5.0
0.2
20
ps
ps
SKEW
RMS Random Clock Jitter (Figure 2)
< 1
< 1
< 1
JITTER
V
PP
Input Voltage Swing
(Differential Configuration)
HG
Q
25
150
800
800
1200
1200
25
150
800
800
1200
1200
25
150
800
800
1200
1200
mV
t
r
t
f
Output Rise/Fall Times
Q
200
70
300
130
400
220
250
80
350
150
450
240
250
100
350
170
500
270
ps
(20% − 80%)
QHG, QHG
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
12.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
1
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter for QHG, QHG Output
http://onsemi.com
5
MC100EP16VC
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
1
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter for Q Output
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
1
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 4. Fmax/Jitter for QHG, QHG Output
http://onsemi.com
6
MC100EP16VC
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
1
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 5. Fmax/Jitter for Q Output
Z = 50 W
Q
Q
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
D
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
http://onsemi.com
7
MC100EP16VC
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EP16VCD
MC100EP16VCDG
SOIC−8
98 Units / Rail
98 Units / Rail
SOIC−8
(Pb−Free)
MC100EP16VCDR2
MC100EP16VCDR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100EP16VCDT
MC100EP16VCDTG
TSSOP−8
100 Units / Rail
100 Units / Rail
TSSOP−8
(Pb−Free)
MC100EP16VCDTR2
MC100EP16VCDTR2G
TSSOP−8
2500 / Rail
2500 / Rail
TSSOP−8
(Pb−Free)
MC100EP16VCMNR4
MC100EP16VCMNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
8
MC100EP16VC
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC100EP16VC
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
http://onsemi.com
10
MC100EP16VC
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
0.05
8 X b
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC100EP16VC/D
相关型号:
©2020 ICPDF网 联系我们和版权申明