MC100EP16VTD [ONSEMI]
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing and Internal Input Termination; 3.3V / 5V ECL差分接收器/驱动器，带有可变输出摆幅和内部输入终端
| 型号： | MC100EP16VTD |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing and Internal Input Termination |
| 文件： | 总12页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP16VT
3.3V / 5VꢀECL Differential
Receiver/Driver with
Variable Output Swing and
Internal Input Termination
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MARKING DIAGRAMS*
Description
The MC100EP16VT is a differential receiver functionally equivalent
to the 100EP16 with input pins controlling the amplitude of the outputs
(pin 1) and providing an internal termination network (pin 4).
8
The V
input pin controls the output amplitude of the EP16VT
CTRL
8
KEP63
ALYW
G
and is referenced to V . (See Figure 4.) The operational range of the
CC
1
V
CTRL
input is from ꢀ V (a supply at V −1.42 V, maximum
BB CC
output amplitude) to V (minimum output amplitude). V is an
externally supplied voltage equal to V −1.42 V (See Figures 2
and Figure 3). A variable resistor between V and V , with the
SOIC−8
D SUFFIX
CASE 751
CC
BB
1
CC
CC
BB
wiper driving V
application circuits and a V
, can control the output amplitude. Typical
CTRL
Voltage vs. Output Amplitude graph
CTRL
8
1
8
are described in this data sheet. When left open, the V
pin will be
CTRL
1
internally pulled down to V and operate as a standard EP16, with
KP63
EE
ALYWG
100% output amplitude.
TSSOP−8
DT SUFFIX
CASE 948R
G
The V input pin offers an internal termination network for a 50 W
TT
line impedance environment, shown in Figure 1. For further reference,
see Application Note AND8020, Termination of ECL Logic Devices.
Input considerations are required for D and D under no signal conditions
to prevent instability.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
1
4
DFN8
MN SUFFIX
CASE 506AA
Features
• 220 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical (See Graph)
• The 100 Series Contains Temperature Compensation
A
L
= Assembly Location
= Wafer Lot
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
Y
W
M
G
= Year
= Work Week
= Date Code
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
= Pb−Free Package
with V = −3.0 V to −5.5 V
EE
(Note: Microdot may be in either location)
• Open Input Default State
• 50 W Internal Termination Resistor
• Pb−Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 3
MC100EP16VT/D
MC100EP16VT
Table 1. PIN DESCRIPTION
V
1
2
8
7
V
CC
CTRL
PIN
FUNCTION
D, D
Q, Q
ECL Data Inputs
ECL Data Outputs
Output Swing Control
Termination Supply
Positive Supply
D
Q
Q
50 W
V
V
V
V
*
CTRL
TT
D
3
4
6
5
50 W
CC
Negative Supply
EE
V
TT
V
EE
EP
Exposed pad must be
connected to a sufficient ther-
mal conduit. Electrically connect
to the most negative supply or
leave floating open.
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
*
Pin will default LOW when left open.
Table 2. ATTRIBUTES
Characteristics
Value
Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
75 kW
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
140 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EP16VT
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
6
EE
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
−6
V
V
EE
I
CC
V ꢁ V
CC
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
8 SOIC
41 to 44
°C/W
JC
JA
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
8 TSSOP
41 to 44 ± 5%
°C/W
JC
JA
DFN8
DFN8
129
84
°C/W
°C/W
500 lfpm
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
Typ
36
25°C
Typ
38
85°C
Typ
40
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Max Swing)
Min
30
Max
Min
Max
Min
Max
48
Unit
mA
mV
I
EE
42
31
44
32
V
OH
2155
2405 2155
2405 2155
2405
(Note 3)
V
ꢁ V
ꢁ V
ꢀ V
CC
CTRL
EE
V
OL
Output LOW Voltage (Max Swing)
(Note 3)
mV
V
1355
1490 1605 1355
1520 1605 1355
1520 1605
CTRL
BB
BB
V
ꢁ V
> V
See
See
See
CC
CTRL
Fig.2
Fig.2
Fig.2
V
= V (Min Swing) 2105
2230 2355 2095
2420 2075
2220 2345 2065
2420 2075
2190 2315
2420
CTRL
CC
V
V
V
V
D, D Input HIGH Voltage (Single−Ended)
D, D Input LOW Voltage (Single−Ended)
2075
1355
mV
mV
mV
V
IH
1675 1355
1675 1355
1675
IL
Input Voltage (V
)
V
V
V
V
V
V
CC
CTRL
IHCMR
CTRL
EE
CC
EE
CC
EE
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 4)
2.0
2.9
2.0
2.9
2.0
2.9
I
I
Input HIGH Current
Input LOW Current
(V Open)
150
150
150
mA
mA
IH
TT
(V Open) −150
TT
−150
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V. V does not change with V
. V changes with V
. V
CTRL
is referenced to V
.
CC
OH
CTRL
OL
CTRL
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC100EP16VT
Table 5. DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
38
85°C
Typ
40
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 6)
Min
30
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
I
EE
36
42
31
44
32
48
V
OH
3855
3980 4105 3855
3980 4105 3855
3980 4105
V
CC
> V
> V
CTRL
EE
V
OL
Output LOW Voltage (Max Swing)
(Note 6)
mV
V
ꢀ V
3055
3190 3305 3055
3220 3305 3055
3220 3305
CTRL
BB
VCC ꢁ V
> V
See
See
See
CTRL
BB
Fig.2
Fig.2
Fig.2
V
= V (Min Swing) 3805
3930 4055 3795
4120 3775
3920 4045 3765
4120 3775
3890 4015
4120
CTRL
CC
V
V
V
V
D, D Input HIGH Voltage (Single−Ended)
D, D Input LOW Voltage (Single−Ended)
3775
3055
mV
mV
mV
V
IH
3375 3055
3375 3055
3375
IL
Input Voltage (V
)
V
V
V
V
V
V
CC
CTRL
IHCMR
CTRL
EE
CC
EE
CC
EE
Input HIGH Voltage Common Mode
2.0
4.6
2.0
4.6
2.0
4.6
Range (Differential Configuration) (Note 7)
I
I
Input HIGH Current
Input LOW Current
(V Open)
150
150
150
mA
mA
IH
TT
(V Open) −150
TT
−150
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V. V does not change with V
. V changes with V
. V
CTRL
is referenced to V
.
CC
OH
CTRL
OL
CTRL
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC100EP16VT
Table 6. DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
25°C
Typ
38
85°C
Typ
40
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 9)
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
I
EE
30
36
42
31
44
32
48
V
OH
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
V
CC
> V > V
CTRL EE
V
OL
Output LOW Voltage (Max Swing)
(Note 9) ꢀ V
mV
V
−1945 −1810 −1695 −1945 −1780 −1695 −1945 −1780 −1695
CTRL
BB
BB
VCC ꢁ V
> V
See
See
See
CTRL
Fig.2
Fig.2
Fig.2
V
CTRL
= V (Min Swing) −1195 −1070 −945 −1205 −1080 −955 −1235 −1110 −985
CC
V
V
V
V
D, D Input HIGH Voltage (Single−Ended)
D, D Input LOW Voltage (Single−Ended)
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
mV
IH
−1625 mV
IL
Input Voltage (V
)
V
EE
V
CC
V
EE
V
CC
V
EE
V
CC
mV
V
CTRL
IHCMR
CTRL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
EE
+2.0
−0.4
V
EE
+2.0
−0.4
V +2.0
EE
−0.4
I
I
Input HIGH Current
Input LOW Current
(V Open)
150
150
150
mA
mA
IH
TT
(V Open) −150
TT
−150
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V. V does not change with V
. V changes with V
IHCMR
. V
is referenced to V
.
CC
OH
CTRL
OL
CTRL
CTRL
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
input signal.
Table 7. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 11)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 4
85°C
Typ
> 4
Symbol
Characteristic
Min
Max
Min
Max
Min
Max Unit
f
Maximum Toggle Frequency
> 4
GHz
max
(See Figure 8. F /JITTER)
max
t
t
,
Propagation Delay to Output Differential
ps
350
300
PLH
PHL
Max Swing
Min Swing
250
200
300
250
350
300
250
200
300
250
350
300
250
200
300
250
t
t
Duty Cycle Skew (Note 12)
5.0
0.2
20
5.0
0.2
20
5.0
0.2
20
ps
ps
SKEW
Cycle−to−Cycle Jitter
< 1
< 1
< 1
JITTER
(See Figure 8. F
/JITTER)
max
V
Input Voltage Swing
(Differential Configuration) (Note 13)
150
800
1200
150
800
1200
150
800
1200
mV
ps
PP
t , t
r
Output Rise/Fall Times
Max Swing Q
Min Swing
70
30
120
80
170
130
80
20
130
70
180
120
100
20
150
70
200
120
f
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
12.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
13.V (min) is minimum input swing for which AC parameters are guaranteed.
PP
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5
MC100EP16VT
100
90
80
70
60
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
1.42
V
BB
VOLTS (V)
Figure 2. VCC − VCTRL (pin #1)
VOH
Min Swing
Max Swing
VOL
1.42
0.0
0.5
1.0
1.5
2.0
V
BB
VOLTS (V)
Figure 3. VCC − VCTRL
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6
MC100EP16VT
V
CTRL
+
1
2
8
7
V
V
CC
CTRL
D
Q*
Q*
50 W
D
3
4
6
50 W
V
TT
5
V
EE
Figure 4. Voltage Source Implementation, VCTRL Pin 1
V
CC
1
2
8
7
V
V
CC
CTRL
V
BB
D
Q*
Q*
50 W
D
3
4
6
5
50 W
V
EE
V
TT
V
EE
Figure 5. Alternative Implementations, VCTRL Pin 1
V
CTRL
+
1
2
8
7
V
V
CC
CTRL
D
Q*
Q*
50 W
D
3
4
6
5
50 W
V
CC
−2 V
V
EE
V
TT
Figure 6. Standard Termination Method, VTT Pin 4
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7
MC100EP16VT
V
CTRL
+
1
2
8
7
V
V
CC
CTRL
D
Q*
Q*
50 W
D
3
4
6
5
50 W
V
EE
V
CC
R
T
V
TT
R
T
5.0 V
3.3 V
112 W
46 W
V
EE
Figure 7. Alternate “Y” Termination Method, VTT Pin 4
1000
10
9
900
800
700
600
500
400
300
200
100
0
2.00 V Below V
CC
8
7
1.25 V Below V
1.00 V Below V
CC
6
5
4
3
CC
0.75 V Below V
CC
2
1
0.25 V Below V
500
CC
(JITTER)
2500 3000
0
1000
1500
2000
3500
4000
FREQUENCY (MHz)
Figure 8. Fmax/Jitter
Z = 50 W
o
Q
D
Receiver
Device
Driver
Device
Q
Z = 50 W
o
D
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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8
MC100EP16VT
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EP16VTD
MC100EP16VTDG
SOIC−8
98 Units / Rail
98 Units / Rail
SOIC−8
(Pb−Free)
MC100EP16VTDR2
MC100EP16VTDR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100EP16VTDT
MC100EP16VTDTG
TSSOP−8
100 Units / Rail
100 Units / Rail
TSSOP−8
(Pb−Free)
MC100EP16VTDTR2
MC100EP16VTDTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EP16VTMNR4
MC100EP16VTMNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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MC100EP16VT
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC100EP16VT
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
http://onsemi.com
11
MC100EP16VT
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
0.05
8 X b
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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