MC100EP446FAG [ONSEMI]
3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter; 3.3 V / 5 V 8位CMOS / ECL / TTL数据输入并行/串行转换器
| 型号： | MC100EP446FAG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter |
| 文件： | 总20页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP446, MC100EP446
3.3 V/5 V 8-Bit
CMOS/ECL/TTL Data Input
Parallel/Serial Converter
Description
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The MC10/100EP446 is an integrated 8−bit parallel to serial data
converter. The device is designed with unique circuit topology to
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence
from parallel data into a serial data stream is from bit D0 to D7. The
parallel input pins D0−D7 are configurable to be threshold controlled by
CMOS, ECL, or TTL level signals. The serial data rate output can be
selected at internal clock data rate or twice the internal clock data rate
using the CKSEL pin.
Control pins are provided to reset (SYNC) and disable internal clock
circuitry (CKEN). In either CKSEL modes, the internal flip−flops are
triggered on the rising edge for CLK and the multiplexers are switched
on the falling edge of CLK, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
MARKING DIAGRAMS*
MCxxx
EP446
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
Additionally, V pin is provided for single−ended input condition.
BB
The 100 Series devices contain temperature compensation network.
1
MCxxx
EP446
Features
32
1
AWLYYWWG
• 3.2 Gb/s Typical Data Rate Capability
• Differential Clock and Serial Outputs
QFN32
MN SUFFIX
CASE 488AM
G
• V Output for Single-ended Input Applications
BB
• Asynchronous Data Reset (SYNC)
• PECL Mode Operating Range:
xxx
A
= 10 or 100
= Assembly Location
V
= 3.0 V to 5.5 V with V = 0 V
EE
WL, L = Wafer Lot
YY, Y = Year
CC
• NECL Mode Operating Range:
= 0 V with V = −3.0 V to −5.5 V
WW, W = Work Week
V
CC
EE
G or G = Pb−Free Package
• Open Input Default State
• Safety Clamp on Inputs
• Parallel Interface Can Support PECL, TTL or CMOS
• Pb−Free Packages are Available*
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 9
MC10EP446/D
MC10EP446, MC100EP446
24
23
22
21
20
19
18
17
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
V
CC
16
15
V
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
EE
V
V
EE
CC
V
PCLK
PCLK
PCLK
PCLK
CF
V
CF
14
13
12
11
10
9
V
V
V
V
EF
EF
MC10EP446
MC100EP446
V
V
EE
SYNC
SYNC
CC
EE
CC
Exposed Pad (EP)
SYNC
S
S
OUT
OUT
SYNC
S
S
OUT
OUT
V
V
V
V
BB2
CC
BB2
CC
V
V
CC
CC
V
V
CC
CC
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
Figure 1. LQFP−32 Pinout (Top View)
Figure 2. QFN−32 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0*−D7*
, S
ECL, CMOS, or TTL Parallel Data Input
ECL Differential Serial Data Output
ECL Differential Clock Input
S
OUT OUT
CLK*, CLK*
PCLK, PCLK
SYNC*, SYNC**
CKSEL*
ECL Differential Parallel Clock Output
ECL Conversion Synchronizing Differential Input (Reset)***
ECL Clock Input Selector
CKEN*, CKEN*
ECL Clock Enable Differential Input
ECL, CMOS, or TTL Input Selector
ECL Reference Mode Connection
Reference Voltage Output
V
V
V
V
V
CF
EF
, V
BB1 BB2
Positive Supply
CC
EE
Negative Supply
* Pins will default LOW when left open.
**Pins will default HIGH when left open.
***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK
initiates the conversion process synchronously on the next rising edge of CLK.
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2
MC10EP446, MC100EP446
Table 2. TRUTH TABLE
Function
HIGH
LOW
Pin
CKSEL
S
: PCLK = 8:1
S
: PCLK = 8:1
OUT
OUT
CLK: S
= 1:2
CLK: S
= 1:1
OUT
OUT
CLK
CLK
S
S
OUT
OUT
CKEN
SYNC
Synchronously Disables Normal Parallel to Serial
Conversion
Synchronously Enables Normal Parallel to Serial Conversion
Asynchronously Resets Internal Flip−Flops*
Synchronous Enable
*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates
the conversion process synchronously on the next rising edge of CLK.
Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE
Table 4. DATA INPUT OPERATING VOLTAGE TABLE
Input Function
ECL Mode
Connect To V Pin
Data Inputs (D [0:7])
Power Supply
CF
V
Pin
CMOS
TTL
PECL
NECL
N/A
p
(V ,V
CC EE
)
EF
CMOS Mode
TTL Mode*
No Connect
PECL
NECL
p
p
p
1.5 V $ 100 mV
N/A
N/A
N/A
*For TTL Mode, if no external voltage can be provided, the reference
voltage can be provided by connecting the appropriate resistor
Power Supply
3.3 V
Resistor Value 10% (Tolerance)
between V and V pins.
CF
EE
1.5 kW
500 W
5.0 V
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3
MC10EP446, MC100EP446
D0
D4
D2
D
C
Q
Q
Q
Q
Q
Q
Q
Q
R
R
R
R
R
R
R
R
MUX
2:1
D
C
Q
R
D
C
MUX
2:1
D
C
Q
R
D
C
MUX
2:1
D
C
Q
R
D
C
D6
D1
S
S
OUT
OUT
MUX
2:1
D
C
MUX
2:1
D
C
Q
R
D
C
D5
D3
D7
MUX
2:1
D
C
Q
R
D
C
MUX
2:1
D
C
Q
R
D
C
÷2
÷2
÷2
PCLK
PCLK
Control
Logic
MUX
2:1
CKEN
CKEN
D
C
Q
CLK
CLK
R
CKSEL
SYNC
SYNC
V
CC
V
V
V
EE
BB
CF
V
EF
Figure 3. Logic Diagram
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4
MC10EP446, MC100EP446
Table 5. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
LQFP−32
QFN−32
Level 2
Level 2
Level 1
−
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
962 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
V
V
6
CC
EE
I
EE
CC
= 0 V
−6
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ≤ V
6
−6
V
EE
CC
I
I
CC
EE
V ≥ V
I
I
Output Current
Continuous
Surge
50
mA
out
100
V
Sink/Source
BB
0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
2S2P
Pb <2 to 3 sec @ 248°C
LQFP−32
12 to 17
°C/W
°C/W
JC
QFN−32
QFN−32
31
27
JA
q
JC
Thermal Resistance (Junction−to−Case)
QFN−32
12
°C/W
°C
T
sol
Wave Solder
265
265
Pb−Free <2 to 3 sec @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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5
MC10EP446, MC100EP446
Table 7. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
110
85°C
Typ
115
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
I
EE
90
110
140
90
140
95
145
mA
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
OH
OL
IH
mV
CMOS 2000
PECL 2090
TTL 2000
3300 2000
3300 2155
3300 2000
3300 2000
3300 2215
3300 2000
3300
3300
3300
V
Input LOW Voltage (Single−Ended)
IL
mV
CMOS
PECL 1365
TTL
0
800
1690 1460
800
0
800
1755 1490
800
0
800
1815
800
0
0
0
V
V
Output Voltage Reference
1790 1840 1990 1855 1905 2055 1915 1965 2115 mV
BB
Input HIGH Voltage Common Mode Range (Dif-
ferential Configuration) (Note 4)
2.0
3.3
150
0.5
2.0
3.3
150
0.5
2.0
3.3
150
0.5
V
IHCMR
I
I
Input HIGH Current
mA
mA
IH
Input LOW Current
(All Except SYNC, SYNC)
0.5
0.5
0.5
IL
SYNC, SYNC −150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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6
MC10EP446, MC100EP446
Table 8. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
110
85°C
Typ
115
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
I
EE
90
110
140
90
140
95
145
mA
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
3865 3950 4115 3930 4055 4180 3990 4115 4240 mV
3065 3190 3315 3130 3255 3380 3190 3315 3440 mV
OH
OL
IH
mV
CMOS 3500
PECL 3790
TTL 2000
5000 3500
5000 3855
5000 2000
5000 3500
5000 3915
5000 2000
5000
5000
5000
V
Input LOW Voltage (Single−Ended)
IL
mV
CMOS
PECL 3065
TTL
0
1500
3390 3130
800
0
1500
3455 3190
800
0
1500
3915
800
0
0
0
V
V
Output Voltage Reference
3490 3540 3690 3555 3605 3755 3615 3665 3815 mV
BB
Input HIGH Voltage Common Mode Range (Dif-
ferential Configuration) (Note 7)
2.0
5.0
150
0.5
2.0
5.0
150
0.5
2.0
5.0
150
0.5
V
IHCMR
I
I
Input HIGH Current
mA
mA
IH
Input LOW Current
(All Except SYNC, SYNC)
0.5
0.5
0.5
IL
SYNC, SYNC −150
−150
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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7
MC10EP446, MC100EP446
Table 9. 10EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
25°C
Typ
110
85°C
Typ
115
Min
90
Typ
Max
Min
Max
Min
Max
145
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
EE
110
140
90
140
95
V
V
V
V
V
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
OH
OL
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
mV
IH
−1485 mV
IL
−1510 −1460 −1310 −1445 −1395 −1245 −1385 −1335 −1185 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
0.0
V
IHCMR
EE
EE
I
I
Input HIGH Current
150
150
150
mA
mA
IH
Input LOW Current
IL
(All Except SYNC, SYNC)
0.5
0.5
0.5
SYNC, SYNC −150
0.5
−150
0.5
−150
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 10. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 11)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Min
90
Max
Min
90
Max
130
Min
95
Max
135
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
I
EE
110
130
2405
1605
110
115
V
V
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
2155
1355
2280
1480
2155
1355
2280
1480
2405
1605
2155
1355
2280
1480
2405
1605
OH
OL
IH
Input HIGH Voltage (Single−Ended)
mV
CMOS
PECL
TTL
2000
2075
2000
3300
3300
3300
2000
2075
2000
3300
3300
3300
2000
2075
2000
3300
3300
3300
V
Input LOW Voltage (Single−Ended)
IL
mV
CMOS
PECL
TTL
0
1355
0
800
1675
800
0
1355
0
800
1675
800
0
1355
0
800
1675
800
V
V
Output Voltage Reference
1775
2.0
1875
1975
3.3
1775
2.0
1875
1975
3.3
1775
2.0
1875
1975
3.3
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
12.All loading with 50 W to V − 2.0 V.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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8
MC10EP446, MC100EP446
Table 11. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 14)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Min
90
Max
Min
90
Max
130
Min
95
Max
135
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
I
EE
110
130
4105
3305
110
115
V
V
V
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
3855
3055
3980
3180
3855
3055
3980
3180
4105
3305
3855
3055
3980
3180
4105
3305
OH
OL
IH
Input HIGH Voltage (Single−Ended)
mV
CMOS
PECL
TTL
3500
3775
2000
5000
5000
5000
3500
3775
2000
5000
5000
5000
3500
3775
2000
5000
5000
5000
V
Input LOW Voltage (Single−Ended)
IL
mV
CMOS
PECL
TTL
0
3055
0
1500
3375
800
0
3055
0
1500
3375
800
0
3055
0
1500
3375
800
V
V
Output Voltage Reference
3475
2.0
3575
3675
5.0
3475
2.0
3575
3675
5.0
3475
2.0
3575
3675
5.0
mV
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
15.All loading with 50 W to V − 2.0 V.
CC
16.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 12. 100EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 17)
CC
EE
−40°C
Typ
25°C
Typ
110
85°C
Typ
115
Min
Max
130
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
EE
90
110
90
130
95
135
V
V
V
V
V
V
Output HIGH Voltage (Note 18)
Output LOW Voltage (Note 18)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
OH
OL
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
mV
IH
−1625 mV
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
0.0
V
IHCMR
EE
EE
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
.
CC
18.All loading with 50 W to V − 2.0 V.
CC
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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9
MC10EP446, MC100EP446
Table 13. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 20)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Maximum Frequency
(Figure 15)
Unit
f
max
GHz
CKSEL High
CKSEL Low
3.2
1.6
3.4
1.7
3.2
1.6
3.4
1.7
3.2
1.6
3.4
1.7
t
t
,
Propagation Delay to Output Differential
PLH
PHL
ps
ps
CKSEL = 0
CLK TO S
,
650
700
750
800
850
900
700
750
800
850
900
950
725
775
850
900
975
1025
OUT
CLK TO PCLK
CKSEL = 1
CLK TO S
,
775
850
875
950
975
1050
825
900
925
1000
1025
1100
875
950
1000
1075
1125
1200
OUT
CLK TO PCLK
t
t
t
t
Setup Time
D to CLK+
SYNC− to CLK−
CKEN+ to CLK−
S
ps
ps
ps
(Figure 4) −375
−425
140
40
−400
200
70
−450
140
40
−450
200
70
−500
140
40
(Figure 5)
(Figure 6)
200
70
Hold Time
D to CLK+
SYNC− to CLK−
CLK− to CKEN−
h
(Figure 4) −525
−575
−550
0
75
−600
−600
0
75
−650
0
(Figure 6)
75
45
45
45
Minimum Pulse Width (Note 22)
Data (D0−D7)
SYNC
pw
150
200
145
150
200
145
150
200
145
CKEN
Random Clock Jitter (RMS)
0.2
800
100
< 1
1200
150
0.2
800
120
< 1
1200
170
0.2
800
140
< 1
1200
190
ps
mV
ps
JITTER
v f
Typ
max
V
Input Differential Voltage Swing
(Note 21)
150
50
150
70
150
90
PP
t
r
t
f
Output Rise/Fall Times
S
OUT
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
21.V (min) is the minimum input swing for which AC parameters are guaranteed.
PP
22.The minimum pulse width is valid only if the setup and hold times are respected.
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10
MC10EP446, MC100EP446
CLK
Data
Valid
Data
Setup Time
t
s
t
h
+ 0 −
Figure 4. Setup and Hold Time for Data
SYNC
SYNC
CLK
t
s
CLK
CLK
CKEN
t
S
t
h
Figure 5. Setup Time for SYNC
Figure 6. Setup and Hold Time for CKEN
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11
MC10EP446, MC100EP446
APPLICATION INFORMATION
The MC10/100EP446 is an integrated 8:1 parallel to serial
Note: all pins requiring ECL voltage inputs must have a
50 W terminating resistor to V (V = V – 2.0 V).
The CKSEL input (Pin 2) is provided to enable the user to
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched ¬
converter. An attribute for EP446 is that the parallel inputs
D0–D7 (Pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
TT
TT
CC
interconnects between V (Pin 27) and V (Pin 26) pins.
EF
CF
For CMOS input levels, leave V and V open. For ECL
EF
CF
operation, short V and V (Pins 26 and 27). For TTL
to when the data is seen on the S
is on the falling edge
CF
EF
OUT
th
operation, connect a 1.5 V supply reference to V and leave
of the 7 clock cycle plus internal propagation delay
(Figure 7). Note the PCLK switches on the falling edge of
CLK.
CF
the V pin open. The 1.5 V reference voltage to V pin can
EF
CF
be accomplished by placing a 1.5 kW or 500 W between V
CF
and V for 3.3 V or 5.0 V power supplies, respectively.
EE
Number of Clock Cycles from Data Latch to SOUT
À
1
2
3
4
5
6
7
CLK
D0
D0−1
D0−2
D1−2
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D1
D2
D3
D4
D5
D6
D7
Data Latched
Data Latched
Data Latched
Data Latched
Á
SOUT
CKSEL
PCLK
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
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12
MC10EP446, MC100EP446
Similarly, for CKSEL HIGH operation, the time from when the parallel data is latched ¬ to when the data is seen on the
th
S
is on the rising edge of the 14 clock cycle plus internal propagation delay (Figure 8). Furthermore, the PCLK switches
OUT
on the rising edge of CLK.
Number of Clock Cycles from Data Latch to SOUT
À
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
D0
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D0−2
D1−2
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
D1
D2
D3
D4
D5
D6
D7
Data Latched
Data Latched
Data Latched
Á
SOUT
CKSEL
PCLK
Figure 8. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH
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13
MC10EP446, MC100EP446
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and
clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial
data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion
process on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch the
parallel input data after the a falling edge of SYNC ¬, followed by the falling edge CLK , on the next rising of edge of CLK
® for CKSEL LOW
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
1
2
3
4
5
6
7
SYNC
(Asynchronous RESET)
Á
À
CLK
Â
SYNC
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D0−2
D1−2
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4
D0
D1
D2
D3
D4
D5
D6
D7
Data Latched
Data Latched
Data Latched
Data Latched
SOUT
CKSEL
PCLK
Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
SYNC
À
Á
Â
CLK
Figure 10. Synchronous Release of SYNC for CKSEL LOW
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14
MC10EP446, MC100EP446
For CKSEL HIGH, as shown in the timing diagrams below, the device will start to latch the parallel input data after the falling
edge of SYNC ¬, followed by the falling edge CLK , on the second rising edge of CLK ® (Figures 11 and 12).
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SYNC
(Asynchronous RESET)
Á Â
À
CLK
SYNC
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D0−2
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4
D0
D1−2
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
D1
D2
D3
D4
D5
D6
D7
Data Latched
Data Latched
Data Latched
SOUT
CKSEL
PCLK
Figure 11. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH and SYNC
SYNC
À
Á
Â
CLK
Figure 12. Synchronous Release of SYNC for CKSEL HIGH
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15
MC10EP446, MC100EP446
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 13).
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
SOUT
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
PCLK
CKSEL
Figure 13. Timing Diagram with CKEN with CKSEL HIGH
The differential PCLK output (Pins 14 and 15) is a word
framer and can help the user synchronize the serial data
conditions, the unused differential input is connected to V
BB
as a switching reference voltage. V may also rebias AC
BB
output, S
(Pins 11 and 12), in their applications.
coupled inputs. When used, decouple V and V via a
OUT
BB CC
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 14).
0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V should be left open. Also, both
BB
An internally generated voltage supply, the V pin, is
outputs of the differential pair must be terminated (50 W to
BB
available to this device only. For single–ended input
V
) even if only one output is used.
TT
CLK
CLK
RESET
SYNC
Pattern Generator
Data Format Logic
(FPGA, ASIC)
EP446
S
SERIAL DATA
OUT
TRIGGER
PCLK
Figure 14. PCLK as Trigger Application
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16
MC10EP446, MC100EP446
800
700
600
500
400
300
200
100
0
CKSEL High
CKSEL Low
0
500
1000
1500
2000
2500
3000
3500
INPUT CLOCK FREQUENCY (MHz)
Figure 15. Typical VOUTPP versus Input Clock Frequency, 255C
Figure 16. SOUT System Jitter Measurement
(Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on SOUT
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17
MC10EP446, MC100EP446
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
MC10EP446FA
Package
Shipping
LQFP−32
250 Units / Tray
250 Units / Tray
MC10EP446FAG
LQFP−32
(Pb−Free)
MC10EP446FAR2
MC10EP446FAR2G
LQFP−32
2000 / Tape & Reel
2000 / Tape & Reel
LQFP−32
(Pb−Free)
MC100EP446FA
LQFP−32
250 Units / Tray
250 Units / Tray
MC100EP446FAG
LQFP−32
(Pb−Free)
MC100EP446FAR2
MC100EP446FAR2G
LQFP−32
2000 / Tape & Reel
2000 / Tape & Reel
LQFP−32
(Pb−Free)
MC10EP446MNG
QFN−32
74 Units / Rail
74 Units / Rail
(Pb−Free)
MC100EP446MNG
MC10EP446MNR4G
MC100EP446MNR4G
QFN−32
(Pb−Free)
QFN−32
(Pb−Free)
1000 / Tape & Reel
1000 / Tape & Reel
QFN−32
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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18
MC10EP446, MC100EP446
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
AE
AE
−U−
−T−
P
B
V
B1
DETAIL Y
BASE
METAL
DETAIL Y
V1
17
8
N
9
4X
−Z−
0.20 (0.008) AC T−U
Z
9
F
D
S1
S
_
8X M
J
R
DETAIL AD
G
SECTION AE−AE
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
X
DETAIL AD
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
0.138 BSC
0.276 BSC
0.138 BSC
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT
INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.250
(0.010) PER SIDE. DIMENSIONS A AND
B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE
−AB−.
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.450
0.150
0.200
0.750
0.002
0.004
0.018
0.006
0.008
0.030
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5_
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER
MAY VARY FROM DEPICTION.
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19
MC10EP446, MC100EP446
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
L
EXPOSED PAD
32 X
SOLDERING FOOTPRINT*
K
9
16
32 X
17
5.30
8
3.20
E2
32 X
0.63
1
24
25
32
32 X
b
e
3.20 5.30
0.10
0.05
C
A
B
C
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC10EP446/D
相关型号：
MC100EP451FA
100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32, LQFP-32
ROCHESTER
MC100EP451FAG
100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32, LEAD FREE, LQFP-32
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MC100EP451FAR2
100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32, LQFP-32
ROCHESTER
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