MC100EPT23DT [ONSEMI]
Dual Differential LVPECL to LVTTL Translator; 双差分LVPECL到LVTTL翻译
| 型号： | MC100EPT23DT |
| 厂家： | 
ONSEMI |
| 描述： | Dual Differential LVPECL to LVTTL Translator |
| 文件： | 总8页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EPT23
3.3VꢀDual Differential
LVPECL/LVDS to LVTTL
Translator
The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL
translator. Because LVPECL (Positive ECL) or LVDS levels are used,
only +3.3 V and ground are required. The small outline 8-lead package
and the dual gate design of the EPT23 makes it ideal for applications
which require the translation of a clock and a data signal.
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MARKING
DIAGRAMS*
The EPT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external V reference, the EPT23 does
8
BB
not require both ECL standard versions. The LVPECL/LVDS inputs
are differential. Therefore, the MC100EPT23 can accept any standard
KPT23
ALYW
SOIC−8
D SUFFIX
CASE 751
8
differential LVPECL/LVDS input referenced from a V of +3.3 V.
CC
1
1
1
• 1.5 ns Typical Propagation Delay
• Maximum Operating Frequency > 275 MHz
• 24 mA LVTTL Outputs
8
TSSOP−8
DT SUFFIX
CASE 948R
KA23
ALYW
8
• Operating Range: V = 3.0 V to 3.6 V with GND = 0 V
CC
1
• Pb−Free Packages are Available
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
February, 2005 − Rev. 11
MC100EPT23/D
MC100EPT23
Table 1. PIN DESCRIPTION
D0
D0
1
2
8
7
V
CC
Pin
Function
LVTTL Outputs
Q0, Q1
D0**, D1**
D0**, D1**
Differential LVPECL Inputs
Q0
Q1
LVPECL LVTTL
V
CC
Positive Supply
Ground
GND
D1
D1
3
4
6
5
** Pins will default to V /2 when left open.
CC
GND
(Top View)
Figure 1. 8−Lead Pinout and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
50 kW
50 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
UL 94 V−0 @ 0.125 in
91 Devices
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
GND = 0 V
Condition 2
Rating
Unit
V
V
CC
V
I
Power Supply
Input Voltage
Output Current
3.8
3.8
GND = 0 V
V ꢀ V
V
I
CC
I
Continuous
Surge
50
mA
mA
out
100
T
Operating Temperature Range
−40 to +85
°C
°C
A
T
Storage Temperature Range
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
500 lfpm
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
0 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
500 lfpm
q
Thermal Resistance (Junction−to−Case)
Wave Solder
Standard Board
TSSOP−8
41 to 44
265
°C/W
°C
JC
T
sol
< 2 to 3 sec @ 248°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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2
MC100EPT23
Table 4. PECL DC CHARACTERISTICS V = 3.3 V, GND = 0 V (Note 2)
CC
−40°C
25°C
Typ
18
85°C
Typ
18
Min
10
Typ
18
Max
25
Min
10
Max
25
Min
10
Max
25
Symbol
CCH
Characteristic
Power Supply Current (Outputs set to HIGH)
Power Supply Current (Outputs set to LOW)
Input HIGH Voltage
Unit
mA
mA
mV
mV
V
I
I
15
26
36
15
26
36
15
26
36
CCL
V
V
V
2075
1355
1.2
2420 2075
1675 1355
2420 2075
1675 1355
2420
1675
3.3
IH
Input LOW Voltage
IL
Input HIGH Voltage Common Mode Range
(Note 3)
3.3
1.2
3.3
1.2
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
0.5
mA
mA
IH
D
D
−150
−150
−150
−150
−150
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. All values vary 1:1 with V
.
CC
3. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 5. TTL DC CHARACTERISTICS V = 3.3 V, GND = 0.0 V, T = −40°C to 85°C
CC
A
Symbol
Characteristic
Output HIGH Voltage
Condition
Min
Typ
Max
Unit
V
V
I
I
= −3.0 mA
2.4
OH
OL
OH
V
Output LOW Voltage
= 24 mA
0.5
V
OL
I
Output Short Circuit Current
−180
−50
mA
OS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0.0 V (Note 4)
CC
−40°C
Typ
25°C
Typ
350
85°C
Typ
350
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
MHz
ns
f
Maximum Frequency (Figure 2)
275
350
275
275
max
t
t
,
Propagation Delay to
Output Differential (Note 5)
1.2
1.2
1.5
1.5
1.8
1.8
1.2
1.1
1.5
1.5
1.8
1.8
1.3
1.1
1.7
1.5
2.4
1.8
PLH
PHL
t
t
t
Output−to−Output Skew++
Output−to−Output Skew−−
Part−to−Part Skew (Note 6)
15
35
70
60
80
500
15
40
70
70
80
500
30
40
140
125
80
500
ps
SK+ +
SK− −
SKPP
t
Random Clock Jitter (RMS) (Figure 2)
5
10
5
10
5
10
ps
JITTER
V
Input Voltage Swing (Differential Configuration)
150
330
800 1200 150
600 900 330
800 1200 150
600 900 330
800 1200 mV
650 900 ps
PP
t t
r
Output Rise/Fall Times (0.8 V − 2.0 V)
Q, Q
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with a 750 mV 50% duty−cycle clock source. R = 500 W to GND and C = 20 pF to GND. Refer to Figure 3.
L
L
5. Reference (V = 3.3V ± 5%; GND = 0 V)
CC
6. Skews are measured between outputs under identical conditions.
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3
MC100EPT23
3.0
2.0
1.0
0.0
12
8
V
OL
ꢀ 0.5 V
V
OH
JITTER
4
0
400
0
100
200
FREQUENCY (MHz)
300
Figure 2. Typical VOH / Jitter versus Frequency (255C)
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
C *
L
R
L
*C includes
L
fixture
capacitance
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
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4
MC100EPT23
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EPT23D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EPT23DG
SOIC−8
(Pb−Free)
MC100EPT23DR2
MC100EPT23DR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100EPT23DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EPT23DTG
TSSOP−8
(Pb−Free)
MC100EPT23DTR2
MC100EPT23DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1642/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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5
MC100EPT23
PACKAGE DIMENSIONS
SOIC−8 NB
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
NOTES:
ISSUE AE
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC100EPT23
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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7
MC100EPT23
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your
local Sales Representative.
MC100EPT23/D
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