MC100LVEL12DG [ONSEMI]
3.3V ECL Low Impedance Driver; 3.3V ECL低阻抗驱动器
| 型号： | MC100LVEL12DG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V ECL Low Impedance Driver |
| 文件： | 总8页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EPT24
3.3VꢀLVTTL/LVCMOS to
Differential LVECL Translator
Description
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a −3.3 V, +3.3 V and ground are required. The small outline
8−lead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
http://onsemi.com
MARKING DIAGRAMS*
8
SOIC−8
D SUFFIX
CASE 751
KPT24
ALYW
G
8
Features
1
1
• 350 ps Typical Propagation Delay
• Maximum Input Clock Frequency > 1.0 GHz Typical
• The 100 Series Contains Temperature Compensation
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
• Operating Range: V = 3.0 V to 3.6 V;
CC
8
KA24
V
EE
= −3.6 V to −3.0 V; GND = 0 V
ALYWG
G
• PNP LVTTL Input for Minimal Loading
• Q Output will Default HIGH with Input Open
• Pb−Free Packages are Available
DFN8
MN SUFFIX
CASE 506AA
1
4
A
L
= Assembly Location
= Wafer Lot
Y
W
M
G
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 8
MC100EPT24/D
MC100EPT24
Table 1. PIN DESCRIPTION
V
1
2
8
7
V
CC
EE
PIN
Q, Q
D
FUNCTION
Differential LVECL Outputs
LVTTL Input
LVTTL
D
Q
V
Positive Supply
CC
LVECL
GND
Ground
NC
NC
3
4
6
5
Q
V
Negative Supply
No Connect
EE
NC
EP
Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
GND
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
181 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
2
MC100EPT24
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
GND = 0 V
Condition 2
= −3.3V
Rating
3.8
Unit
V
V
CC
V
EE
V
IN
Positive Power Supply
Negative Power Supply
Input Voltage
V
V
EE
GND = 0 V
= 3.3V
−3.8
V
CC
GND = 0 V
V v V
0 to V
V
I
CC
CC
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
−40 to +85
−65 to +150
°C
°C
A
T
Storage Temperature Range
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
TSSOP−8
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. LVTTL INPUT DC CHARACTERISTICS V = 3.3 V, V = −3.6 V to −3.0 V, GND = 0.0 V; T = −40°C to 85°C
CC
EE
A
Symbol
Characteristic
Input HIGH Current
Condition
Min
Typ
Max
20
Unit
mA
mA
mA
V
I
I
I
V
V
V
= 2.7 V
IH
IN
Input HIGH Current HIGH Voltage
Input LOW Current
= V = 3.8 V
100
−0.6
−1.0
IHH
IL
CC
IN
= 0.5 V
IN
V
IK
V
IH
V
IL
Input Clamp Voltage
Input HIGH Voltage
I
IN
= −18 mA
2.0
V
Input LOW Voltage
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. NECL OUTPUT DC CHARACTERISTICS V = 3.3 V, V = −3.3 V, GND = 0.0 V (Note 2)
CC
EE
−40°C
Typ
25°C
85°C
Min
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
mV
mV
mA
mA
V
OH
V
OL
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Positive Power Supply Current
Negative Power Supply Current
-1145 −1020 -895
-1145 −1020 -895
-1145 −1030 -895
-1945 −1820 -1695 -1945 −1820 -1695 -1945 −1820 -1695
I
2.0
30
4.0
38
2.0
30
4.0
38
2.0
30
4.0
38
CC
EE
I
20
20
20
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Output levels will vary 1:1 with GND. V can vary ± 0.3 V.
EE
3. Outputs are terminated through a 50 W resistor to GND − 2 V.
http://onsemi.com
3
MC100EPT24
Table 6. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 4)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 1
85°C
Typ
> 1
Min
300
70
Max
Min
300
80
Max
Min
300
100
Max
Symbol
Characteristic
Unit
f
Maximum Input Clock Frequency (Fig-
ure 2)
> 1
GHz
max
t
t
,
Propagation Delay to
Output Differential (Note 5)
500
800
530
800
560
800
ps
PLH
PHL
t
RMS Random Clock Jitter (Figure 2)
0.2
< 1
0.2
< 1
0.2
< 1
ps
ps
JITTER
t
r
t
f
Output Rise/Fall Times
Q, Q
125
170
130
180
150
200
(20% − 80%) @ 50 MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V.
5. Specifications for standard TTL input signal.
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
(JITTER)
700
1
100
300
500
900
1100
1300
INPUT CLOCK FREQUENCY (MHz)
Figure 2. Output Voltage Amplitude (VOUTpp)/RMS Jitter
vs. Input Clock Frequency at Ambient Temperature
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
http://onsemi.com
4
MC100EPT24
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EPT24D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EPT24DG
SOIC−8
(Pb−Free)
MC100EPT24DR2
MC100EPT24DR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100EPT24DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EPT24DTG
TSSOP−8
(Pb−Free)
MC100EPT24DTR2
MC100EPT24DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EPT24MNR4
MC100EPT24MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
5
MC100EPT24
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MC100EPT24
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
http://onsemi.com
7
MC100EPT24
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
0.05
8 X b
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC100EPT24/D
相关型号：
©2020 ICPDF网 联系我们和版权申明