MC100LVEP210 [ONSEMI]

Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver; 低压1 ： 5双Diff.LVECL / LVPECL / LVEPECL / HSTL时钟驱动器


型号：	MC100LVEP210
厂家：	ONSEMI
描述：	Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver 低压1 ： 5双Diff.LVECL / LVPECL / LVEPECL / HSTL时钟驱动器时钟驱动器
文件：	总8页 (文件大小：138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

The MC100LVEP210 is a low skew 1–to–5 dual differential driver,

designed with clock distribution in mind. The LVECL/LVPECL input

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signals can be either differential or single–ended if the V

output is

used. The signal is fanned out to 5 identical differential outputs. HSTL

inputs can be used when the EP210 is operating in LVPECL mode.

The LVEP210 specifically guarantees low output–to–output skew.

Optimal design, layout, and processing minimize skew within a device

and from lot to lot.

To ensure the tight skew specification is realized, both sides of the

differential output need to be terminated identically into 50Ω even if

only one side is being used. When fewer than all ten pairs are used,

identically terminate all the output pairs on the same package side

whether used or unused. If no outputs on a single side are used, then

leave these outputs open (unterminated). This will maintain minimum

output skew. Failure to do this will result in a 10–20ps loss of skew

margin (propagation delay) in the output(s) in use.

32–LEAD TQFP

FA SUFFIX

CASE 873A

MARKING DIAGRAM*

= Assembly Location

MC100

LVEP210

AWLYYWW

WL = Wafer Lot

YY = Year

WW = Work Week

The MC100LVEP210, as with most other LVECL devices, can be

operated from a positive V

supply in LVPECL mode. This allows

the LVEP210 to be used for high performance clock distribution in

+3.3V or +2.5V systems. Single ended input operation is limited to a

VCC ≥ 3.0V in PECL mode, or VEE ≤ –3.0V in ECL mode.

Designers can take advantage of the LVEP210’s performance to

distribute low skew clocks across the backplane or the board. In a

LVPECL environment, series or Thevenin line terminations are

typically used as they require no additional power supplies. For more

information on using PECL, designers should refer to Application

Note AN1406/D.

*For additional information, see Application Note

AND8002/D

ORDERING INFORMATION

Device

Package

Shipping

• 100ps Part–to–Part Skew

• 35ps Output–to–Output Skew

• Differential Design

MC100LVEP210FA

TQFP

250 Units/Tray

MC100LVEP210FAR2 TQFP

2000 Tape & Reel

• V Output

• 475ps Typical Propagation Delay

• High Bandwidth to 1.5GHz Typical

• LVPECL and HSTL mode: 2.375V to 3.8V V

with V = 0V

• LVECL mode: 0V V

with V = –2.375V to –3.8V

• Internal Input Resistors: Pulldown on D, D

• Pullup and Pulldown on CLK

• ESD Protection: >2KV HBM, >100V MM

• Moisture Sensitivity Level 2

For Additional Information, See Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”,

Oxygen Index 28 to 34

• Transistor Count = 461 devices

Semiconductor Components Industries, LLC, 1999

Publication Order Number:

March, 2000 – Rev. 2

MC100LVEP210/D

MC100LVEP210

Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1

24 23 22 21 20 19 18 17

VCC

Qa2

Qa1

Qa0

VCC

Qb2

PIN DESCRIPTION

FUNCTION

CLKn/CLKn

Qn0:4/Qn0:4

VBB

LVECL/LVPECL/HSTL CLK Inputs

LVECL/LVPECL Outputs

Reference Voltage Output

Positive Supply

Qb3

Qb4

VCC

MC100LVEP210

VCC

VEE

Negative, 0 Supply

VCC NC CLKa CLKa VBB CLKb CLKb VEE

Figure 1. 32–Lead TQFP Pinout (Top View)

Warning: All V

to Power Supply to guarantee proper operation.

and V

pins must be externally connected

Qa0

Qb0

Qa1

Qb1

CLKa

CLKb

Qa2

Qb2

Qa3

Qb3

Qa4

Qb4

Figure 2. Logic Symbol

MAXIMUM RATINGS*

Symbol

Parameter

Value

–6.0 to 0

6.0 to 0

–6.0 to 0

6.0 to 0

Unit

Power Supply (V

= 0V)

VDC

Input Voltage (V

Output Current

= 0V, V not more negative than V )

= 0V, V not more positive than V

)

Continuous

Surge

100

out

Sink/Source Current

± 0.5

°C

Operating Temperature Range

Storage Temperature

–40 to +85

–65 to +150

°C

stg

Thermal Resistance (Junction–to–Ambient)

Still Air

500lfpm

°C/W

Thermal Resistance (Junction–to–Case)

12 to 17

265

°C/W

°C

Solder Temperature (<2 to 3 Seconds: 245°C desired)

sol

* Maximum Ratings are those values beyond which damage to the device may occur.

Use for inputs of same package only.

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MC100LVEP210

DC CHARACTERISTICS, ECL/LVECL (V

= 0V; V

= –3.3(+0.925, –0.5)V) (Note 5.)

–40°C

Typ

25°C

Typ

85°C

Typ

Symbol

Characteristic

Power Supply Current

Min

Max

Min

Max

Min

Max

Unit

IEE

(Note 1.)

Output HIGH Voltage

(Note 2.)

–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895

–1995 –1820 –1650 –1995 –1820 –1650 –1995 –1820 –1650

Output LOW Voltage

(Note 2.)

Input HIGH Voltage

Single Ended

–1165

–1810

–880 –1165

–1625 –1810

–880 –1165

–1625 –1810

–880

Input LOW Voltage

Single Ended

–1625

Output Voltage Reference (Note 3.)

–1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325

Input HIGH Voltage Common Mode

Range (Note 4.)

V +1.2

0.0

V +1.2

0.0

V +1.2

0.0

IHCMR

Input HIGH Current

150

µA

Input LOW Current

CLK

0.5

–150

0.5

–150

0.5

–150

NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.

1. V

= 0V, V

= V

to V

, all other pins floating.

EEmin

EEmax

2. All loading with 50 ohms to V –2.0 volts.

3. Single ended input operation is limited V

4. V

IHCMR

5. Input and output parameters vary 1:1 with V

≤ –3.0V in ECL/LVECL mode.

min varies 1:1 with V , max varies 1:1 with V .

EE CC

DC CHARACTERISTICS, LVPECL (V

= 3.3V ± 0.5V, V

= 0V) (Note 10.)

–40°C

Typ

25°C

85°C

Typ

Symbol

Characteristic

Power Supply Current

Min

Max

Min

Typ

Max

Min

Max

Unit

IEE

(Note 6.)

Output HIGH Voltage

(Note 7.)

2155

1305

2135

1490

2280

1480

2405

1650

2420

1675

2155

1305

2135

1490

2280

1480

2405

1650

2420

1675

2155

1305

2135

1490

2280

1480

2405

1650

2420

1675

Output LOW Voltage

(Note 7.)

Input HIGH Voltage

Single Ended

Input LOW Voltage

Single Ended

Output Voltage Reference (Note 8.)

1775

1.2

1875

1975

3.3

1775

1.2

1875

1975

3.3

1775

1.2

1875

1975

3.3

Input HIGH Voltage Common Mode

Range (Note 9.)

IHCMR

Input HIGH Current

150

µA

Input LOW Current

CLK

0.5

–150

0.5

–150

0.5

–150

NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.

6. V

= 3.3V ± 0.5V, V

= 0V, all other pins floating.

7. All loading with 50 ohms to V –2.0 volts.

8. Single ended input operation is limited V

≥ –3.0V in PECL mode.

9. V

min varies 1:1 with V , max varies 1:1 with V .

IHCMR

EE CC

10.Input and output parameters vary 1:1 with V

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MC100LVEP210

DC CHARACTERISTICS, LVEPECL (V

= 2.5V ± 0.125V, V

= 0V) (Note 14.)

–40°C

Typ

25°C

Typ

85°C

Typ

Symbol

Characteristic

Power Supply Current

Min

Max

Min

Max

Min

Max

Unit

IEE

(Note 11.)

Output HIGH Voltage

(Note 12.)

1355

505

1335

690

1.2

1480

680

1605

850

1620

875

2.5

1355

505

1335

690

1.2

1480

680

1605

850

1620

875

2.5

1355

505

1335

690

1.2

1480

680

1605

850

1620

875

2.5

Output LOW Voltage

(Note 12.)

Input HIGH Voltage

Single Ended

Input LOW Voltage

Single Ended

Input HIGH Voltage Common Mode

Range (Note 13.)

IHCMR

Input HIGH Current

150

µA

Input LOW Current

CLK

0.5

–150

0.5

–150

0.5

–150

NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.

11. V

= 2.5V, V = 0V, all other pins floating.

12.All loading with 50 ohms to V

13.V

min varies 1:1 with V , max varies 1:1 with V .

IHCMR

EE CC

14.Input and output parameters vary 1:1 with V

DC CHARACTERISTICS, HSTL (V

= 2.5(–0.125, +1.3)V, V

= 0V)

–40°C

25°C

85°C

Symbol

Characteristic

Input HIGH Voltage

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

1200

Input LOW Voltage

400

900

Input Crossover Voltage

680

Power Supply Current (Note 15.)

= 2.375V to 3.8V, V = 0V, all other pins floating.

100

15.V

AC CHARACTERISTICS (V

= 0V; V

= –2.5V to –3.8V) or (V

= 2.5V to 3.8V; V

EE = 0V)

–40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Maximum Toggle Frequency

for LVECL and LVPECL

(Note 16.)

1.5

GHz

maxLVPECL

Maximum Toggle Frequency

for HSTL (Note 16.)

250

350

MHz

maxHSTL

Propagation Delay

Differential

200

300

400

200

450

300

500

750

PLH

PHL

Within Device Skew

Duty Cycle Skew (Note 17.)

TBD

100

TBD

SKEW

Cycle–to–Cycle Jitter

TBD

800

170

TBD

800

180

TBD

800

280

JITTER

Input Voltage Swing (Diff.)

150

100

1200

270

150

100

1200

290

150

100

1200

350

Output Rise/Fall Times

(20% – 80%)

16.F

max

guaranteed for functionality only.

17.Skewismeasuredbetweenoutputsunderidenticaltransitionsofsimilarpathsthroughadevice.Dutycycleskewisdefinedonlyfordifferential

operation when the delays are measured from the crosspoint of the inputs to the crosspoint of the outputs.

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MC100LVEP210

PACKAGE DIMENSIONS

TQFP

FA SUFFIX

32–LEAD PLASTIC PACKAGE

CASE 873A–02

ISSUE A

0.20 (0.008) AB T–U

–U–

–T–

DETAIL Y

–Z–

DETAIL Y

0.20 (0.008) AC T–U

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE

DETERMINED AT DATUM PLANE –AB–.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –AC–.

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION

IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

DETAIL AD

–AB–

–AC–

SEATING

PLANE

0.10 (0.004) AC

BASE

METAL

8. MINIMUM SOLDER PLATE THICKNESS SHALL

BE 0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

8X M

MILLIMETERS

DIM MIN MAX

7.000 BSC

INCHES

MIN MAX

0.276 BSC

0.138 BSC

0.276 BSC

0.138 BSC

3.500 BSC

7.000 BSC

3.500 BSC

1.400 1.600 0.055 0.063

0.300 0.450 0.012 0.018

1.350 1.450 0.053 0.057

0.300 0.400 0.012 0.016

SECTION AE–AE

0.800 BSC

0.031 BSC

0.050 0.150 0.002 0.006

0.090 0.200 0.004 0.008

0.500 0.700 0.020 0.028

12 REF

0.090 0.160 0.004 0.006

0.400 BSC 0.016 BSC

12 REF

DETAIL AD

0.150 0.250 0.006 0.010

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.354 BSC

0.177 BSC

0.354 BSC

0.177 BSC

0.008 REF

0.039 REF

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MC100LVEP210

Notes

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MC100LVEP210

Notes

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MC100LVEP210

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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

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EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

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*Available from Germany, France, Italy, England, Ireland

MC100LVEP210/D

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MC100LVEP210 [ONSEMI]

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