MC10162P [ONSEMI]
Binary to 1-8 Decoder (High); 二进制到1-8解码器（高）
| 型号： | MC10162P |
| 厂家： | 
ONSEMI |
| 描述： | Binary to 1-8 Decoder (High) |
| 文件： | 总4页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10162
Binary to 1-8 Decoder
(High)
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other
outputs are low. The enable inputs, when either or both are high, force
all outputs low.
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The MC10162 is a true parallel decoder. No series gating is used
internally, eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of
the two enable inputs is used as the data input, while the other is used
as a data enable input.
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10162L
AWLYYWW
A complete mux/demux operation on 16 bits for data distribution is
illustrated in Figure 1 of the MC10161 data sheet.
1
• P = 315 ns typ/pkg (No Load)
16
D
PDIP–16
P SUFFIX
CASE 648
• t = 4.0 ns typ
pd
MC10162P
AWLYYWW
• t , t = 2.0 ns typ (20%–80%)
r
f
1
LOGIC DIAGRAM
1
E0Ą2
E1Ą15
PLCC–20
FN SUFFIX
CASE 775
6ĄQ0
5ĄQ1
10162
AWLYYWW
4ĄQ2
3ĄQ3
13ĄQ4
AĄ7
BĄ9
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
12ĄQ5
DIP PIN ASSIGNMENT
11ĄQ6
10ĄQ7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
CC2
CĄ14
CC1
E0
E1
C
V
V
= PIN 1
= PIN 16
= PIN 8
CC1
Q3
Q2
Q1
Q0
A
CC2
V
EE
Q4
Q5
TRUTH TABLE
Q6
INPUTS
OUTPUTS
Q7
B
E0
E1
C
B
A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
V
EE
L
H
H
L
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
L
H
L
H
H
H
H
X
X
L
H
L
H
H
X
X
H
X
X
ORDERING INFORMATION
Device
Package
Shipping
MC10162L
CDIP–16
25 Units / Rail
MC10162P
PDIP–16
PLCC–20
25 Units / Rail
46 Units / Rail
MC10162FN
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
January, 2002 – Rev. 7
MC10162/D
MC10162
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Typ
Pin
Under
Test
–30°C
Max
84
+85°C
Min
Min
Max
76
Min
Max
84
Characteristic
Power Supply Drain Current
Input Current
Symbol
Unit
mAdc
µAdc
µAdc
Vdc
I
E
8
61
I
14
14
13
350
220
220
inH
I
inL
0.5
0.5
0.3
Output Voltage
Output Voltage
Logic 1
Logic 0
V
OH
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
V
OL
13
13
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
V
13
–1.080
–0.980
–0.910
Vdc
Vdc
OHA
V
13
13
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
OLA
Switching Times (50Ω Load)
ns
Propagation Delay
t
t
13
13
1.5
1.5
6.2
6.2
1.5
1.5
4.0
4.0
6.0
6.0
1.5
1.5
6.4
6.4
14+13–
14–13+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
13
13
1.0
1.0
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
13+
t
13–
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
V
IHmax
V
ILmin
V
V
V
EE
IHAmin
ILAmax
–30°C
+25°C
+85°C
–0.890
–0.810
–0.700
–1.890
–1.850
–1.825
–1.205
–1.105
–1.035
–1.500
–1.475
–1.440
–5.2
–5.2
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
)
CC
Characteristic
Power Supply Drain Current
Input Current
Symbol
V
V
ILmin
V
V
V
EE
Gnd
1,16
1,16
1,16
1,16
IHmax
IHAmin
ILAmax
I
E
8
8
8
8
8
I
14
14
13
14
inH
I
inL
14
Output Voltage
Output Voltage
Logic 1
V
OH
14
Logic 0
V
OL
13
13
2
15
8
8
1,16
1,16
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
V
13
14
8
1,16
OHA
V
13
13
2
15
8
8
1,16
1,16
OLA
Switching Times
(50Ω Load)
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t
t
13
13
14
14
13
13
8
8
1,16
1,16
14+13+
14–13–
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t+
13
13
14
14
13
13
8
8
1,16
1,16
t–
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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2
MC10162
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
M
S
S
0.007 (0.180)
T
L-M
N
B
Y BRK
–M–
–N–
M
S
S
N
0.007 (0.180)
T
L-M
U
D
D
–L–
Z
W
20
1
S
S
S
0.010 (0.250)
T
L-M
N
G1
X
V
A
VIEW D–D
M
M
S
S
S
S
0.007 (0.180)
0.007 (0.180)
T
L-M
L-M
N
N
M
S
S
N
0.007 (0.180)
T
L-M
H
Z
T
R
K1
K
C
E
M
S
S
N
0.007 (0.180)
T
L-M
F
0.004 (0.100)
VIEW S
G
–T– SEATING
PLANE
J
VIEW S
NOTES:
INCHES
MILLIMETERS
G1
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
S
S
S
0.010 (0.250)
T
L-M
N
A
B
C
E
F
0.385
0.385
0.165
0.090
0.013
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
---
0.032
---
---
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
---
2
0.81
---
---
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.356
0.356
0.048
0.048
0.056
0.020
10
2
_
_
_
_
G1 0.310
K1 0.040
0.330
---
7.88
1.02
8.38
---
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3
MC10162
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
DIM MIN MAX
MILLIMETERS
MIN
19.05
6.10
---
MAX
19.93
7.49
5.08
0.50
A
B
C
D
E
F
0.750
0.240
---
0.785
0.295
0.200
0.020
–T–
SEATING
PLANE
0.015
0.39
K
N
0.050 BSC
1.27 BSC
0.055
0.065
1.40
1.65
G
H
K
L
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J 16 PL
G
0.300 BSC
7.62 BSC
M
S
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
D 16 PL
_
_
_
M
S
T A
0.25 (0.010)
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
–A–
ISSUE R
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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MC10162/D
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