MC10E196FNR2G [ONSEMI]
5V ECL Programmable Delay Chip; 5V ECL可编程延迟芯片
| 型号： | MC10E196FNR2G |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL Programmable Delay Chip |
| 文件： | 总12页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E196, MC100E196
5VꢀECL Programmable
Delay Chip
Description
The MC10E/100E196 is a programmable delay chip (PDC)
designed primarily for very accurate differential ECL input edge
placement applications.
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The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays
1.25 and 1.5 times the basic gate delay of approximately 80 ps. These
two elements provide the E196 with a digitally-selectable resolution
of approximately 20 ps. The required device delay is selected by the
seven address inputs D[0:6], which are latched on chip by a high signal
on the latch enable (LEN) control.
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
The FTUNE input takes an analog voltage and applies it to an
internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)
minimum resolution still further. The FTUNE input is what
differentiates the E196 from the E195.
MCxxxE196FNG
AWLYYWW
An eighth latched input, D7, is provided for cascading multiple
PDC’s for increased programmable range. The cascade logic allows
full control of multiple PDC’s, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
*For additional marking information, refer to
Application Note AND8002/D.
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Features
• 2.0 ns Worst Case Delay Range
• ≈20 ps/Delay Step Resolution
• Linear Input for Tighter Resolution
• >1.0 GHz Bandwidth
• On Chip Cascade Circuitry
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 425 devices
• Pb−Free Packages are Available*
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 75 V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 9
MC10E196/D
MC10E196, MC100E196
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Table 1. PIN DESCRIPTION
PIN
D2
D3 D4 D5 D6 D7 NC
FUNCTION
25
24
23
22
21
20
19
IN/IN
ECL Signal Input
FTUNE
NC
D1
D0
26
27
18
17
EN
ECL Input Enable (H Forces Q Low)
ECL MUX Select Inputs
ECL Signal Output
D[0:7]
Q/Q
LEN
ECL Latch Enable
V
LEN 28
16
15
CC
SET MIN
SET MAX
CASCADE
FTUNE
ECL Min Delay Set
ECL Max Delay Set
ECL Cascade Signal
ECL Linear Voltage Input
Reference Voltage Output
Positive Supply
V
V
CCO
EE
1
2
3
4
MC10E196
MC100E196
IN
IN
Q
Q
V
14
13
12
V
V
V
BB
CC
EE
, V
CCO
Negative Supply
No Connect
V
BB
CCO
NC
5
6
7
8
9
10
11
Table 2. TRUTH TABLE
NC NC EN
EN
EN
L
H
L
Q = IN
Q Logic Low
* All V and V
pins are tied together on the die.
CCO
CC
LEN
Pass Through D[0:10]
Latch D[0:10]
Warning: All V , V
, and V pins must be externally
EE
CC CCO
connected to Power Supply to guarantee proper operation.
LEN
H
L
SETMIN
SETMIN
SETMAX
SETMAX
Normal Mode
Figure 1. Pinout: PLCC−28
(Top View)
H
L
Min Delay Path
Normal Mode
H
Max Delay Path
V
BB
FTUNE
1
0
0
0
0
0
0
0
IN
4 GATES
8 GATES
16 GATES
IN
1
1
1
1
1
1
1
1
1
1
Q
Q
0
EN
* 1.25
* 1.5
1
1
LINEAR
RAMP
V
EE
CASCADE
LEN
LATCH
Q
LEN
SET MIN
SET MAX
7 BIT LATCH
D
CASCADE
CASCADE
D0
D1
D2
D3
D4
D5
D6
D7
* delays are 25% or 50% longer than
* standard (standard ≈ 80 ps)
Figure 2. Logic Diagram − Simplified
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2
MC10E196, MC100E196
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
8
CC
EE
I
EE
CC
= 0 V
−8
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
−6
V
V
EE
CC
I
I
CC
EE
V ꢁ V
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
0 to +85
A
T
−65 to +150
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
JC
V
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
EE
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E196, MC100E196
Table 4. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 1)
EE
CCx
0°C
25°C
Typ
85°C
Typ
Min
Typ
130
Max
156
Min
Max
156
Min
Max
156
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
130
130
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3980
3050
3830
3050
3.62
2.2
4070
3210
3995
3285
4160
3370
4160
3520
3.74
4.6
4020
3050
3870
3050
3.65
2.2
4105
3210
4030
3285
4190
3370
4190
3520
3.75
4.6
4090
3050
3940
3050
3.69
2.2
4185
3227
4110
3302
4280
3405
4280
3555
3.81
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
3. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 5. 10E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 4)
EE
CCx
0°C
Typ
130
−1020 −930
25°C
Typ
85°C
Typ
Min
Max
156
Min
Max
156
Min
Max
156
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
130
130
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−840
−980
−895
−810
−910
−815
−720
OH
OL
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV
−1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV
IH
IL
−1.38
−2.8
−1.27 −1.35
−1.25 −1.31
−1.19
−0.4
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
−0.4
−2.8
−0.4
−2.8
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.065
0.3
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
5. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
6. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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4
MC10E196, MC100E196
Table 6. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 7)
EE
CCx
0°C
25°C
Typ
85°C
Typ
Min
Typ
130
Max
156
Min
Max
156
Min
Max
179
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
130
150
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3975
3190
3835
3190
3.62
2.2
4050
3295
3975
3355
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4050
3255
3975
3355
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4050
3260
3975
3355
4120
3380
4120
3525
3.74
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
9. V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
Table 7. 100E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 10)
EE
CCx
0°C
Typ
130
25°C
Typ
130
85°C
Typ
150
Min
Max
Min
Max
Min
Max
179
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
156
156
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1025 −950
−880 −1025 −950
−880 −1025 −950
−880
OH
OL
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
IH
IL
−1.38
−1.26 −1.38
−1.26 −1.38
−1.26
−0.4
V
V
BB
Input HIGH Voltage Common Mode Range −2.8
−0.4
−2.8
−0.4
−2.8
IHCMR
(Differential Configuration) (Note 12)
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
11. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
12.V
min varies 1:1 with V , max varies 1:1 with V
.
IHCMR
EE
CC
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5
MC10E196, MC100E196
Table 8. AC CHARACTERISTICS V
= 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 13)
CCx EE
CCx
EE
0°C
25°C
Typ
85°C
Min
Typ
Max
Min
Max
Min
Typ
Max
Symbol
Characteristic
Unit
GHz
ps
f
Maximum Toggle Frequency
>1.0
MAX
t
t
Propagation Delay
PLH
PHL
1210
3320
1250
300
1360
3570
1450
450
1510
3820
1650
700
1240
3380
1275
300
1390
3630
1475
450
1540
3880
1675
700
1440
3920
1350
300
1590
4270
1650
450
1765
4720
1950
700
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE
t
Programmable Range
(max) − t (min)
ps
ps
RANGE
2000
2175
2050
2240
2375
2580
t
PD
PD
Dt
Step Delay (Note 14)
17
34
17.5
35
21
42
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
55
115
250
505
1000
68
105
180
325
620
1190
55
115
250
515
1030
70
105
180
65
140
305
620
1240
84
120
205
136
272
544
1088
140
280
560
1120
168
336
672
1344
325
380
620
1220
740
1450
Lin
Linearity (Note 15)
Duty Cycle Skew
D1
D0
D1
D0
D1
D0
t
ps
SKEW
±30
±30
±30
t
−t
(Note 16)
PHL PLH
t
t
Random Clock Jitter (RMS)
Setup Time
< 5
< 5
< 5
ps
ps
JITTER
s
200
800
200
0
200
800
200
0
200
800
200
0
D to LEN
D to IN (Note 17)
EN to IN (Note 18)
t
t
Hold Time
ps
ps
h
500
0
250
500
0
250
500
0
250
LEN to D
IN to EN (Note 19)
Release Time
R
300
800
800
300
800
800
300
800
800
EN to IN (Note 20)
SET MAX to LEN
SET MIN to LEN
t
Random Clock Jitter (RMS)
Output Rise/Fall Time
< 5
< 5
< 5
ps
ps
jit
t
t
r
f
125
300
225
450
325
650
125
300
225
450
325
650
125
300
225
450
325
650
20−80% (Q)
20−80% (CASCADE)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
14.Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
15.The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the
LSB the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
16.Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18.This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
19.This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
20.This release time is the minimum time that EN must be de−asserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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MC10E196, MC100E196
ANALOG INPUT CHARACTERISTICS
FTUNE = V to V
CC
EE
140
120
100
80
100
90
80
70
60
50
40
30
20
60
40
20
0
10
0
−4.5
−3.5
−2.5
−1.5
−0.5
−5
−4
−3
−2
−1
0
FTUNE VOLTAGE (V)
FTUNE VOLTAGE (V)
Propagation Delay versus FTUNE Voltage
(100E196)
Propagation Delay versus FTUNE Voltage
(10E196)
USING THE FTUNE ANALOG INPUT
The analog FTUNE pin on the E196 device is intended to
add more delay in a tunable gate to enhance the 20 ps
resolution capabilities of the fully digital E195. The level of
resolution obtained is dependent on the number of
increments applied to the appropriate range on the FTUNE
pin.
To provide this further level of resolution (See Logic
Diagram), the FTUNE pin must be capable of adjusting the
additional delay finer than the 20 ps digital resolution. From
the provided graphs one sees that this requirement is easily
achieved as over the entire FTUNE voltage range a 100 ps
additional delay can be achieved. This extra analog range
ensures that the FTUNE pin will be capable even under
worst case conditions of covering the digital resolution.
Typically the analog input will be driven by an external DAC
to provide a digital control with very fine analog output
steps. The final resolution of the device will be dependent on
the width of the DAC chosen.
To determine the voltage range necessary for the FTUNE
input, the graphs provided should be used. As an example if
a tuning range of 40 ps is selected to cover worst case
conditions and ensure coverage of the digital range, from the
100E196 graph a voltage range of −3.25 V to −4.0 V would
be necessary on the FTUNE pin. Obviously there are
numerous voltage ranges which can be used to cover a given
delay range, users are given the flexibility to determine
which one best fits their designs.
one more address line per added E196. Obviously cascading
multiple PDC’s will result in a larger programmable range,
however, this increase is at the expense of a longer minimum
delay.
Figure 3 illustrates the interconnect scheme for
cascading two E196’s. As can be seen, this scheme can
easily be expanded for larger E196 chains. The D7 input of
the E196 is the cascade control pin. With the interconnect
scheme of Figure 3 when D7 is asserted it signals the need
for a larger programmable range than is achievable with a
single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7
of chip #1 above is low the cascade output will also be low
while the cascade bar output will be a logical high. In this
condition the SET MIN pin of chip #2 will be asserted and
thus all of the latches of chip #2 will be reset and the device
will be set at its minimum delay. Since the RESET and SET
inputs of the latches are overriding any changes on the
A0−A6 address bus will not affect the operation of chip #2.
Chip #1 on the other hand will have both SET MIN and
SET MAX de-asserted so that its delay will be controlled
entirely by the address bus A0−A6. If the delay needed is
greater than can be achieved with 31.75 gate delays
(1111111 on the A0−A6 address bus) D7 will be asserted to
signal the need to cascade the delay to the next E196 device.
When D7 is asserted the SET MIN pin of chip #2 will be
de-asserted and the delay will be controlled by the A0−A6
address bus. Chip #1 on the other hand will have its SET
MAX pin asserted resulting in the device delay to be
independent of the A0−A6 address bus.
Cascading Multiple E196’s
To increase the programmable range of the E196 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E196’s without the need for any
external gating. Furthermore this capability requires only
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7
MC10E196, MC100E196
When the SET MAX pin of chip #1 is asserted the D0 and
When cascading multiple PDC’s it will prove more cost
effective to use a single E196 for the Most Significant Bit
(MSB) of the chain while using E195 for the lower order
bits. This is due to the fact that only one fine tune input is
needed to further reduce the delay step resolution.
D1 latches will be reset while the rest of the latches will be
set. In addition, to maintain monotonicity an additional gate
delay is selected in the cascade circuitry. As a result when D7
of chip #1 is asserted the delay increases from 31.75 gates
to 32 gates. A 32 gate delay is the maximum delay setting for
the E196.
ADDRESS BUS (A0−A6)
LINEAR
INPUT
A7
D1
FTUNE
D1
FTUNE
D0
D0
E196
Chip #1
E196
Chip #2
V
V
LEN
LEN
CC
CC
V
V
V
V
CC0
Q
CC0
Q
V
V
EE
EE
IN
IN
IN
IN
INPUT
OUTPUT
Q
Q
CC0
CC0
V
V
BB
BB
Figure 3. Cascading Interconnect Architecture
TO SELECT MULTIPLEXERS
BIT 0
BIT 1
D1
BIT 2
BIT 3
D3
BIT 4
BIT 5
BIT 6
D6
BIT 7
CASCADE
CASCADE
D0
Q0
Q1
D2
Q2
Q3
D4
Q4
D5
Q5
Q6
D7
Q7
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
SET MIN
SET MAX
Figure 4. Expansion of the Latch Section of the E196 Block Diagram
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8
MC10E196, MC100E196
30
1600
1575
Note:
All Taps Selected
SET = H, Temp. = 0°C
25
20
1550
1525
1500
15
10
5
1475
1450
1425
1400
1375
1350
1325
1300
0
−5
−10
−15
−5.5
−5.3
−5.1
−4.9
, (V)
−4.7
−4.5
−4.3
0
0
0
10
20
30 40 50 60
70
80 90 100
V
Temperature (°C)
EE
Figure 5. Change in Delay vs. Change in
Supply Voltage
Figure 6. Delay vs. Temperature (Fixed Path)
4400
4300
4200
4100
4000
3900
3800
3700
3600
2800
2000
1200
85°C
0°C
3600
3500
3400
0
10
20
30 40 50 60
70
80 90 100
32
64
96
128
Temperature (°C)
Tap Delay
Figure 7. Delay vs. Temperature (Max. Delay).
Figure 8. 100E196 Temperature Effects on
Delay.
3900
3400
2900
88
84
80
76
72
68
2400
1900
1400
64
0
10
20
30 40 50 60
70
80 90 100
20
40
60
80
100
120
Temperature (°C)
Tap Selection
Figure 9. Delay vs. Temperature (Per Gate).
Figure 10. E195 Delay Linearity.
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9
MC10E196, MC100E196
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 11. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E196FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E196FNG
PLCC−28
(Pb−Free)
MC10E196FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E196FNR2G
PLCC−28
(Pb−Free)
MC100E196FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E196FNG
PLCC−28
(Pb−Free)
MC100E196FNR2
MC100E196FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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10
MC10E196, MC100E196
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
0.007 (0.180)
T
L−M
N
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T
L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L−M
L−M
N
M
S
S
N
0.007 (0.180)
T
L−M
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T
L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
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11
MC10E196, MC100E196
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC10E196/D
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