MC10EL34DR2G [ONSEMI]
5V ECL ±2, ±4, ±8 Clock Generation Chip; 5V ECL ± 2 ， ± 4 ， ± 8时钟发生器芯片
| 型号： | MC10EL34DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL ±2, ±4, ±8 Clock Generation Chip |
| 文件： | 总8页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EL34, MC100EL34
5VꢀECL ÷2, ÷4, ÷8 Clock
Generation Chip
Description
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
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output edges are all precisely aligned. The V pin, an internally
BB
generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is
16
1
connected to V as a switching reference voltage. V may also
BB
BB
rebias AC coupled inputs. When used, decouple V and V via a
BB
CC
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V should be left open.
BB
SO−16
D SUFFIX
CASE 751B
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip−flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
MARKING DIAGRAMS*
16
1
16
10EL34G
AWLYWW
100EL34G
AWLYWW
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
1
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The 100 Series contains temperature compensation.
WL
YY
WW
G
Features
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• PECL Mode Operating Range:
*For additional marking information, refer to
Application Note AND8002/D.
V
CC
= 4.2 V to 5.7 V with V = 0 V
EE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
• NECL Mode Operating Range:
= 0 V with V = −4.2 V to −5.7 V
V
CC
EE
• Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 10
MC10EL34/D
MC10EL34, MC100EL34
V
EN NC CLK CLK V
MR
V
EE
CC
BB
Table 1. FUNCTION TABLE
16
15
14
13
12
11
10
9
CLK*
EN*
MR*
Function
Z
ZZ
X
L
H
X
L
L
H
Divide
0−3
Reset Q
0−3
D
Q
R
Hold Q
*Pins will default low when left open.
Z = Low-to-High Transition
ZZ = High-to-Low Transition
÷2
Q
÷4
Q
÷8
Q
R
R
R
2
3
8
5
6
1
4
7
Table 2. PIN DESCRIPTION
V
Q0
V
Q1
Q2
Q0
Q1
Q2
CC
CC
Pin
CLK, CLK
EN
Function
ECL Diff Clock Inputs
*All V pins are tied together on the die.
CC
Warning: All V and V pins must be externally connected
to Power Supply to guarantee proper operation.
CC
EE
ECL Sync Enable
ECL Master Reset
ECL Diff ÷2 Outputs
ECL Diff ÷4 Outputs
ECL Diff ÷8 Outputs
Reference Voltage Output
Positive Supply
MR
Figure 1. Logic Diagram and Pinout Assignment
Q0, Q0
Q1, Q1
Q2, Q2
V
V
V
BB
CC
EE
Negative Supply
NC
No Connect
Table 3. ATTRIBUTES
Characteristics
Value
75 KW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charge Device Model
> 1 KV
> 100 V
> 2 KV
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
191 Devices
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
MC10EL34, MC100EL34
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
8
CC
EE
I
EE
CC
= 0 V
−8
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
I
CC
EE
V w V
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SO−16
SO−16
130
75
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
SO−16
33 to 36
°C/W
°C
JC
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
265
265
Pb−Free <2 to 3 sec @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 10EL SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0 V (Note 2)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
39
Min
Typ
Max
39
Min
Typ
Max
39
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3920
3050
3770
3050
3.57
3.0
4010
3200
4110
3350
4110
3500
3.7
4020
3050
3870
3050
3.65
3.0
4105
3210
4190
3370
4190
3520
3.75
4.6
4090
3050
3940
3050
3.69
3.0
4185
3227
4280
3405
4280
3555
3.81
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 4)
4.6
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.3
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.06 V / −0.5 V.
CC
EE
3. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1 V.
PP
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3
MC10EL34, MC100EL34
Table 6. 10EL SERIES NECL DC CHARACTERISTICS V = 0 V; V = −5.0 V (Note 5)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
39
Min
Typ
Max
39
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
39
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1080 −990
−890
−980
−895
−810
−910
−815
−720
OH
OL
−1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV
−1230
−1950
−1.43
−2.0
−890 −1130
−1500 −1950
−1.30 −1.35
−810 −1060
−1480 −1950
−1.25 −1.31
−720
mV
IH
−1445 mV
IL
−1.19
−0.4
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 7)
−0.4
−2.0
−0.4
−2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.3
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +0.06 V / −0.5 V.
CC
EE
6. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1 V.
PP
Table 7. 100EL SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0 V (Note 8)
CC
−40°C
Typ
EE
25°C
85°C
Min
Max
39
Min
Typ
Max
39
Min
Typ
Max
42
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
V
I
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3915
3170
3835
3190
3.62
2.2
3995
3305
4120
3445
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4045
3295
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4050
3295
4120
3380
4120
3525
3.74
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V . V can vary +0.8 V / −0.5 V.
CC
EE
9. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
10. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1 V.
PP
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4
MC10EL34, MC100EL34
Table 8. 100EL SERIES NECL DC CHARACTERISTICS V = 0 V; V = −5.0 V (Note 11)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
39
Min
Typ
Max
42
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
39
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
−1085 −1005
−880
−1025
−955
−880
−1025
−955
−880
OH
OL
−1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
Input HIGH Voltage (Single−Ended) −1165
Input LOW Voltage (Single−Ended) −1810
−880
−1165
−880
−1165
−880
mV
IH
−1475 −1810
−1475 −1810
−1475 mV
IL
Output Voltage Reference
−1.38
−2.8
−1.26
−0.4
−1.38
−2.8
−1.26
−0.4
−1.38
−2.8
−1.26
−0.4
V
V
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V can vary +0.8 V / −0.5 V.
CC
EE
12.Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
13. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1 V.
PP
Table 9. AC CHARACTERISTICS V = 5.0 V; V = 0.0 V or V = 0.0 V; V = −5.0 V (Note 14)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
GHz
ps
f
Maximum Toggle Frequency
1.1
1.1
1.1
max
t
t
Propagation
Delay to
Output
CLK to Q0
CLK to Q1,2
MR to Q
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
970
910
790
1210
1150
1090
PLH
PHL
t
t
t
t
t
Within-Device Skew (Note 15)
Cycle−to−Cycle Jitter
Setup Time EN
100
1.0
100
1.0
100
1.0
ps
ps
ps
ps
ps
mV
ps
SKEW
JITTER
S
400
250
400
150
225
400
250
400
150
225
400
250
400
150
225
Hold Time EN
H
Set/Reset Recovery
Input Swing (Note 16)
200
200
200
RR
V
1000
475
1000
475
1000
475
PP
t
t
Output Rise/Fall Times Q
(20% − 80%)
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.10 Series: V can vary +0.06 V / −0.5 V.
EE
100 Series: V can vary +0.8 V / −0.5 V.
EE
15.Within-device skew is defined as identical transitions on similar paths through a device.
16.V min is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
PP
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5
MC10EL34, MC100EL34
There are two distinct functional relationships between the Master Reset and Clock:
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the
outputs will follow the first ensuing clock rising edge.
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
CASE 2: If the MR is de−asserted (H−L), after the Clock has transitioned low, the
outputs will follow the second ensuing clock rising edge.
Figure 2. Timing Diagrams
The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal
divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge
of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-
tionships.
T
T
RR
RR
CLOCK
CLOCK
MR
MR
OUTPUT
OUTPUT
CASE 1
CASE 2
Figure 3. Reset Recovery Time
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6
MC10EL34, MC100EL34
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
MC10EL34D
Package
Shipping
SO−16
48 Units / Rail
48 Units / Rail
MC10EL34DG
SO−16
(Pb−Free)
MC10EL34DR2
SO−16
2500 / Tape & Reel
2500 / Tape & Reel
MC10EL34DR2G
SO−16
(Pb−Free)
MC100EL34D
SO−16
48 Units / Rail
48 Units / Rail
MC100EL34DG
SO−16
(Pb−Free)
MC100EL34DR2
SO−16
2500 / Tape & Reel
2500 / Tape & Reel
MC100EL34DR2G
SO−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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7
MC10EL34, MC100EL34
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC10EL34/D
相关型号：
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