MC10ELT25DR2G [ONSEMI]
−5 V Differential ECL to TTL Translator; -5 V差分ECL至TTL转换器
| 型号： | MC10ELT25DR2G |
| 厂家： | 
ONSEMI |
| 描述： | −5 V Differential ECL to TTL Translator |
| 文件： | 总8页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10ELT25, MC100ELT25
−5 VꢀDifferential ECL to TTL
Translator
Description
The MC10ELT/100ELT25 is a differential ECL to TTL translator.
Because ECL levels are used, a +5 V, −5.2 V (or −4.5 V) and ground
are required. The small outline 8-lead package and the single gate of
the ELT25 makes it ideal for those applications where space,
performance and low power are at a premium.
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MARKING DIAGRAMS*
The V pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
BB
8
8
8
HLT25
ALYW
G
KLT25
ALYW
G
1
differential input is connected to V as a switching reference voltage.
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
BB
SOIC−8
D SUFFIX
CASE 751
1
1
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
Features
8
8
1
8
• 2.6 ns Typical Propagation Delay
• 100 MHz F
• 24 mA TTL Outputs
• Flow Through Pinouts
1
HT25
KT25
ALYWG
ALYWG
CLK
MAX
TSSOP−8
DT SUFFIX
CASE 948R
G
G
1
• Operating Range: V = 4.5 V to 5.5 V with GND = 0 V;
CC
V
EE
= −4.2 V to −5.7 V with GND = 0 V
• Internal Input 50 KW Pulldown Resistors
• Q Output will default HIGH with inputs open or < 1.3 V
• Pb−Free Packages are Available
1
4
1
4
DFN8
MN SUFFIX
CASE 506AA
H
K
= MC10
= MC100
A
L
= Assembly Location
= Wafer Lot
5F = MC10
2U = MC100
Y
W
G
= Year
= Work Week
= Pb−Free Package
M
= Date Code
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 12
MC10ELT25/D
MC10ELT25, MC100ELT25
Table 1. PIN DESCRIPTION
V
1
2
8
7
V
CC
EE
Pin
Function
ECL Differential Inputs
TTL
D, D
Q
D
Q
TTL Output
ECL
V
V
V
Reference Voltage Output
Positive Supply
Negative Supply
Ground
BB
CC
EE
D
3
4
6
5
NC
GND
V
BB
GND
NC
No Connect
Figure 1. 8−Lead Pinout (Top View) and Logic
EP
Exposed pad must be connected to a sufficient
thermal conduit. Electrically connect to the most
negative supply or leave floating open.
Diagram
Table 2. ATTRIBUTES
Characteristics
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
> 1 kV
> 400 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
38 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
GND = 0 V
Condition 2
= −5.0 V
Rating
Unit
V
V
CC
V
EE
V
IN
V
V
7
EE
Negative Power Supply
Input Voltage
GND = 0 V
GND = 0 V
= +5.0 V
−8
V
CC
0 to V
V
EE
I
V
Sink/Source
± 0.5
mA
°C
°C
BB
BB
T
Operating Temperature Range
−40 to +85
−65 to +150
A
T
Storage Temperature Range
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
TSSOP−8
41 to 44 ± 5%
°C/W
JC
JA
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC10ELT25, MC100ELT25
Table 4. 10ELT SERIES NECL INPUT DC CHARACTERISTICS V = 5.0 V; V = −5.0 V; GND = 0 V (Note 2)
CC
EE
−40°C
25°C
85°C
Min
Input HIGH Voltage (Single−Ended) (Note 3) −1230
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
V
V
V
−890 −1130
−1500 −1950
−1.30 −1.35
−810 −1060
−1480 −1950
−1.25 −1.31
−720
mV
IH
Input LOW Voltage (Single−Ended) (Note 3)
−1950
−1.43
−2.8
−1445 mV
IL
Output Voltage Reference
−1.19
V
V
BB
Input HIGH Voltage Common Mode Range
(Differential) (Notes 3 and 4)
0.0
−2.8
0.0
−2.8
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
mA
IH
0.5
0.5
0.3
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input parameters vary 1:1 with GND. V can vary +0.06 V to −0.5 V.
EE
3. TTL output R = 500 W to GND
L
4. V
min varies 1:1 with V , V
max varies 1:1 with GND.
IHCMR
IHCMR
EE
Table 5. 100ELT SERIES NECL INPUT DC CHARACTERISTICS V = 5.0 V; V = −5.0 V; GND = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
85°C
Min
Input HIGH Voltage (Single−Ended) (Note 6) −1165
Typ
Max
Min
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
V
V
V
−880 −1165
−1475 −1810
−1.26 −1.38
−880 −1165
−1475 −1810
−1.26 −1.38
−880
mV
IH
Input LOW Voltage (Single−Ended) (Note 6)
−1810
−1.38
−2.8
−1475 mV
IL
Output Voltage Reference
−1.26
V
V
BB
Input HIGH Voltage Common Mode Range
(Differential) (Notes 6 and 7)
0.0
−2.8
0.0
−2.8
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with GND. V can vary +0.8 V to −0.5 V.
EE
6. TTL output R = 500 W to GND
L
7. V
min varies 1:1 with V , V
max varies 1:1 with GND.
IHCMR
IHCMR
EE
Table 6. TTL OUTPUT DC CHARACTERISTICS V = 4.5 V to 5.5 V; T = −40°C to +85°C
CC
A
Symbol
Characteristic
Output HIGH Voltage
Condition
= −3.0 mA
Min
Typ
Max
Unit
V
V
OH
V
OL
I
I
2.4
OH
Output LOW Voltage
= 24 mA
0.5
16
V
OL
I
I
I
I
Power Supply Current
11
13
15
mA
mA
mA
mA
CCH
CCL
EE
Power Supply Current
18
Negative Power Supply Current
Output Short Circuit Current
21
−150
−60
OS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10ELT25, MC100ELT25
Table 7. AC CHARACTERISTICS V = 5.0 V; V = −5.0 V; GND= 0 V (Note 8 and Note 9)
CC
EE
−40°C
25°C
Typ
100
85°C
Min
Typ
Max
Min
Max
Min
Typ
Max
Symbol
Characteristic
Unit
MHz
ns
f
t
t
t
Maximum Toggle Frequency
Propagation Delay @ 1.5 V
Propagation Delay @ 1.5 V
Random Clock Jitter (RMS)
max
1.7
2.6
3.6
4.1
1.7
2.6
3.6
4.1
1.7
2.6
3.6
4.1
PLH
ns
PHL
35
ps
ns
JITTER
t
r
t
f
Output Rise/Fall Times QTTL
1.9
2.3
10% − 90%
V
PP
Input Swing (Note 10)
200
1000
200
1000
200
1000
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. V can vary ± 0.25 V.
CC
EE
V
can vary +0.06 V to −0.5 V for 10ELT; V can vary +0.8 V to −0.5 V for 100ELT.
EE
9. R = 500 W to GND and C = 20 pF to GND. Refer to Figure 2.
L
L
10.V (min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈ 40.
PP
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
C *
L
R
L
*C includes
L
fixture
capacitance
AC TEST LOAD
GND
Figure 2. TTL Output Loading Used for Device Evaluation
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4
MC10ELT25, MC100ELT25
ORDERING INFORMATION
Device
†
Package
Shipping
MC10ELT25D
SOIC−8
98 Units / Rail
98 Units / Rail
MC10ELT25DG
SOIC−8
(Pb−Free)
MC10ELT25DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10ELT25DR2G
SOIC−8
(Pb−Free)
MC10ELT25DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC10ELT25DTG
TSSOP−8
(Pb−Free)
MC10ELT25DTR2
MC10ELT25DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC10ELT25MNR4
MC10ELT25MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
MC100ELT25D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100ELT25DG
SOIC−8
(Pb−Free)
MC100ELT25DR2
MC100ELT25DR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100ELT25DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100ELT25DTG
TSSOP−8
(Pb−Free)
MC100ELT25DTR2
MC100ELT25DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100ELT25MNR4
MC100ELT25MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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5
MC10ELT25, MC100ELT25
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC10ELT25, MC100ELT25
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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7
MC10ELT25, MC100ELT25
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
8 X b
0.05
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC10ELT25/D
相关型号：
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