MC10EP139DWG [ONSEMI]
3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation Chip; 3.3V / 5V ECL ± 2/4， ±4 /5/6时钟发生器芯片
| 型号： | MC10EP139DWG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation Chip |
| 文件： | 总14页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP139, MC100EP139
3.3V / 5VꢀECL ÷2/4, ÷4/5/6
Clock Generation Chip
Description
The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single−ended ECL or, if positive power supplies are used,
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MARKING
DIAGRAMS*
LVPECL input signals. In addition, by using the V output, a sinusoidal
BB
source can be AC coupled into the device. If a single−ended input is to be
HEP or KEP
used, the V output should be connected to the CLK input and bypassed
to ground via a 0.01 mF capacitor.
BB
139
ALYWG
G
1
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. The internal enable flip−flop is clocked on the
falling edge of the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
TSSOP−20
DT SUFFIX
CASE 948E
20
MCXXXEP139
AWLYYWWG
1
Upon start−up, the internal flip−flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and the
SOIC−20
DW SUFFIX
CASE 751D
1
20
÷4/5/6 outputs of a single device. All V
and V pins must be
1
CC
EE
XXXX
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
EP139
ALYWG
G
QFN−20
MN SUFFIX
CASE 485E
Features
• Maximum Frequency > 1.0 GHz Typical
• 50 ps Output−to−Output Skew
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
HEP
KEP
XXX
A
L,WL
Y, YY
= MC10EP
with V = 0 V
= MC100EP
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
W, WW = Work Week
• Safety Clamp on Inputs
G or G = Pb−Free Package
• Synchronous Enable/Disable
(Note: Microdot may be in either location)
• Master Reset for Synchronization of Multiple Chips
*For additional marking information, refer to
Application Note AND8002/D.
• V Output
BB
• Pb−Free Packages are Available
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 7
MC10EP139/D
MC10EP139, MC100EP139
V
Q0
Q0 Q1 Q1
18 17 16
Q2 Q2 Q3 Q3
15 14 13 12
V
EE
CC
Table 1. PIN DESCRIPTION
PIN
20
19
11
FUNCTION
CLK*, CLK*
EN*
ECL Differential Clock Inputs
ECL Sync Enable
MR*
ECL Master Reset
1
2
3
4
5
6
7
8
9
10
V
ECL Reference Output
BB
Q0, Q1, Q0, Q1
Q2, Q3, Q2, Q3
DIVSELa*
ECL Differential B2/4 Outputs
ECL Differential B4/5/6 Outputs
ECL Frequency Select Input B2/4
ECL Frequency Select Input B4/5/6
ECL Frequency Select Input B4/5/6
ECL Positive Supply
Warning: All V and V pins must be externally connected to
Power Supply to guarantee proper operation.
CC
EE
DIVSELb0*
DIVSELb1
Figure 1. 20−Lead Pinout (Top View)
V
V
CC
EE
ECL Negative Supply
EP
Exposed Pad
*Pins will default low when left open.
Exposed Pad
EN
20
V
V
Q0
17
Q0
16
CC
CC
19
18
DIVSELb0
CLK
1
2
3
4
5
15
14
13
12
11
Q1
Q1
MC10/100EP139
CLK
Q2
Q2
Q3
V
BB
MR
6
7
8
9
10
V
DIVSELb1DIVSELa V
Q3
EE
CC
NOTE: The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to V
.
EE
Figure 1. QFN−20 Pinout (Top View)
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2
MC10EP139, MC100EP139
DIVSELa
Q0
CLK
CLK
÷2/4
Q0
Q1
R
Q1
Q2
EN
÷4/5/6
Q2
Q3
R
MR
DIVSELb0
DIVSELb1
Q3
V
EE
Figure 2. Logic Diagram
Table 2. FUNCTION TABLES
CLK
EN
MR
Function
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0:3
Reset Q0:3
Z = Low−to−High Transition
ZZ = High−to−Low Transition
DIVSELa
Q0:1 Outputs
L
H
Divide by 2
Divide by 4
DIVSELb0 DIVSELb1
Q2:3 Outputs
L
H
L
L
L
H
H
Divide by 4
Divide by 6
Divide by 5
Divide by 5
H
CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
Figure 3. CLK and OUTPUT Timing Diagram
CLK
RESET
Q (÷n)
t
RR
Figure 4. Timing Diagram
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3
MC10EP139, MC100EP139
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 100 V
> 2 kV
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−20
TSSOP−20
QFN−20
Level 1
Level 1
N/A
Level 3
Level 1
Level
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
758 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
V
V
6
CC
EE
I
EE
CC
= 0 V
−6
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
Sink/Source
BB
0.5
mA
°C
BB
T
A
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
T
stg
°C
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
140
100
°C/W
°C/W
JA
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−20
23 to 41
°C/W
JC
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
SOIC−20
SOIC−20
90
60
°C/W
°C/W
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
q
q
Thermal Resistance (Junction−to−Case)
SOIC−20
33 to 35
°C/W
JC
JA
QFN−20
QFN−20
90
60
°C/W
°C/W
500 lfpm
q
Thermal Resistance (Junction−to−Case)
Standard Board
QFN−20
33 to 35
°C/W
°C
JC
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
265
265
Pb−Free <2 to 3 sec @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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4
MC10EP139, MC100EP139
Table 5. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
65
Typ
82
Max
105
Min
65
Max
105
Min
65
Max
105
Unit
mA
mV
mV
mV
mV
mV
V
I
83
84
EE
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2165
1365
2090
1365
1790
2.0
2290
1490
2415
1615
2415
1690
1990
3.3
2230
1430
2155
1460
1855
2.0
2355
1555
2480
1680
2480
1755
2055
3.3
2290
1490
2215
1490
1915
2.0
2415
1615
2540
1740
2540
1815
2115
3.3
OH
OL
V
V
V
V
V
IH
IL
1890
1955
2015
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
65
Typ
82
Max
105
Min
65
Max
105
Min
65
Max
105
Unit
mA
mV
mV
mV
mV
mV
V
I
83
84
EE
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3865
3065
3790
3065
3490
2.0
3990
3190
4115
3315
4115
3390
3690
5.0
3930
3130
3855
3130
3555
2.0
4055
3255
4180
3380
4180
3455
3755
5.0
3990
3190
3915
3190
3615
2.0
4115
3315
4240
3440
4240
3515
3815
5.0
OH
OL
V
V
V
V
V
IH
IL
3590
3655
3715
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP139, MC100EP139
Table 7. 10EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
Typ
82
25°C
Typ
83
85°C
Typ
84
Symbol
Characteristic
Min
65
Max
Min
Max
Min
Max
105
Unit
mA
mV
mV
mV
mV
mV
V
I
Power Supply Current
105
65
105
65
EE
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
OH
OL
V
V
V
V
V
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
IH
−1485
IL
−1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
0.0
IHCMR
EE
EE
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 11)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
70
Max
Min
70
Max
105
Min
75
Max
110
Unit
mA
mV
mV
mV
mV
mV
V
I
83
100
2405
1605
2420
1675
1975
3.3
87
90
EE
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2155
1355
2075
1355
1775
2.0
2280
1480
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
OH
OL
V
V
V
V
V
IH
IL
1875
1875
1875
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
12.All loading with 50 W to V − 2.0 V.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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6
MC10EP139, MC100EP139
Table 9. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 14)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
70
Max
Min
70
Max
105
Min
75
Max
110
Unit
mA
mV
mV
mV
mV
mV
V
I
85
100
4105
3305
4120
3375
3675
5.0
90
95
EE
V
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3855
3055
3775
3055
3475
2.0
3980
3180
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
OH
OL
V
V
V
V
V
IH
IL
3575
3575
3575
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
15.All loading with 50 W to V − 2.0 V.
CC
16.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 17)
CC
EE
−40°C
25°C
Typ
90
85°C
Typ
95
Symbol
Characteristic
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
mV
V
I
Power Supply Current
70
85
100
70
105
75
110
EE
V
Output HIGH Voltage (Note 18)
Output LOW Voltage (Note 18)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
V
V
V
V
V
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
IH
−1625
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
0.0
IHCMR
EE
EE
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
.
CC
18.All loading with 50 W to V − 2.0 V.
CC
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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7
MC10EP139, MC100EP139
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or
V = 3.0 V to 5.5 V; V = 0 V (Note 20)
CC EE
CC
EE
−40°C
Typ
25°C
Typ
> 1
85°C
Typ
> 1
Symbol
Characteristic
Maximum Frequency
(See Figure 5 F /JITTER)
Min
Max
Min
Max
Min
Max
Unit
f
> 1
GHz
max
max
t
t
,
Propagation Delay
CLK, Q (Diff)
MR, Q
550
700
700
800
800
900
600
700
750
850
900
1000
675
800
825
950
975
1100
ps
PLH
PHL
t
t
Reset Recovery
Setup Time
200
100
200
100
200
100
ps
ps
RR
s
EN, CLK
DIVSEL, CLK
200
400
120
180
200
400
120
180
200
400
120
180
t
Hold Time
CLK, EN
CLK, DIVSEL
100
200
50
140
100
200
50
140
100
200
50
140
ps
h
t
t
Minimum Pulse Width
Within Device Skew
MR
550
450
550
450
550
450
ps
ps
PW
Q, Q
50
200
100
300
50
200
100
300
50
200
100
300
SKEW
Device−to−Device Skew (Note 21)
t
Random Clock Jitter (RMS)
0.2
800
180
< 1.0
1200
250
0.2
800
190
< 1.0
1200
275
0.2
800
215
< 1.5
1200
300
ps
mV
ps
JITTER
(See Figure 5 F
/JITTER)
max
V
Input Voltage Swing (Differential Con-
figuration)
150
110
150
125
150
150
PP
t
t
Output Rise/Fall Times
Q, Q
r
f
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
21.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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8
MC10EP139, MC100EP139
900
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
(JITTER)
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
Figure 5. B2, Fmax/Jitter
900
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
(JITTER)
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
Figure 6. B5, Fmax/Jitter
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9
MC10EP139, MC100EP139
900
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
(JITTER)
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
Figure 7. B4, Fmax/Jitter
900
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
(JITTER)
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
Figure 8. B6, Fmax/Jitter
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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10
MC10EP139, MC100EP139
ORDERING INFORMATION
Device
†
Package
Shipping
MC10EP139DT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOIC−20
75 Units / Rail
75 Units / Rail
MC10EP139DTG
MC10EP139DTR2
MC10EP139DTR2G
MC10EP139DW
2500 / Tape & Reel
2500 / Tape & Reel
38 Units / Rail
MC10EP139DWG
SOIC−20
(Pb−Free
38 Units / Rail
MC10EP139DWR2
MC10EP139DWR2G
SOIC−20
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20
(Pb−Free
MC10EP139MNG
QFN−20
(Pb−Free)
92 Units / Rail
MC10EP139MNTXG
QFN−20
(Pb−Free)
3000 / Tape & Reel
MC100EP139DT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOIC−20
75 Units / Rail
75 Units / Rail
MC100EP139DTG
MC100EP139DTR2
MC100EP139DTR2G
MC100EP139DW
MC100EP139DWG
2500 / Tape & Reel
2500 / Tape & Reel
38 Units / Rail
SOIC−20
(Pb−Free
38 Units / Rail
MC100EP139DWR2
MC100EP139DWR2G
SOIC−20
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20
(Pb−Free
MC100EP139MNG
QFN−20
(Pb−Free)
92 Units / Rail
MC100EP139MNTXG
QFN−20
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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11
MC10EP139, MC100EP139
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
V
0.10 (0.004)
T U
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
MC10EP139, MC100EP139
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
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13
MC10EP139, MC100EP139
PACKAGE DIMENSIONS
QFN−20
CASE 485E−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
−X−
A
M
−Y−
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
N
B
MILLIMETERS
DIM MIN MAX
4.00 BSC
4.00 BSC
INCHES
MIN MAX
A
B
C
D
E
F
0.157 BSC
0.157 BSC
0.25 (0.010) T
0.25 (0.010) T
R
0.80
1.00
0.35
2.85
2.85
0.031
0.039
0.014
0.112
0.112
0.23
2.75
2.75
0.009
0.108
0.108
G
H
J
0.50 BSC
0.020 BSC
1.38
1.43
0.054
0.056
J
0.20 REF
0.008 REF
C
K
L
0.00
0.35
0.05
0.45
0.000
0.014
0.002
0.018
SEATING
PLANE
−T−
0.08 (0.003) T
K
M
N
P
R
2.00 BSC
2.00 BSC
0.079 BSC
0.079 BSC
E
1.38
0.60
1.43
0.80
0.054
0.024
0.056
0.031
H
G
L
6
10
5
1
11
F
15
20
16
P
D NOTE 3
M
0.10 (0.004)
T X Y
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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MC10EP139/D
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